VHDL语言数字系统中英文对照外文翻译文献

中英文对照外文翻译

(文档含英文原文和中文翻译)

DESIGNING A DIGITAL SYSTEM WITH VHDL

Abstract:In this paper a digital system designing with VHDL is presented. Here are exposed sequentially all the phases of the very digital system's designing. The main methods are also on show here. The project descriptions’ types are presented. The stress is put on the use of VHDL for synthesis of structural and behavioral models.

For creating the project of the chosen digital system an integrated system WebPack was used, as well as ModelSIm XE II for the model's simulation.

Keywords: Design, VHDL, digital systems, model, WebPack

1. INTRODUCTION

The digital systems are complex ones, consisting of lots of components. As far as the automated design of such systems is concerned, methods for designing time reducing and limiting the complexity of the task are sought out and applied. A method of the kind is connected with the decomposition and hierarchy principles. The decomposition of the systems is realized in a way, which differentiates functionally independent modules.

A digital system can be described as a module with inputs and/or outputs. The electrical values on the outputs are some function of the values on the inputs.

One way of describing the function of a module is to describe how it is composed of sub-modules. Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signal s. This kind of description is called a structural description.

In many cases, it is not appropriate to describe a module structurally. One such case is a module, which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioral description.

Usually, for structural and behavioral description, either Verilog or VHDL is used. In this paper a designing with VHDL is presented. Here are exposed sequentially all the phases of the very digital system's designing. The main methods are also on show here. The project descriptions’ ty pes are presented. The stress is put on the use of VHDL for synthesis of structural and behavioral models. Here are presented several VHDL models of computer systems’ components.

2. METHODS AND STAGES IN DIGITAL SYSTEMS’ DESIGN

In digital systems’ design, as well as design of complex systems, a couple of methods are in use:

? top - down designing;

? up - down designing.

In top - down designing the building up of the system is usually started from below in upright direction through elaboratin g the element blocks’ schemes, assembled later to form the whole product.

An advantage of this method is the use of representation on functional block level and the lower, the structural level, is addressed only during the error check simulations within the project.

The up-down designing starts with a specification on the highest level. After that, the project is being decomposed into functional blocks and the requirements for the income and outcome time proportions are specified. The functional models are described through behavioral models or by models on register levels and are subsequently simulated.

Some of the advantages of the methods are:

? аn easier execution of the task’s specifications;

? иt allows a projects’ check on system level,without tackling the structural details;

? The project’s check is done, with no regard to the technology of its realization.

That allows that the choice of technology be made on a later stage of the designing

project.

The most effective up-down designing method is the use of an abstract description of the scheme and the sequential details specifying of the different hierarchy levels’ description.

The digital systems’ design goes through the next stages:

? Specification;

? Functional (electrical) designing;

? Physical designing;

? Manufacturing;

? Testing.

Through specification the product parameters, necessary for its proper destination, are determined.

Through the functional (electrical) designing, the electrical scheme, responsible for the functions and parameters of the product, in terms of the specification, is elaborated.

The behavioral stage serves as a description for the scheme as a system, and its entries and exits are marked out. In most of the cases, VHDL models are used.

The Functional (electrical) designing deals with main functional blocks’ elaboration. Usually a detailed VHDL description of the functional block is made and being checked by a VHDL simulation.

With the increasing complexity of the projects, for the elaboration on structural level, the technique of synthesis is applied. It allows that the scheme with logical elements be synthesized from a VHDL description. Through logical description details such as charging, elements’ delay, are specified and crucial methods and problems with time scattering of signals are defined.

The Physical designing stages strongly depend on technology. The common task is concerned with the deploying of the logical elements and defining (tracing) their interrelations.

Provided that for the product realization PLD, CPLD or FPGA chips are used, then the result of the physical designing represents a configuration file for designing the chosen device’s resources.

The testing of the project represents a number of procedures, used by designers, to provide: ?adequacy between project and specification;

?the execution of the project in terms of the chosen technology.

The designing process is usually iterative, including pre-designing of given parts, until the intended indicators are obtained.

For the tasks of testing in electrical designing (the functionality of the product and its electrical parameters), simulations are used.

The simulation on behavioral level defines how the product will run, before its actual compounding blocks are chosen. For working out of the behavioral models, the hardware description languages are used (VHDL, Verilog and others).

Through simulation, on a logical primitives level, the schemes are built up with basic logical elements “AND-NO”, “OR-NO”, inv ertors and triggers and are being simulated in order to find out irrelevances with their expected acting.

In functional testing, the delays are not concerned or they are supposed similar for all logical elements.

Error identification after the physical design

After topology’s final elaboration are made the next procedures:

? check out of the tech norms throughout manufacturing;

? check out for the project’s authenticity.

The tech norms for manufacturing are specific for each technological process.

The authenticity verification of the project aims to guarantee the product’s proper working. It includes:

? finding out the interconnection of the scheme;

? finding out the parasite components of the topology.

3. TYPES OF DESIGN DESCRIPTIONS

Through the designing process, three types of design description are in use:

? behavioral;

? structural;

? physical.

The behavioral description tackles the system as if it were a kind of “black box” with its entrances and exits, with no regard to its structure. The aim is to ignore the redundant details and to concentrate on the specification of the necessary for the functions, which are to be done by the product. On this stage, languages for the apparatus part are used HDL (Hardware Description Languages) - VHDL, Verilog and others.

The structural description defines the way that the system is to be built up. Here, the system’s structure, made of blocks and their interrelations, is tackled. The subsystems, which are to provide its functional execution, as well as their detailed description for analysis of the operational speed, charging and so on, are defined. The structural description can be presented by languages for the description of the hardware, as well as by electrical schemes.

The design process is connected with the transformations of the systems’ descriptions and their sequential details specification. Decomposition from behavioral to structural description can be realized on a number of levels in a hierarchy. From the highest to the lowest, these levels can be outlined as it follows:

? system level;

? functional level;

? logical level;

? scheme level.

On the highest system level, the system’s behavior is represented by algorithms that describe its functions. In order that these functions be executed, the architecture of the system is worked out, including microprocessors, memories, main boards and other structural components.

On the lower level, the system’s behavior is described by Bolivia e quations. For their execution, logical elements and triggers are used.

4. USE OF VHDL FOR SYNTHESIS OF STRUCTURAL AND BEHAVIORAL MODELS

VHDL is a Hardware Description Language for describing digital system [2].

VHDL is designed to full a number of needs in the design process.

VHDL contains a number of facilities for modifying the state of objects and controlling the flow of execution of modules.

In VHDL, an entity is such a module which may be used as a component in a design, or which may be the top-level module of the design. The entity declarative part may be used to declare items, which are to be used in the implementation of the entity.

Once an entity has had its interface specified in an entity declaration, one or more implementations of the entity can be described in architecture bodies. Each architecture body can describe a different view of the entity.

The declarations in the architecture body define items that will be used to construct the design description.

Signals are used to connect sub modules in a design. The sub modules in an architecture body can be described as blocks. A block is a unit of module structure, with its own interface,

connected to other blocks or ports by signals. A signal assignment schedules one or more transactions to a signal (or port).

The primary unit of behavioral description in VHDL is the process. When more than one process is activated at the same time, they execute concurrently.

A process statement which can be used in an architecture body or block. The declarations define items which can be used locally within the process.

A process may contain a number of signal assignment statements for a given signal, which together form a driver for the signal.

VHDL descriptions write them in a design file. After then invoke a compiler to analyze them and insert them into a design library. A number of VHDL constructs may be separately analyzed for inclusion in a design library. These constructs are called library units. A design file may contain a number of library units.

The behavioral model represents a functional interpretation of the designed digital system. The hardware of the digital device is regarded as a kind of a discreet system. Its behavior is described as a number of operations. These operations are applied within the system’s database. Within the creation of behavioral VHDL models, operations are described by processes and their interconnections-by signals. On fig 1 is presented a VHDL model of a linear decipherer.

library IEEE;

use IEEE.std_logic_1164.all;

entity DESHIF is

port (x1,x2,x3 in: std_logic;

J: out std_logic_vector(0 to 7));

end DESHIF;

arhitecture STRUCTURAL of DESHIF is

component AND3

port (I1,I2,I3: in std_logic;

O1: out std_logic);

end component;

component NOT1

port (I1: in std_logic;

O1: out std_logic);

end component;

signal a,b,c: std_logic;

begin

U1: NOT1 port map (I1=>x1,O1=>a);

U2: NOT1 port map (I1=>x2,O1=>b);

U3: NOT1 port map (I1=>x3,O1=>c);

U4: AND3 port map (I1=>a,I2=>b,I3=>c,O1=>J(0));

U5: AND3 port map (I1=>a,I2=>b,I3=>x3,O1=>J(1));

U6: AND3 port map (I1=>a,I2=>x2,I3=>c,O1=>J(2));

U7: AND3 port map (I1=>a,I2=>x2,I3=>x3,O1=>J(3));

U8: AND3 port map (I1=>x1,I2=>b,I3=>c,O1=>J(4));

U9: AND3 port map (I1=>x1,I2=>b,I3=>x3,O1=>J(5));

U10: AND3 port map (I1=>x1,I2=>x2,I3=>c,O1=>J(6));

U11: AND3 port map (I1=>x1,I2=>x2,I3=>x3,O1=>J(7));

end STRUCTURAL;

architecture DATA_FLOW of DESHIF is

signal T1,T2,T3: bit;

begin

T1<= not x1;

T2<= not x2;

T3<= not x3;

F1<=T1 and T2 and T3;

F2<=T1 and T2 and x3;

F3<=T1 and x2 and T3;

F4<=T1 and x2 and x3;

F5<=x1 and T2 and T3;

F6<=x1 and T2 and x3;

F1<=x1 and x2 and T3;

F1<=x1 and x2 and x3;

end DATA_FLOW;

fig.1 VHDL code of a linear decipherer

Structural VHDL models ar e means for reflecting the project’s hierarchy. They are built up by decomposition of digital systems of functionally interconnected parts. These parts are presented as components, and their interconnections are realized through signals. These signals enter and exit the components via ports.

For example, within the designing of the digital module, presented on [2], its structural model has three main components-counter, decoder and light-diode seven-segment display. On fig.2 is shown a part of the structural model, synthesized in WebPack.

Fig.2 . VHDL structural description

The simulation starts with an initialization phas e, and then proceeds by repeating a two-stage simulation cycl e. In the initialization phase, all signals are given initial values, the simulation time is set to zero, and each module’s behavior program is executed. This usually results in transactions being scheduled on output signals for some later time.

The purpose of the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monito r. The monitor allows signals and other state information to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger.

The computer-synthesized models of the structure and behavior of the digital systems are used for the elaboration of project units.

5. CONCLUSION

With the increasing complexity of the projects, structural presentation on a logical elements’ level, becomes a hard, even impossible. Therefore, a higher abstraction level description would allow optimal results to be reached, such as consummation, characteristics, size and price.

The hardware description language VHDL is quite suitable for purposes of that kind. It can be used for a high-level behavioral description, as well as for detailed structural description.

This language provides:

a standard way for documenting the project;

? means for creation of abstract simulation models, which can be used by each VHDL-simulator;

? possibility for an automatic synthesis of the electrical scheme from the project’s abstract description.

The VHDL language allows the elaboration of a complete functional structural model of the specialized integral scheme, which can be simulated in order to assess its adequacy in terms of the specification’s requirements. Thus, a higher quality of the project is guaranteed, because errors and problems are found out shortly after the start of the designing process.

6. REFERENCES

[1]. Lipsett R., C. Ussery, VHDL: Hardware Description and Design, 1989.

[2]. Kukenska V., I. Simeonov, Designing of a Digital module for Management of a Seven-segmented indication with Programming logics through the use of the Description language VHDL, The 12 International Scientific and Applied Science Conference, ELECTRONICS ET'2002, Sozopol, Bulgaria, September 25-27, 2003.

[3]. Navabi Z. , VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, 1993.

用 VHDL 实现数字系统的设计

摘要：本文的内容是用VHDL语言设计数字系统，按顺序列出数字系统设计的所有步骤，此外，还有主要方法，介绍项目描述的类型，强调VHDL语言用于结构的合成和行为模式。

对于创建项目所选择的数字系统的集成系统使用了WebPack，以及协同XE II 的模型来进行模拟的。

关键字：设计，教程，数字系统、WebPack 模型

1.介绍

数字系统都是由复杂的大量组件组成的。对这种系统的自动化设计而言，应该实现应用方法设计时间的减少，以及限制任务的复杂性。这种方法应遵循分解和层次结构的原则，在职能上能区分独立模块的方式，实现系统的分解。

数字系统可以作为输入和/或输出模块描述。对产出的电值是一些功能上输入的值。

描述一种模块函数的一种方法是描述组成它的子模块。每个子模块是某些实体的实例和实例的端口使用信号进行连接。这种描述方法被称为结构描述。

在许多情况下，是不适合用结构描述的。其中一个元件是一个模块，这是在其他一些结构描述的层次结构的底部的。例如，如果您正在用从IC 商店购买的IC包设计一个系统，你不需要描述IC 的内部结构。在这种情况下，说明模块执行的功能是必需的，而不提及它实际的内部结构。这样的描述被称为功能或行为描述。

通常，结构和行为的说明，需要Verilog 或者VHDL语言。本文提供了超大规模集成电路的设计。在这里按顺序列出了数字系统设计的所有阶段，及其主要方法，介绍项目描述的类型，强调VHDL 用于合成结构和行为模式。这里介绍几种VHDL 模型的计算机系统组件。

2.数字系统设计的方法和阶段

在数字系统设计，以及设计的复杂系统中，通常使用的几个方法：

? ? 自顶向下设计

? ? 自底向上设计

自底向下的方法在通常从底部开始建立系统的设计方向，拟订模块的设计，通过组装以后形成整个产品。

此方法的优点是使用功能块级别来实现，结构级别较低，仅在项目中的错误检查模拟过程中处理。

自顶向下设计始于最高水平的规范。之后，该项目被分解为功能块，并且输入输出时间的比例可按需要指定。功能模型是通过行为模型或注册级别的模型描述的，随后进行模拟。

此方法的优点是：

? ? 任务的规范更容易实现；

? ? 无需处理结构的详细信息，即可允许项目在制度层面上进行检查；

? ? 不用考虑到其实现的技术，项目的检查就能完成。允许对设计项目的后期作出技术的选择。

自顶向下设计的最有效方法是该计划摘要说明的使用和指定顺序详细信息不同层次的描述。

数字系统设计经历的下一阶段：

? ? 规范；

? ? 功能（电子）的设计；

? ? 物理设计；

? ? 制造；

? ? 测试。

通过规范的产品参数，从而确定所需的正确目标。

通过功能（电子）设计，电子设计，参照产品的规格来制定产品的函数和参数。

在行为阶段中为系统方案而进行的描述，其条目和出口已被标出。在大多数情况下，使用VHDL 模型。主要功能块的完成需要功能（电）的设计来处理。通常由VHDL 功能块的详细说明来完成，以及通过VHDL 模拟进行检查。

随着项目的日益复杂，在结构层面上，需要应用合成技术。它需要包含逻辑元素的方案通过VHDL语言描述来进行综合。通过逻辑描述的详细信息如充电，元素的延误，是被指定的关键的方法，并定义了时间离散信号的问题。

物理设计阶段紧紧依赖于技术。逻辑元素的部署和它们之间联系的定义（跟踪）与常见任务紧密相关。

在可编程逻辑器件的实现的条件下，可以使用CPLD 或FPGA 芯片，然后物理设计的结果则表示了设计所选设备的资源配置文件。

测试项目代表了设计师使用的一些程序，用于提供：

·在项目和规范之间保持适中；

·在所选择的技术方面的项目执行。

设计过程通常逐步实现，包括已获得部分的预设计，直到获得预期的指标。

对于电气设计（产品和其电气参数的功能）任务的测试，常用模拟来进行。

在选择其实际的混合模块之前，行为层面上的模拟定义了产品将如何运行。对于行为模式，应使用硬件描述语言(vhdl 语言、Verilog语言和其他语言）。

通过模拟，在逻辑单元的级别上，由基本逻辑元素"与非"、"或非"、转换器和触发器来建立系统，是为了找出与其预期行为的无关性。

在功能测试中，延迟是不相关，或者它们对于所有的逻辑元素来说类似。

物理设计后的错误鉴定

拓扑的最后阐述后进行下一步程序：

? ? 在制作过程中检查技术规范；

? ?检查项目的真实性。

针对每个工艺过程的制造技术规范都是被指定的。

项目真实性核查的目的是保证产品的正常工作。它包括：

? ? 找出互连的方案；

? ? 找出拓扑的寄生组件。

3.设计描述的类型

设计过程中，有三种类型的设计说明可以使用：

? ? 行为；

? ? 结构；

? ? 物理。

用行为描述处理系统，系统就像是一种只有入口和出口的"黑匣子"，而不顾其结构。目的是忽略冗余的详细信息，并致力于必要功能的详细说明，以及所做产品的规范。在这一阶段，使用HDL （硬件描述语言）-vhdl 语言、Verilog语言和其他语言。

结构的描述定义的方式为系统建立的方式。在这里，被处理的系统结构是由块和及其相互关系组成的。定义的子系统，是为提供其功能而执行的，以及分析运行速度，收费等，以及其详细说明。结构描述可以用硬件描述语言来描述，如通过电子设计。

设计过程与系统描述和其顺序详细信息规范的转换有紧密联系。从行为描述到结构描述进行分解，可实现层次结构中的某些级别。从最高到最低的这些级别可以概述为，如下所示：

? ? 系统级别；

? ? 功能级别；

? ? 逻辑级别；

? ? 计划级别。