DSP28335光伏并网逆变器spwm.c

#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
#include "spwm_pwm.h"


void InitEPWM1(void)
{

// Setup TBCLK
EPwm1Regs.TBPRD = EPWM_TIMER_TBPRD;
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count updown
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


// Set actions
// EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
// EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //配置互补输出
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBFED = 500; //死去设置t=1/150000000*500 nm
EPwm1Regs.DBRED = 500; //死去设置t=1/150000000*500 nm

//ADC触发源配置
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate INT on 1rd event
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 2; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
}
void InitEPWM2(void)
{
// Setup TBCLK
EPwm2Regs.TBPRD = EPWM_TIMER_TBPRD;
EPwm2Regs.TBPHS.half.TBPHS = EPWM_TIMER_TBPRD; // Phase is 180
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count updown
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;; // able phase loading
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //配置互补输出
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBFED = 500; //死区设置t=1/150000000*500 nm
EPwm2Regs.DBRED = 500; //死区设置t=1

/150000000*500 nm


EPwm1Regs.CMPA.half.CMPA = 0;
EPwm2Regs.CMPA.half.CMPA = 0;
}
void InitEPWM3(void)
{
// Setup TBCLK
EPwm3Regs.TBPRD = DC_DC_EPWM_TIMER_TBPRD; //20KHZ
EPwm3Regs.TBPHS.half.TBPHS = 0; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Setup counter mode
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count updown
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;; // able phase loading
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4;

// Setup shadowing
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;


// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down count

EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //配置互补输出
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBFED = 600; //死区设置t=1/150000000*500 nm
EPwm3Regs.DBRED = 600; //死区设置t=1/150000000*500 nm

EPwm3Regs.CMPA.half.CMPA = (DC_DC_EPWM_TIMER_TBPRD/2);

}