UG82S4048GSG中文资料

General Description

8M Bytes (2M x 40)UG82S4048GSG

Features Single 3.3 +/- 0.3V power supply Burst Mode Operation

11/9 Addressing (Row/Column)

Data scramble (Sequential & Interleave)All inputs are sampled at the positive going edge of the system clock Two Clocks System

Auto & self refresh capability (4096 Cycles/64ms)LVTTL compatible inputs and output Serial PD with EEPROM JEDEC standard

PCB:Height (1250mil),single sided component

The UG82S4048GSG is a 2,096,152 bits by 40 Synchronous DRAM module w/ECC .The UG82S4048GSG is assembled using 5 pcs of 2M x 8 4k refresh Synchronous DRAMs in 44 pin TSOP packages mounted on 100 pin unbuffered printed circuit board.

Pin Assignment

Absolute Maximum Ratings

Voltage Relative to GND -0.3 to +4.6 V Operating Temperature 0 to +70 C Storage Temperature -55 to +125 C Short-circuit Output Current 50mA Power Dissipation 5.0 W

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Pin Names

Pin Name Function

A0 ~ A10/AP Address input (Multiplexed)BA0 Select bank DQ0 ~ DQ31Data input/output CLK0Clock input CKE0Clock enable input CS0Chip select input RAS Row address strobe CAS Column address strobe WE

Write enable DQM0 ~ 3Data Mask

V CC Power supply (3.3V)V SS Ground SDA Serial data I/O SCL Serial clock NC

No connection

CB0 ~ CB7

Check Bit SDRAM 100Pin DIMM w/ECC based on 2M x 8

UG82S4048GSG

Functional Block Diagram

V DD

Vss

Two 0.33uF

per each SDRAM

To all SDRAMs

CKE0

CAS

WE

SDRAM U0 ~ U4

SDRAM U0 ~ U4

SDRAM U0 ~ U4

Capacitors

U0 , U4

U1

10

10

CLK0

U2

U3 Note : ALL RESISTOR VALUES ARE 10 OHMS

CLK1

10

10pF

UG82S4048GSG

Physical Dimension

100 Pin DIMM Module

Units : Inches (millimeters)

Tolerances : ±.005(.13) unless otherwise specified

Detail C

Detail A Detail B ( Front view )