八位串行输入串行输出冒泡排序(verilog)

实现功能：八位串行输入串行输出冒泡排序

源文件：

module bubble_sort(clk,rst,Load,Sort,Send,Data_in,Data_out); input clk,rst,Load,Sort,Send;

input [7:0]Data_in;

output reg[7:0] Data_out;

reg[7:0] A[1:8];

reg[3:0]k;

reg[3:0]i,j;

reg [2:0]state,nstate;

parameter S_rst=3'd0;

parameter S_init=3'd1;

parameter S_idle=3'd2;

parameter S_load=3'd3;

parameter S_prep=3'd4;

parameter S_sort=3'd5;

parameter S_wait=3'd6;

parameter S_send=3'd7;

always@(posedge clk or posedge rst)

begin

if(rst)

state<=S_rst;

else

state<=nstate;

end

//状态切换

always@(state or Load or Sort or Send or i or k)

begin

case(state)

S_rst:

begin

nstate=S_init;

end

S_init:

nstate=S_idle;

S_idle:

begin

if(Load==1'b1)

nstate=S_load;

else if(Sort==1'b1)

nstate=S_prep;

else nstate = S_idle;

end

S_load:

begin

if(k==4'd8)

nstate=S_init;

else

nstate=S_load;

end

S_prep:

nstate=S_sort;

S_sort:

begin

if(i<=j)

nstate=S_sort;

else if(i<=4'd8)

nstate=S_sort;

else if(Send==1'b1)

nstate=S_send;

else

nstate=S_wait;

end

S_wait:

begin

if(Send==1'b1)

nstate=Send;

else

nstate=S_wait;

end

S_send:

begin

if(k==4'd8)

nstate=S_init;

else

nstate=S_send;

end

default:

nstate=S_rst;

endcase

end

//数据传送

always@(posedge clk)

begin

case(state)

S_rst: ;

S_init:

begin

k<=4'd0;

end

S_idle:

begin

if((Load==1'b0)&&(Sort==1'b1))

begin

j<=4'd8;

i<=4'd2;

end

end

S_load:

begin

if(k<4'd8)

begin

k<=k+1'b1;

A[1]<=Data_in;

A[2]<=A[1];

A[3]<=A[2];

A[4]<=A[3];

A[5]<=A[4];

A[6]<=A[5];

A[7]<=A[6];

A[8]<=A[7];

end

end

S_prep:

begin

if(A[j-1]>A[j])

begin

A[j]<=A[j-1];

A[j-1]<=A[j];

j<=j-1'b1;

end

end

S_sort:

begin

if(i<=j)

if(A[j-1]>A[j])

begin

A[j]<=A[j-1];

A[j-1]<=A[j];

j<=j-1'b1;

end

else

j<=j-1'b1;

else if(i<=4'd8)

begin

j<=4'd8;

i<=i+1'b1;

end

else if(Send==1'b1)

k<=4'd0;

end

S_wait:

if(Send==1'b1)

k<=4'd0;

S_send:

begin

if(k<4'd8)

begin

k<=k+1'b1;

A[1]<=8'd0;

A[2]<=A[1];

A[3]<=A[2];

A[4]<=A[3];

A[5]<=A[4];

A[6]<=A[5];

A[7]<=A[6];

A[8]<=A[7];

Data_out<=A[8];

end

end

default: ;

endcase

end

//end

Endmodule

测试文件：

`timescale 1 ns/ 1 ps

module bubble_sort_vlg_tst();

reg [7:0]Data_in;

reg Load;

reg Send;

reg Sort;

reg clk;

reg rst;

wire [7:0]Data_out;

bubble_sort i1 (

.Data_in(Data_in),

.Data_out(Data_out),

.Load(Load),

.Send(Send),

.Sort(Sort),

.clk(clk),

.rst(rst)

);

initial

begin

Data_in=8'd0;

clk=1'b0;

forever #10 clk=~clk;

$display("Running testbench");

end

initial

begin

rst=1'b1;Load=1'b0;Sort=1'b0;Send=1'b0; #100 rst=1'b0;Load=1'b1;

#60 Data_in=8'd37;

#20 Data_in=8'd29;

#20 Data_in=8'd01;

#20 Data_in=8'd19;

#20 Data_in=8'd89;

#20 Data_in=8'd10;

#20 Data_in=8'd12;

#20 Data_in=8'd182;

#20 Load=1'b0;

Sort=1'b1;

Send=1'b1;

#2000 $stop;

end

endmodule

仿真结果：

输入数据波形

输出数据波形