VN5050J-E_07中文资料

September 2007 Rev 21/31

VN5050J-E

Single channel high side driver

for automotive applications

Features

■

Main

–Inrush current active management by power limitation

–Very low stand-by current – 3.0V CMOS compatible input

–Optimized electromagnetic emission –Very low electromagnetic susceptibility –In compliance with the 2002/95/EC European directive ■

Diagnostic functions

–Open drain status output –On state open load detection –Off state open load detection –Thermal shutdown indication

■

Protections

–Undervoltage shut-down –Overvoltage clamp

–Output stuck to V CC detection –Load current limitation

–Self limiting of fast thermal transients

–Protection against loss of ground and loss of V CC

–Thermal shut down

–Reverse battery protection (see Figure 27)–Electrostatic discharge protection Application

■

All types of resistive, inductive and capacitive loads

Description

The VN5050J-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient

compatibility table). The device detects open load condition both in on and off state, when STAT_DIS is left open or driven low. Output shorted to V CC is detected in the off state.

When STAT_DIS is driven high, the STATUS pin is in a high impedance condition.Output current limitation protects the device in overload

condition. In case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention.Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

PowerSSO-12

Table 1. Device summary

Package Order codes

Tube Tape & Reel Max supply voltage V CC 41V Operating voltage range

V CC 4.5 to 36V Max On-State resistance (per ch.)R ON 50 m ?Current limitation (typ)I LIMH 19 A Off state supply current

I S

2 μA (1)

(1)Typical value with all loads connected PowerSSO-12

VN5050J-E

VN5050JTR-E

https://www.360docs.net/doc/7f15923790.html,

Contents VN5050J-E

Contents

1Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20

3.1.1Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . 20

3.1.2Solution 2: diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . 21

3.2Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3MCU I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1ECOP ACK? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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VN5050J-E List of tables List of tables

Table 2.Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3.Suggested connections for unused and n.c. pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5.Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6.Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7.Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8.Status pin (V SD=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9.Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10.Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 11.Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 12.Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 13.Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 14.Thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15.PowerSSO-12? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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List of figures VN5050J-E List of figures

Figure 1.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3.Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4.Status timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5.Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6.Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7.Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8.Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9.High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11.Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12.Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13.Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14.Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 15.Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 16.On state resistance vs V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 17.Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 18.Openload on state detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 19.Openload off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 20.I LIM vs T case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 21.Turn-on voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 22.Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 23.Turn-off voltage slope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 24.STAT_DIS clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 25.High level STAT_DIS voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 26.Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 27.Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 28.Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 29.Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 30.PowerSSO-12 PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 31.Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24 Figure 32.PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 25 Figure 33.Thermal fitting model of a single channel HSD in PowerSSO-12. . . . . . . . . . . . . . . . . . . . 25 Figure 34.PowerSSO-12? package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 35.PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 36.PowerSSO-12 tape and reel shipment (suffix “TR”). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/31

VN5050J-E Block diagram and pin description

5/31

1 Block diagram and pin description

Name Function

Table 2.

Pin function

V CC

Battery connection

OUTPUT Power output GND Ground connection. Must be reverse battery protected by an external diode/resistor

network

INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state

STA TUS Open drain digital diagnostic pin

ST A T_DIS

Active high CMOS compatible pin, to disable the ST A TUS pin

Connection / Pin Status N.C.Output Input STAT_DIS

Block diagram and pin description

VN5050J-E

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Table 3.Suggested connections for unused and n.c. pins

Floating X X X X X T o ground

N.R.(1)

(1)Not recommended

N.R.

Through 10K ?

resistor

Through 10K ?

resistor

VN5050J-E Electrical specifications

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2 Electrical specifications

Note:

V F = V OUT - V CC during reverse battery condition

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 4.

Absolute maximum ratings

Symbol Parameter

Value Unit V CC DC supply voltage 41V - V CC Reverse DC supply voltage 0.3V - I GND DC reverse ground pin current 200mA I OUT DC output current

Internally limited

A - I OUT Reverse DC output current 12A I IN DC input current +10 / -1mA I ST AT

DC status current

+10 / -1mA I STAT_DIS DC status disable current +10 / -1mA E MAX

Maximum switching energy

(L=3mH; R L =0?; V bat =13.5V; T jstart =150oC; I OUT = I limL (Typ.))

104

Electrical specifications

VN5050J-E

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2.2 Thermal data

Symbol Parameter

Value Unit

V ESD

Electrostatic discharge

(Human Body Model: R=1.5K ?; C=100pF)- INPUT - ST A TUS - ST A T_DIS - OUTPUT - V CC

40004000400050005000V V V V V V ESD Charge device model (CDM-AEC-Q100-011)750V T j Junction operating temperature -40 to 150°C T stg

Storage temperature

- 55 to 150

°C

Table 4.

Absolute maximum ratings (continued)

Symbol

Parameter

Value

Unit

Table 5.

Thermal data

R thj-case Thermal resistance junction-case (Max.)

(with one channel ON)

2.7°C/W R thj-amb

Thermal resistance junction-ambient (Max.)

See Figure 31

°C/W

VN5050J-E Electrical specifications

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2.3 Electrical characteristics

Values specified in this section are for 8V

specified .

Symbol Parameter

Test conditions

Min.Typ.Max.Unit

Symbol Parameter

Test conditions

Min.

Typ.Max.

Unit Table 6.

Power section

V CC Operating supply voltage 4.5

1336V V USD Undervoltage shutdown 3.5 4.5

V V USDhyst

Undervoltage shut-down hysteresis

0.5

V R ON On state resistance (2)I OUT =1A; T j =25°C I OUT =1A; T j =150°C

I OUT =1A; V CC =5V; T j =25°C 5010065m ?m ?m ?V clamp

Clamp voltage

I S =20mA

52V

I S

Supply current

Off State; V CC =13V; T j =25°C;V IN =V OUT =V SENSE =V CSD =0V On State; V CC =13V; V IN =5V; I OUT =0A

2(1)1.9(1)PowerMOS leakage included.5(1)3.5μA mA

I L(off1)

Off state output current (2)

(2)For each channel

V IN =V OUT =0V; V CC =13V; T j =25°C

V IN =V OUT =0V; V CC =13V; T j =125°C

000.01

35μA

I L(off2)Off state output current (2)V IN =0V; V OUT =4V -750V F

Output - V CC diode voltage (2)

-I OUT =2A; T j =150°C

0.7

Table 7.

Switching (V CC = 13V; T j = 25°C)

t d(on)T urn-on delay time R L = 6.5? (see Figure 5)20μs t d(off)

T urn-off delay time

R L = 6.5? (see Figure 5)

μs

dV OUT /dt (on)T urn-on voltage slope R L = 6.5? see Figure 21V /μs dV OUT /dt (off)T urn-off voltage slope R L = 6.5? see Figure 23V /μs

W ON Switching energy losses

during t won

R L = 6.5? (see Figure 5)

0.2mJ W OFF

Switching energy losses

during t woff

R L = 6.5? (see Figure 5)

0.2

Electrical specifications VN5050J-E

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Symbol Parameter Test conditions Min Typ Max Unit Symbol Parameter Test conditions Min.Typ.Max.Unit Table 8.Status pin (V SD=0V)

V STAT

Status low output

voltage

I STA T= 1.6 mA, V SD=0V0.5V

I LST AT Status leakage current

Normal Operation or V SD=5V,

V STA T= 5V

10μA

C ST AT

Status pin input

capacitance

Normal Operation or V SD=5V,

V STA T= 5V

100pF V SCL Status clamp voltage

I STA T= 1mA

I STA T= -1mA

5.5

-0.7

V Table 9.Protections (1)

(1)To ensure long term reliability under heavy overload or short circuit conditions, protection and related

diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles

I limH DC Short circuit current

V CC=13V

13.51926.5

26.5

I limL

Short circuit current

during thermal cycling

V CC=13V

T R

7A T TSD Shutdown temperature150175200°C T R Reset temperature T RS + 1T RS + 5°C T RS

Thermal reset of

STA TUS

135°C T HYST

Thermal hysteresis

(T TSD-T R)

7°C t SDL

Status delay in overload

conditions

T j>T TSD (see Figure 4)20μs V DEMAG

Turn-off output voltage

clamp

I OUT=2A; V IN=0; L=6mH V CC-41V CC-46V CC-52V

V ON

Output voltage drop

limitation

I OUT = 0.1A;

T j= -40°C...+150°C

(see Figure 6)

25mV

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Electrical specifications

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Symbol Parameter

Test conditions Min Typ Max Unit

Symbol Parameter

Test conditions

Min.

Typ.

Max.Unit

Table 10.

Openload detection

I OL Openload ON State Detection Threshold V IN = 5V ,8V

See Figure 18

50mA t DOL(on)

Openload ON State Detection Delay

I OUT = 0A, V CC =13V (see Figure 4)

200

μs

t POL

Delay between INPUT falling edge and STA TUS

rising edge in Openload condition

OUT = 0A (see Figure 4)2005001000μs

V OL Openload OFF State Voltage Detection Threshold

V IN = 0V , 8V

See Figure 19

t DSTKON

Output Short Circuit to V CC Detection Delay at T urn Off

(see Figure 4)180

t POL

μs

Table 11.

Logic input

V IL Input Low Level 0.9

V I IL Low Level Input Current V IN =0.9 V

1μA V IH Input High Level

2.1

V I IH High Level Input Current V IN = 2.1 V 10

μA V I(hyst)Input Hysteresis Voltage 0.25V V ICL Input Clamp Voltage I IN = 1mA I IN = -1mA

5.5

-0.7

V V V SDL STA T_DIS low level voltage

0.9V I SDL Low level STA T_DIS current

V SD = 0.9 V

1μA V SDH STA T_DIS high level voltage

2.1

V I SDH High level ST A T_DIS current

V SD = 2.1 V

μA V SD(hyst)STA T_DIS hysteresis voltage

0.25V V SDCL

STA T_DIS clamp voltage

I SD =1mA I SD =-1mA 5.5

-0.7

V V

Electrical specifications VN5050J-E

12/31

Truth T able

Conditions Input Output Status (V SD=0V)(1) Table 12.Truth table

(1)If the V SD is high, the STATUS pin is in a high impedance.

Normal operation

H Current limitation

H Overtemperature

L Undervoltage

X Output voltage > V OL

H Output current < I OL

H(2)

(2)The STATUS pin becomes high with a delay equal to t POL after INPUT falling edge.

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Electrical specifications

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Figure 5.

Switching characteristics

Figure 6.Output voltage drop limitation

V OUT

dV OUT /dt (on)

t r

80%

10%

t f

dV OUT /dt (off)

t d(off)

t d(on)

INPUT

90%

t Won

t Woff

V on

I out

V cc -V out

T j =150o C

T j =25o C

T j =-40o C

V on /R on(T)

Electrical specifications VN5050J-E

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ISO 7637-2:

2004(E)

Test pulse

Test levels Number of

pulses or

test times

Burst cycle/pulse

repetition time

Delays and

Impedance III IV

ISO 7637-2:

2004(E)

Test pulse

Test level results(1)

III IV Class Contents

Table 13.Electrical transient requirements

1-75V-100V5000 pulses0.5 s 5 s 2 ms, 10 ?2a+37V+50V5000 pulses0.2 s 5 s50 μs, 2 ?3a-100V-150V1h90 ms100 ms0.1 μs, 50 ?3b+75V+100V1h90 ms100 ms0.1 μs, 50 ?4-6V-7V1pulse

100 ms,

0.01?

5b(2)+65V+87V 1 pulse400 ms, 2?(1)The above test levels must be considered referred to V CC = 13.5V except for pulse 5b

1C C

2a C C

3a C C

3b C C

4C C

5b(2)

(2)Valid in case of external load dump clamp: 40V maximum referred to ground.

C C

C All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to

disturbance and cannot be returned to proper operation without replacing the device.

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Electrical specifications VN5050J-E

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2.4 Electrical characteristics curves

Figure 8.

Off state output current Figure 9.

High level input current

Figure 10.Input clamp voltage

Figure 11.Input high level

Figure 12.Input low level

Figure 13.Input hysteresis voltage

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Electrical specifications

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Figure 14.Status low output voltage

On state resistance vs T case

Figure 15.Status leakage current

Figure 16.On state resistance vs V CC

Figure 17.Status clamp voltage

Figure 18.Openload on state detection threshold

Electrical specifications

VN5050J-E

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Figure 19.Openload off state voltage detection threshold

Figure 20.I LIM vs T case

Figure 21.Turn-on voltage slope

Figure 22.Undervoltage shutdown

Figure 23.Turn-off voltage slope

Figure 24.STAT_DIS clamp voltage

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Electrical specifications

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Figure 25.High level STAT_DIS voltage

Figure 26.Low level STAT_DIS voltage

Application information VN5050J-E

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3 Application information

Figure 27.Application schematic

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (R GND only).

This can be used with any type of load.

The following is an indication on how to dimension the R GND resistor.1.

R GND ≤ 600mV / (I S(on)max ). 2. R GND ≥ (?V CC ) / (-I GND )

where -I GND is the DC reverse ground pin current and can be found in the absolute

maximum rating section of the device datasheet.

Power Dissipation in R GND (when V CC <0: during reverse battery situations) is:P D = (-V CC )2/R GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I S(on)max becomes the sum of the maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the R GND will produce a shift (I S(on)max * R GND ) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R GND .

If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).

V CC

GND

OUTPUT

D GND

R GND

D ld

μC

+5V

V GND

ST A T_DIS

INPUT

R prot

+5V

ST A TUS