MT29F16G08CBACA__L72A 美光芯片

NAND Flash Die

16Gb Die: x8 300mm MLC MT29F16G08CBACA MT29F16G08CBECB

Features

?Contact factory for part availability

?Open NAND Flash Interface (ONFI) 2.2-compliant1?Multiple-level cell (MLC) technology ?Organization

–Page size x8: 4320 bytes (4096 + 224 bytes)

–Block size: 256 pages (1024K + 56K bytes)

–Plane size: 2 planes x 1024 blocks per plane

–Device size: 16Gb: 2048 blocks

?Synchronous I/O performance

–Up to synchronous timing mode 5

–Clock rate: 10ns (DDR)

–Read/write throughput per pin: 200MT/s ?Asynchronous I/O performance

–Up to asynchronous timing mode 5

–t RC/t WC: 20ns (MIN)

?Array performance

–Read page: 75μs (MAX)

–Program page: 1300μs (TYP)

–Erase block: 3ms (TYP)

?Operating Voltage Range

–V CC: 2.7–3.6V

–V CCQ: 1.7-1.95V, 2.7–3.6V

?Command set: ONFI NAND Flash Protocol ?Advanced Command Set

–Program cache

–Read cache sequential

–Read cache random

–One-time programmable (OTP) mode

–Multi-plane commands

–Multi-LUN operations

–Read unique ID

–Copyback

?First block (block address 00h) is valid when ship-ped from factory2

?RESET (FFh) required as first command after power-on

?Operation status byte provides software method for detecting:

–Operation completion

–Pass/fail condition

–Write-protect status ?Data strobe (DQS) signals provide a hardware meth-od for synchronizing data DQ in the synchronous interface

?Copyback operations supported within the plane from which data is read

?Operating temperature:

–Commercial: 0oC to +70oC

Die Outline

?Die size (stepping distance): 6.43380mm x

8.83905mm

?Bond pad location and identification, see Bond Pad Locations and Identification (page 5)

General Physical Specifications ?Nominal wafer thickness: 790μm ±25μm

?Typical bond-pad metal thickness: 17.7k??Typical topside passivation: 4k? oxynitride over 10.5k? of silane oxide

?Metallization composition: 3k? Pd over 10k? Ni over 3k? Cu

Options Marking Interface:

–Asynchronous MT29F16G08CBACA –Synchronous MT29F16G08CBECB ?Form: Wafer3W ?Testing: Standard probe C1

Figure 1: Order Information

MT29F16G08CBACA L72A 3W C1

Product #Die database Form Testing level

Notes: 1.The ONFI 2.2 specification is available at

https://www.360docs.net/doc/7f17443066.html,.

2.For details, see the "Features" and "Error

Management" sections of the packaged

product data sheet.

General Die Instructions

Die Testing Procedures

Micron? wafer products are tested at a standard probe test level. Wafer probe is per-

formed at an elevated temperature to ensure product functionality in Micron's stand-

ard packages. The package environment is not within Micron's control, so the user

must determine the necessary heat sink requirements to ensure that the die junction

temperature remains within specified limits.

Wafer-Level Testing

The standard probe flow is the same probe flow used for Micron's package products.

The following list provides an example of a standard probe test performed at wafer level

for Micron's products:

?Opens/shorts

?Input/output leakage tests

?I CC standby

?Voltage regulator performance

?Nominal V CC and V CCQ functional

?Memory array algorithmic patterns

?High voltage stress

?PROGRAM performance

?ERASE performance

?Invalid block marking

Repairs are implemented at each repair test. Repairable die are processed through re-

pair algorithms based on the repair solutions defined during the tests described above.

Post-repair testing is conducted with appropriate guardbands to ensure a consistently

high quality level.

The status register reports the status of die operations.

Figure 2: Standard Probe Flow

Micron retains a wafer map of each wafer as part of the probe records, along with a lot

summary of wafer yields for each lot probed. Micron reserves the right to change the

probe program at any time to improve the reliability, package device yield, or perform-

ance of the product. Die users may experience differences in performance and reliabili-

ty relative to Micron data sheet specifications. This is due to differences in package

capacitance, inductance, resistance, trace length, and device testing.

Functional Specification

The specifications in this die data sheet are provided for reference only. For target func-

tional and parametric specifications, refer to the packaged product data sheet. This

data sheet is available to customers under NDA; to obtain a copy, contact Micron

NAND Flash support at nandsupport@https://www.360docs.net/doc/7f17443066.html,.

Bonding Instructions

Refer to the Bond Pad Location from Pad 1 Center Table for a complete list of bond

pads and coordinates from bond pad 1 center, and to the Bond Pad Location from Die

Center Table for bond pad locations from center of die.

The back side of the die is at V SS potential. For improved thermal performance, it is rec-

ommended that the die be connected to the ground plane. It is also possible to leave

the back side of the die floating.

Micron recommends following the best practices guidelines (defined in the technical

note TN-29-24, "Micron Wire-Bonding Techniques," located on Micron's secure Web

site) when bonding to copper wafers with nickel-palladium metallization.

Wafer-Level Processing

Micron provides full-thickness wafers to accommodate post-processing. Post-process-

ing includes adding extra passivation or metal layers, or bumping bond-pads. The

street width is provided in the die outline, which also provides a reference from the cen-

ter of bond pad 1 to the center of the intersection of the two streets for easy alignment. Storage Requirements

Micron's wafer products are packaged for shipping in a cleanroom environment. Upon

receipt, the customer should transfer the die or wafers to a similar environment for stor-

age. Micron advises that customers avoid exposing Flash die products to ultraviolet

light or processing them at temperatures greater than 250°C for more than five minutes.

Failure to adhere to these handling instructions will result in irreparable damage to the

devices.

Micron also recommends that the wafers be maintained in a filtered nitrogen atmos-

phere until removed for assembly. The moisture content of the storage facility should

be maintained at 30% ±10% relative humidity. Precautions for avoiding ESD damage

are necessary during handling. The die must be in an ESD-protected environment for

inspection and assembly at all times.

Product Reliability Monitors

Micron’s QRA department continually samples product families for reliability studies.

These samples are subjected to a battery of tests known as "accelerated life and environ-

mental stress tests." During these tests, devices are stressed for many hours under

conditions designed to simulate years of normal field use. A summary of these product-

family evaluations is published on a regular basis and is available upon request.

Die/Wafer-Level Reliability and Screening

Extensive Micron qualification of both the die and the die manufacturing process

shows that production burn-in is not required to meet the endurance and data reten-

tion specifications on Flash products. Additional information is available upon request.

Bond Pad Locations and Identification

Bond pad locations are provided from the center of pad 1, located in the upper-left cor-

ner of the die (see Table 1), and from the center of the die (see Table 2).

Table 1: Bond Pad Location from Pad 1 Center

Notes: 1.Reference is to center of each bond pad from center of pad 1.

2.All die V CC and V SS pads must have separate connections.

3.DNU = do not use.

4.See Multiple-Die Stack Configurations (page 7) for bonding configuration.

5.For MT29F16G08CBACA this pad is DNU; for MT29F16G08CBECB connect to DQS.

Table 2: Bond Pad Location from Die Center

Notes: 1.Reference is to center of each bond pad from center of die.

2.All die V CC and V SS pads must have separate connections.

3.DNU = do not use.

4.See Multiple-Die Stack Configurations (page 7) for bonding configuration.

5.For MT29F16G08CBACA this pad is DNU; for MT29F16G08CBECB connect to DQS.

Multiple-Die Stack Configurations

More than one NAND die can be stacked into a package. It is possible for two die to

share a single CE# signal. When two die are connected to a single CE#, this permits Multi-LUN operations.

The multiple-die stack (MDS) bond pads are used to configure the NAND die to share a single CE#.

Table 3: MDS Bonding Configuration

Note:

1.DNU = do not use.

NAND Flash Die: 16Gb 300mm MLC Multiple-Die Stack Configurations

Device and Array Organization for Multiple-Die Stack Configurations

Figure 3: Example Device Organization for Single-Die Package

Async Sync CE# CE#CLE CLE ALE ALE WE# CLK RE# W/R#DQ[7:0] DQ[7:0]

N/A DQS WP#

WP#

R/B#

Note: 1.DNU = do not use.

Figure 4: Example Device Organization for Two-Die Package with Single CE#, Single I/O Channel

Async Sync CE# CE#CLE CLE ALE ALE WE# CLK RE# W/R#DQ[7:0] DQ[7:0]

N/A DQS WP#

WP#

R/B#

Note: 1.DNU = do not use.

Figure 5: Example Device Organization for Two-Die Package with Two CE#s, Two I/O Channels

CE#CLE-1ALE-1CLK-1W/R#-1DQ[7:0]-1DQS-1WP#-1

R/B#

CE2#CLE-2ALE-2CLK-2W/R#-2DQ[7:0]-2

DQS-2WP#-2

CE#CLE-1ALE-1WE#-1RE#-1DQ[7:0]-1

N/A WP#-1

CE2#CLE-2ALE-2WE#-2RE#-2DQ[7:0]-2

N/A WP#-2

R/B2#

Async Sync Note: 1.DNU = do not use.

Figure 6: Example Device Organization for a Four-Die Package with Two CE#s, Single I/O Channel

CE#

CLE

ALE

CLK W/R# DQ[7:0]

DQS

WP#

R/B#

CLE

ALE

CLK

W/R# DQ[7:0]

DQS

WP#R/B2#

CE#

CLE

ALE

WE#

RE#

DQ[7:0]

N/A

WP#

CE2#

CLE

ALE

WE#

RE#

DQ[7:0]

N/A

WP#

Async Sync

Note: 1.DNU = do not use.

Figure 7: Array Organization per Logical Unit (LUN)

(0, 2, 4, ..., 2046)(1, 3, 5, ..., 2047)

4320 bytes

Logical Unit (LUN)

Table 4: Array Addressing for Logical Unit (LUN)

Notes:

1.CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the

page address, block address, and LUN address are collectively called the row address.2.When using the synchronous interface, CA0 is forced to 0 internally; one data cycle al-ways returns one even byte and one odd byte.

3.Column addresses 4320 (10E0h) through 8191 (1FFFh) are invalid, out of bounds, do not

exist in the device, and cannot be addressed.4.BA[8] is the plane-select bit:

Plane 0: BA[8] = 0Plane 1: BA[8] = 1

https://www.360docs.net/doc/7f17443066.html,0 is the LUN-select bit. It is present only when two LUNs are shared on the target;

otherwise, it should be held LOW.LUN 0: LA0 = 0LUN 1: LA0 = 1

Identification Operations for Multiple-Die Stack Configurations

The data returned by the READ ID (90h) and READ PARAMETER PAGE (ECh) com-

mands are different depending on the MDS configuration (see Multiple-Die Stack

Configurations (page 7)).

Table 5: READ ID Parameters for Address 00h

Note: 1.h = hexadecimal.

Table 6: READ ID Parameters for Address 20h

Notes: 1.h = hexadecimal.

2.XXh = undefined.

Table 7: Parameter Page Data Structure Table

Table 7: Parameter Page Data Structure Table (Continued)

Table 7: Parameter Page Data Structure Table (Continued)

Table 7: Parameter Page Data Structure Table (Continued)

Table 7: Parameter Page Data Structure Table (Continued)

Table 7: Parameter Page Data Structure Table (Continued)

Table 7: Parameter Page Data Structure Table (Continued)

Die Features and Physical Specifications

Figure 8: L72A Die Outline

Note: 1.Die is not drawn to scale. Dimension are shown in Die Features and Physical Specifica-

tions (page 19)

Table 8: Die Dimensions

Table 8: Die Dimensions (Continued)