SPCA1528av03_draft_hilevel

a l ly ti n On de e fi n Us SPCA1528Ao C gy a o Digital StildCamera lControllers l i e no M ch m e us el T pl v u n -L e S i H or F
Preliminary
JUL. 10, 2008 Version 0.3 (Draft)
Sunplus mMedia Inc. reserves the right to change this documentation without prior notice. Information provided by Sunplus mMedia Inc. is believed to be accurate and reliable. However, Sunplus mMedia Inc. makes no warranty for any errors which may appear in this document. Contact Sunplus mMedia Inc. to obtain the latest version of device specifications before placing your order. patent or other rights of third parties which may result from its use. No responsibility is assumed by Sunplus mMedia Inc. for any infringement of In addition, Sunplus mMedia Inc. products are not authorized for use as critical
components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus mMedia. * Draft: preliminary information only. Customers MUST contact Sunplus mMedia for ultimate confirmation before placing orders.

Preliminary
SPCA1528A
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 4 1.1. INTRODUCTION ...................................................................................................................................................................................... 4 1.2. TERMINOLOGY ....................................................................................................................................................................................... 4 2. FEATURE .................................................................................................................................................................................................... 5 2.1. CPU ..................................................................................................................................................................................................... 5 2.2. PERIPHERAL .......................................................................................................................................................................................... 5 2.3. MEMORY INTERFACE .............................................................................................................................................................................. 5 2.4. STORAGE MEDIA INTERFACE .................................................................................................................................................................. 5 2.5. SENSOR ................................................................................................................................................................................................ 5 2.6. DISPLAY ................................................................................................................................................................................................ 5 2.7. COLOR DSP.......................................................................................................................................................................................... 5 2.8. STILL IMAGE AND VIDEO COMPRESSION .................................................................................................................................................. 5 2.9. USB ..................................................................................................................................................................................................... 5 2.10. AUDIO ................................................................................................................................................................................................... 5 2.11. PACKAGE AND POWER ........................................................................................................................................................................... 5 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 6 3.1. BLOCK DIAGRAM.................................................................................................................................................................................... 6 3.2. FUNCTION DESCRIPTION ........................................................................................................................................................................ 6 4. PIN DESCRIPTIONS ................................................................................................................................................................................... 8 4.1. PIN DESCRIPTIONS ................................................................................................................................................................................ 8 4.1.1. CPU Interface ........................................................................................................................................................................... 8 4.1.2. Storage media interface ............................................................................................................................................................ 8 4.1.3. System ...................................................................................................................................................................................... 9 4.1.4. AUDIO/SAR .............................................................................................................................................................................. 9 4.1.5. SDRAM interface ...................................................................................................................................................................... 9 4.1.6. Digital TV interface.................................................................................................................................................................. 10 4.1.7. USB interface...........................................................................................................................................................................11 4.1.8. Video DAC interface.................................................................................................................................................................11 4.1.9. Sensor interface.......................................................................................................................................................................11 4.1.10. RTC .................................................................................................................................................................................... 12
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4.1.11.GPIO ....................................................................................................................................................................................... 12 4.1.12. Power/Ground .................................................................................................................................................................... 12
4.2. IO-TRA............................................................................................................................................................................................... 13 5. ELECTRICAL SPECIFICATION ................................................................................................................................................................ 14 5.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 14 5.2. DC CHARACTERISTICS ......................................................................................................................................................................... 14 5.3. RTC PARAMETERS .............................................................................................................................................................................. 15 5.4. USB INTERFACE CHARACTERISTICS ..................................................................................................................................................... 15 5.4.1. USB DC Characteristics.......................................................................................................................................................... 15 5.4.2. USB AC Characteristics .......................................................................................................................................................... 16 5.5. ANALOG AUDIO INTERFACE CHARACTERISTICS ..................................................................................................................................... 16 5.6. ANALOG VIDEO INTERFACE CHARACTERISTICS ..................................................................................................................................... 17 ? Sunplus mMedia Inc. Proprietary & Confidential 2 JUL. 10, 2008 Preliminary Version: 0.3 (Draft)

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SPCA1528A
5.7. GENERAL-PURPOSE ADC CHARACTERISTICS ....................................................................................................................................... 17 6. PACKAGE INFORMATION ....................................................................................................................................................................... 18 6.1. PACKAGE PIN ASSIGNMENT .................................................................................................................................................................. 18 6.1.1. LQFP 128-pin Package 1 (SPCA1525A) ................................................................................................................................ 18 6.1.2. LQFP 128-pin Package 2 (SPCA1526A) ................................................................................................................................ 19 6.1.3. LQFP 176-pin Package........................................................................................................................................................... 20 6.2. PIN NAME ............................................................................................................................................................................................ 21 6.2.1. LQFP 128-pin Package 1 (SPCA1525A) ................................................................................................................................ 21 6.2.2. LQFP 128-pin Package 2 (SPCA1526A) ................................................................................................................................ 22 6.2.3. LQFP 176-pin Package........................................................................................................................................................... 23 6.3. ORDERING INFORMATION ..................................................................................................................................................................... 24 6.4. STORAGE CONDITION AND PERIOD FOR PACKAGE ................................................................................................................................. 30 6.5. RECOMMENDED SMT TEMPERATURE PROFILE...................................................................................................................................... 30 7. DISCLAIMER............................................................................................................................................................................................. 31 8. REVISION HISTORY ................................................................................................................................................................................. 32
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Digital Still Camera Controllers
1.GENERAL DESCRIPTION
1.1. Introduction
The SPCA1528A is a low cost digital still camera SoC, which features with a full set of components required in a digital still camera system. The SoC has embedded with Sunplus high quality
1.2. Terminology
AE: AWB: Automatic Exposure Automatic White Balance Encoder and Decoder
image processing engine, high- speed JPEG CODEC and a wide range of peripheral interfaces, making a low cost DSC easy to be realized.
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CODEC: Color DSP: DMA: I2C: Color image Digital Signal Processor Direct Memory Access Inter IC Control ISP: In System Programming LCM: Liquid Crystal display Module MMC: PLL: SD: Multi Media Card Phase Lock Loop Secure Digital card UART: USB: Universal Asynchronous Receiver Transmitter Universal Serial Bus VGA: Video Graphics ArrayTV game product
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2.FEATURE
2.1. CPU
8032 with 8KB Data Memory and 2KB Program Memory Support ISP (In-System-Programming) function via USB Program code shadowing function to SDRAM External NOR-type Flash up to 1MB
2.7. Color DSP
Support RGB Bayer patterns output and YUV422 output sensor. Support both master mode and slave mode CMOS sensors. Programmable frame rate. On-chip color processing engine AWB window statistics
2.2. Peripheral
1 UART port
USB 2.0 high speed with on-chip PHY Two PWM ports Three timers
3-channel general purpose ADC GPIOs
2.3. Memory Interface
Support SDRAM with density of 16Mb to 512Mb
Programmable DRAM operating frequencies up to 96MHz Support down grade SDRAM
2.4. Storage Media Interface
Supports NAND-type flash memory and serial flash memory Support MMC and SD memory cards
2.5. Sensor
Support all popular CMOS image sensors
Image resolution from 2M pixels to 5 M pixels
Support Digital TV Input, CCIR601 (8-bit data bus) and CCIR656
I2C serial control port for sensor parameter settings Accurate flash light control at pixel level Mechanical shutter control
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— 2-D edge enhancement — Luminance histogram — Hue/Saturation adjustment Brightness/Contrast adjustment — Programmable edge enhancement the user-defined firmware. Fully programmable Gamma table Lens shade compensation emboss, binaries, sepia, black/white.
Bad pixel concealment can be done by hard-wired engine or by
Support special image effects such as negative, Solaris,
2.8. Still Image and Video Compression
Motion JPEG 640x480 (VGA) resolution CODEC up to 30 fps
2.9. USB
USB 2.0 Full/High Speed function with built-in USB2.0 transceiver
Supports USB mass storage, audio, video, and still image
2.10. Audio
IMA ADPCM audio CODEC
Built-in mono audio ADC for microphone input
Mono PWM DAC with external amplifier to support speaker
2.11. Package and Power 2.6. Display
Supports Digital LCD Display Interface for Casio, AUO, Sony, and TOPPOLY Supports ITU-R BT 601 digital video output interface Built-in TV encoder to support direct output analog NTSC or PAL composite video signals Programmable luminance(Contrast, Brightness) and 3.3V IO power supply 1.8V core power supply 128-pin/176-pin LQFP package
chrominance(Hue, Saturation) control for display Support font-based OSD Support 8/9 bits LCM interface
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SPCA1528A
3. BLOCK DIAGRAM
3.1. Block Diagram
The following diagram shows the internal structure of SPCA1528A and a typical connection to the external devices.
27MHz
PLL
8032 CPU
Data/ Program Memory
CMOS image sensor
3-channel ADC
32.768KHz
Backup capacitor
3.2. Function Description
CMOS Sensor controller
The sensor interface connects to CMOS sensors. connect to a video decoder to capture video. used to program CMOS sensors.
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CMOS sensor controller Image Processing Engine DRAM bridge DRAM controller SDRAM Traffic controller General Purpose ADC GPIOs PWMs UART DISPLAY controller MotionJPEG/JPEG CODEC Audio controller DMA controller Timers TV encoder Audio ADC/DAC USB controller Storage media controller RTC DAC USB2.0 PHY Mic Amp PC NAND Flash Serial flash NOR Flash SD/MMC LCD/LCM TV Speaker
DISPLAY Controller
It can also
This module has integrated a variety of digital interfaces, which include TFT LCD interface, LCM interface, It also integrates a TV encoder, supporting both NTSC and PAL composite video outputs. The OSD function is also implemented in this module.
A serial interface is
RTC The RTC module enables the SPCA1528A to maintain the calendar function with minimum power consumption. Image Processing Engine The Image processing engine of the SPCA1528A is a very flexible pipeline. PLL The SPCA1528A has an on-chip PLL that allows the use of a minimum number of crystals in user applications. Major internal It will perform color interpolation, gamma correction,
image scaling for digital zoom, and image enhancement filtering. It also has real-time AF/AE/AWB statistic engines to provide data for computing the optimal control parameters. All the functions are controlled by a set of programmable registers, allowing users to fine-tune the image quality.
clocks can be generated with a single 27MHz crystal.
8032 CPU The built-in 8032 CPU coordinates camera operation. JPEG CODEC This image compression engine can generate JPEG compressed
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files in JFIF and EXIF format with firmware support. The engine USB2.0 High Speed Controller The USB controller supports USB2.0 full speed and high speed data transfer. A high performance USB2.0 PHY is integrated. DRAM Controller The DRAM controller provides an access path to the SDRAM for other internal modules of the SPCA1528A. Many special SPCA1528A supports all types of USB pipes, including control, bulk, ISO and interrupt pipes. Totally, eight USB endpoints are implemented in SPCA1528A controller. The following table summarizes the functions of each endpoint. can also decode JPEG compressed images for playback.
functions are also implemented in this module. For example, image scaling, copy and paste of image parts, image rotation, … etc.
DMA Controller
The DMA controller allows high-speed data transfers between SPCA1528A internal modules.
Storage Media Controller
The storage interface controller is a high efficiency bridge between different storage media protocol and the internal bus. data transfers and PIO data transfers are supported.
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Endpoint 0 1 2 3 4 5 6 7 Function Control endpoint as default pipe Video ISO IN endpoint Bulk IN endpoint for MSDC Bulk OUT endpoint for MSDC Interrupt IN endpoint for SIDC Interrupt IN endpoint for audio status Both DMA ISO IN endpoint for audio data Interrupt IN endpoint for debugging
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4. PIN DESCRIPTIONS
4.1. Pin Descriptions 4.1.1.
No. 1
CPU Interface
Hex. Psen Dir. B Program space enable This pin is an output pin when the built-in CPU is enabled. Description
2 3 4 5 6 7 8 9 10
romwrnn p00 p01 p02 p03 p04 p05 p06 p07
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27
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When external CPU is used, this pin is an input pin. O B B B B B B B External write pulse. This pin is used in the ISP (in-system-programming) function CPU port 0, address/data multiplex pin, bit 0. CPU port 0, address/data multiplex pin, bit 1. CPU port 0, address/data multiplex pin, bit 2. CPU port 0, address/data multiplex pin, bit 3. CPU port 0, address/data multiplex pin, bit 4. CPU port 0, address/data multiplex pin, bit 5. CPU port 0, address/data multiplex pin, bit 6. B CPU port 0, address/data multiplex pin, bit 7. Default function Alternative function B CPU address bit 0 CPU port 1, bit 0. B B B B B B B CPU address bit 1 CPU address bit 2 CPU address bit 3 CPU address bit 4 CPU address bit 5 CPU address bit 6 CPU address bit 7 CPU port 1, bit 1. CPU port 1, bit 2. CPU port 1, bit 3. CPU port 1, bit 4. CPU port 1, bit 5. CPU port 1, bit 6. CPU port 1, bit 7. B B B B B B B B CPU port 2, high byte address, bit 0. CPU port 2, high byte address, bit 1. CPU port 2, high byte address, bit 2. CPU port 2, high byte address, bit 3. CPU port 2, high byte address, bit 4. CPU port 2, high byte address, bit 5. CPU port 2, high byte address, bit 6. CPU port 2, high byte address, bit 7. Dir. Nand-gate Serial-Flash CE(O) SI (I) SCK(O) SO(O) CLK (O) DAT0 (B) WP/ RE/ (O) (O) 8 DAT1 (B) DAT2 (B) Description SD/MMC Alternative function Probe2_0 Probe2_1 Probe2_2 Probe2_3 Probe2_4 Probe2_5 Probe2_6 Probe2_7 JUL. 10, 2008 Preliminary Version: 0.3 (Draft)
4.1.2. Storage media interface
No. Hex.
1 2 3 4 5 6 7 8
fmgpio0 fmgpio1 fmgpio2 fmgpio3 fmgpio4 fmgpio5 fmgpio6 fmgpio7
B B B B B B B B
CE/
(O)
RDY (I) ALE CLE (O) (O)
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No. 9 10 11 12 13 14 15 16 17 18 Hex. fmgpio8 fmgpio9 fmgpio10 fmgpio11 fmgpio12 fmgpio13 fmgpio14 fmgpio15 fmgpio16 fmgpio17 Dir. B B B B B B B B B B D0 D1 D2 D3 D4 D5 D6 D7 (B) (B) (B) (B) (B) (B) (B) (B) WE/ (O) Description DAT3 (B) CMD (B)
4.1.3. System
No. 1 2 3 4 5 6 7 Hex.
Testmode Lvdi xvss xtal27i xtal27o cp xvdd
4.1.4. AUDIO/SAR
No. 1 2 3 4 5 6 7 8 9 10 Hex. AVDD AVSS
VREFF
MICBIAS SAR0 SAR1 SAR2 MICINP MICINN ADFLT
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Dir. I Description testmode I Low power detect input Crystal pad ground PG I 27MHz crystal pad input O I 27MHz crystal pad output RC filter input to audio PLL Crystal pad power PG 3.3V Dir. PG Description 3.3V power for ADC PG O Ground for ADC Reference voltage for ADC O I Buffered voltage output suitable for electro-microphone-capsule biasing. SAR ADC channel I. I I I I O SAR ADC channel II. SAR ADC channel III. Microphone positive input. Microphone negative input. Anti-aliasing filter cap for ADC. 3.3V
4.1.5. SDRAM interface
No. 1 2 3 4 5 Hex. sdclk rasnn casnn mwenn ldqm Dir. O O O O O SDRAM clock SDRAM raw address strobe signal SDRAM column address strobe signal SDRAM write enable signal SDRAM data mask signal, low byte 9 JUL. 10, 2008 Preliminary Version: 0.3 (Draft) Description
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No. 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Hex. udqm cke md0 md1 md2 md3 md4 md5 md6 md7 md8 md9 md10 md11 md12 md13 md14 md15 ma0 Dir. O O B B B B SDRAM data mask signal, high byte SDRAM clock enable signal SDRAM data bus, bit 0 SDRAM data bus, bit 1 SDRAM data bus, bit 2 SDRAM data bus, bit 3 SDRAM data bus, bit 4 SDRAM data bus, bit 5 SDRAM data bus, bit 6 SDRAM data bus, bit 7 SDRAM data bus, bit 8 SDRAM data bus, bit 9 3.3V Description
25 26 27 28 29 30 31 32 33 34 35
ma1 ma2 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma10 ma11
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B B B B B B B SDRAM data bus, bit 10 B SDRAM data bus, bit 11 B B B B SDRAM data bus, bit 12 SDRAM data bus, bit 13 SDRAM data bus, bit 14 SDRAM data bus, bit 15 B SDRAM address bus, bit 0. The bus is also used for IO-trap. During IO-trap stage, the “ma” bus is an input bus. After the IO-trap stage, the bus is an output bus. B B B B B SDRAM address bus, bit 1 SDRAM address bus, bit 2 SDRAM address bus, bit 3 SDRAM address bus, bit 4 SDRAM address bus, bit 5 SDRAM address bus, bit 6 SDRAM address bus, bit 7 SDRAM address bus, bit 8 SDRAM address bus, bit 9 O O O O O O SDRAM address bus, bit 10 SDRAM address bus, bit 11 16M bit 64M bit BA0 BA1 NC 128M bit BA0 BA1 NC 256M/512M bit BA0 BA1 A12 O O O BA NC NC
36 37 38
ma12 ma13 ma14
4.1.6. Digital TV interface
No. Hex. Dir. CCIR601 1 2 3 4 digtv0 digtv1 digtv2 digtv3 B B B B DDX0 DDX1 DDX2 DDX3 LCD DDX0 DDX1 DDX2 DDX3 10 Description LCM D0 D1 D2 D3 PROBE Probe1_0 Probe1_1 Probe1_2 Probe1_3 JUL. 10, 2008 Preliminary Version: 0.3 (Draft)
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No. 5 6 7 8 9 10 11 12 13 Hex. digtv4 digtv5 digtv6 digtv7 digtv8 digtv9 digtv10 digtv11 digtv12 Dir. B B B B B B VSYNC DDX4 DDX5 DDX6 DDX7 DDX4 DDX5 DDX6 DDX7 DEM VSD Description D4 D5 D6 D7 RD CS A0 Probe1_4 Probe1_5 Probe1_6 Probe1_7
4.1.7. USB interface
No. 1 2 3 4 5 6 7 Hex. uvdd dp dm uvss rext vddtx vsstx
4.1.8. Video DAC interface
No. 1 2 3 4 5 Hex. avdd avss cout rset cbu Dir. PG
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B HSYNC DCLK HSD B DCLK WR D8 B DDX8 Dir. PG B Description USB transceiver analog power. 3.3V USB data plus. B USB data minus. PG O USB transceiver analog ground. External register pin PG TX power PG TX ground Description Analog power 3.3V PG O I Analog ground Composite video signal output DAC scale adjustment I Connect to power via a 0.1uF capacitor Dir. I I I I I I I I I I B Sensor data input bit 0. Sensor data input bit 1. Sensor data input bit 2. Sensor data input bit 3. Sensor data input bit 4. Sensor data input bit 5. Sensor data input bit 6. Sensor data input bit 7. Sensor data input bit 8. Sensor data input bit 9. Vertical synchronization signal 11 JUL. 10, 2008 Preliminary Version: 0.3 (Draft) TV decoder data input bit0 TV decoder data input bit1 TV decoder data input bit2 TV decoder data input bit3 TV decoder data input bit4 TV decoder data input bit5 TV decoder data input bit6 TV decoder data input bit7 Description
4.1.9. Sensor interface
No. 1 2 3 4 5 6 7 8 9 10 11 Hex. rgb0 rgb1 rgb2 rgb3 rgb4 rgb5 rgb6 rgb7 rgb8 rgb9 VD
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No. 12 13 14 15 16 HD MCLK PCLK sck sd Hex. Dir. B B B O B Horizontal synchronization signal Sensor master clock Sensor pixel clock SSISCL SSISDA Description
4.1.10. RTC
No. 1 2 3 Hex. xtalrtco xtalrtci xvdd
4.1.11. GPIO
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Hex. GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17
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Dir. O I Description 32768 crystal pad output 32768 crystal pad input RTC crystal pad power PG 3.3V Dir. B Description General purpose IO bit 0 Mshutter Flashctr B General purpose IO bit 1 B General purpose IO bit 2 Card-detect B B General purpose IO bit 3 General purpose IO bit 4 RXD TXD Power hold B B General purpose IO bit 5 General purpose IO bit 6 PWMDACA PWMDACB PWM0 PWM1 B B General purpose IO bit 7 General purpose IO bit 8 LCD_SEN shutter_en B General purpose IO bit 9 SD-WP detect B General purpose IO bit 10 General purpose IO bit 11 trap B suspend B B General purpose IO bit 12 General purpose IO bit 13 B B B B General purpose IO bit 14 General purpose IO bit 15 General purpose IO bit 16 General purpose IO bit 17 ROM_A16 (O) ROM_A17 (O) ROM_A18 (O) ROM_A19 (O)
4.1.12. Power/Ground
No. 1~5 6~10 11~15 Hex. Ovdd vss Dvdd Dir. PG PG PG IO PAD power IO/Core ground Core power 1.8V Description 3.3V
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4.2. IO-TRAP
The IO-TRAP circuit is used to set the hardware configurations of the SPCA1528A. function. The IO-TRAP configuration is as below: IO-trap IOTRAP[6], IOTRAP[0] External CPU selection. 2’bx0: Enable internal CPU. This is the normal configuration. 2’b10: Disable internal CPU, SPCA1528A is controlled by an external CPU via CPU interface. 2’b11: Disable internal CPU, SPCA1528A is controlled by an external CPU via sensor interface. Description Parts of the MA pins are used for the IO-TRAP
Pin Name MA[6],MA[0]
MA[1]
MA[5:2]
MA[7]
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IOTRAP[1] Fast reset selection. PLL reaches stable state. mode is used in chip test only. Boot mode selection. IOTRAP[5:2] 4’bxx1x: Boot from external NOR-type ROM. 4’b1x0x: Boot from UART. 4’b010x: ISP. 4’b0000: Boot from NAND. 4’b0001: Boot from SPI. UART selection. IOTRAP[7] 0: Normal mode. The GPIO [4:3] are used as GPIOs. 1: The GPIO [4:3] are used as UART.
and digital TV
1’b0: Normal mode. The internal reset control circuit keeps reseting SPCA1528A core until on chip
1’b1: Fast reset mode. The reset control circuit resets SPCA1528A core for 32 crystal clocks. This
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5. ELECTRICAL SPECIFICATION
5.1. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply Voltage relative to VSS Operating temperature Storage temperature HBM MM LatchUp Symbol VT VDD TOPT TSTG VHBM VMM It Value -0.4 to 4.0 -0.4 to 4.0 0 to +70 -55 to 125 Unit V V °C °C
5.2. DC Characteristics
DC Characteristics (TA＝25℃, VDD–VSS＝3.3V) Symbol VDD IDD
IDD
IDD
IDD
IDD
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> 100 Parameter Min. 3.0 Typ. 3.3 Max. 3.6 I/O operating voltage Core operating voltage Icore (Suspend) 1.62 1.8 1.98 T.B.D IIO (Preview) T.B.D Icore (Preview) Iddr (Preview) T.B.D T.B.D IIO (Snap) T.B.D Icore (Snap) Iddr (Snap) T.B.D T.B.D IIO (Still Playback) T.B.D Icore (Still Playback) Iddr (Still Playback) T.B.D T.B.D IIO (Video Clip) T.B.D Icore (Video Clip) Iddr (Video Clip) T.B.D T.B.D IIO (Video Playback) T.B.D Icore (Video Playback) Iddr (Video Playback) T.B.D T.B.D Parameter Input low voltage Input high voltage Output low current Output high current Output low current Output high current Output low current Output high current Schmitt trigger positive-going threshold 14 Min -0.3 0.7 VDD Typ. 4 -4 8 -8 12 -12 1.5 Max 0.3 VDD VDD+10% -
nt
> 2000 > 200
al i
ly n
V V mA Unit V V mA
mA
mA
mA
mA
IDD
mA
Table 5.2.2 DC Characteristics (TA＝25℃, VDD–VSS＝3.3V) Symbol VIL VIH IOL IOH IOL IOH IOL IOH VT ＋ Unit V V mA mA mA mA mA mA V JUL. 10, 2008 Preliminary Version: 0.3 (Draft)
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Symbol VT － VHYS IIL Parameter Schmitt trigger negative-going threshold Hysteresis voltage Input leakage current Min Typ. 1.2 0.3 1 Max Unit V V μA
5.3. RTC Parameters
Table 5.3 RTC Current Consumption Symbol IRTC
RTC accuracy: +/- 2.5 seconds/day
5.4. USB Interface Characteristics 5.4.1. USB DC Characteristics
Symbol
VIH VIHZ VIL VDI
VHSSQ
VOL VOH VCRS
VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK
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Parameter Min Typ. 2 Max Unit μA Current Consumption, VRTC＝3.3V Parameter Min. Typ. Max. Unit Input Levels (full speed) Input level high (driven) 2.0 V Input level high (floating) 2.7 3.6 V Input level low 0.8 V Differential input sensitivity 0.2 V Input Levels (high speed) High-speed squelch detection threshold (differential signal amplitude) 100 150 mV Output Levels (full speed) Output level low 0.0 0.3 V Output level high 2.8 3.6 V Output signal crossover voltage 1.3 2.0 V Output Levels (high speed) High-speed idle level -10.0 360 10.0 440 mV High-speed data signaling high mV High-speed data signaling low Chirp J level (differential voltage) Chirp K level (differential voltage) -10.0 700 -900 10.0 1100 -500 mV mV mV
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5.4.2. USB AC Characteristics
Full Speed Symbol Parameter Driver Characteristics TFR TFF TRFM Rise time Fall time Differential Rise and Fall time matching (TFR/TFF) Clock Timing 4 4 90 20 20 111.11 ns ns % Min. Typ. Max. Unit
TFDRATE
TFDEOP Paired JK jitter Paired KJ jitter
High Speed Symbol
THSR THSF
THSDRAT THSFRAM
5.5. Analog Audio Interface Characteristics
(TA =25°C, AVDD=3.3V±10%, DVDD=1.8V±10%)
Audio Analog-to-Digital Converter Electrical Characteristics: Parameter
Input voltage (MICINP-MICINN) Microphone input resistance
a l ly ti n On de e fi n Us o y C g ia lo ed no M ch m e us el T pl v u n -L e S i H or F
Average bit rate 12.00 Mb/s Full Speed Data Timing EOP width 166.67 ns Source jitter for paired JK jitter 1.00 ns Source jitter for paired KJ jitter 1.00 ns Parameter Min. Typ. Max. Unit Driver Characteristics Rise time Fall time 500 ps 500 ps Clock Timing High-speed data rate 479.760 480.240 b/s ps Microframe interval 124.9375 125.0625 Condition Min. Typ. Max. Unit Vpp ? F Hz dB dB dB dB dB dB dB Boost gain = 20dB PGA gain = 0dB AVAVDD33AD/13.75 Boost gain = 20dB 10K 20 0 -12 FIN = 1kHz, PGA gain = 0dB FIN = 1kHz, PGA gain = 0dB 20 2 1.5 0.15 85 10P 19,200 20 33 Gain Range Step Size Step Variation Gain Range Step Size Step Variation
Microphone input capacitance Frequency response Boost amplifier:
PGA:
Signal to noise ratio (SNR)
Total harmonic distortion + noise (THD+N)
-
-
0.01
%
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JUL. 10, 2008 Preliminary Version: 0.3 (Draft)

Preliminary
SPCA1528A
Microphone Bias Electrical Characteristics: (TA=25°C, AVAVDD33AD=3.3V±10%, DVDVDD18=1.8V±10%, ClockADMCLK=12.288MHz) Parameter Bias voltage Bias current source Output noise voltage 1kHz~20kHz Condition Min. Typ. 0.75*AVAVDD33AD 25 Max. 3.5 Unit V mA nV/(Hz^0.5)
5.6. Analog Video Interface Characteristics
Video DAC Parameter Power supply Resolution INL DNL Clock frequency Output voltage
5.7. General-Purpose ADC Characteristics
(TA =25°C, AVDD=3.3V±10%, DVDD=1.8V±10%) Parameter
Input voltage range Input resistance Resolution No missing codes
Differential Nonlinearity Integral Nonlinearity
a l ly ti n On de e fi n Us o y C g ia lo ed no M ch m e us el T pl v u n -L e S i H or F
Condition Min. 3.0 Typ. 3.0 9 ±3 Max. 3.6 Unit V bit LSB ±0.5 27 LSB MHz V Rset=390ohm 1.27 1.3 1.43 Condition Min. 0 Typ. Max. Unit V VDDAUD infinite 10 (SARIN0~SARIN2) ? bit 10 bit ±1 ±2 LSB ±2 ±4 LSB
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JUL. 10, 2008 Preliminary Version: 0.3 (Draft)

Preliminary
SPCA1528A
6. PACKAGE INFORMATION
6.1. Package Pin Assignment 6.1.1. LQFP 128-pin Package 1 (SPCA1525A)
a l ly ti n On de e fi n Us o y C g ia lo ed no M ch m e us el T pl v u n -L e S i H or F
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JUL. 10, 2008 Preliminary Version: 0.3 (Draft)

Preliminary
SPCA1528A
6.1.2. LQFP 128-pin Package 2 (SPCA1526A)
xgpio[3] DVDD xgpio[2] xgpio[1] xgpio[0] VSS OVDD xmd[0] xmd[1] xmd[2] xmd[3] xmd[4] xmd[5] xmd[6] xmd[7] xldqm xmd[15] xmd[14] xmd[13] xmd[12] xmd[11] DVDD VSS xmd[10] xmd[9] xmd[8] xudqm xsdramclk xcke xma[14] xma[11] OVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
a l ly ti n On de e fi n Us o y C g ia lo ed no M ch m e us el T pl v u n -L e S i H or F
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AVSSXTAL xtal27i xtal27o AVDDXTAL AVSSTX AVDDTX xdp xdm AVSSRX AVDDRX xrext AVDDDAC xcout xcbu xrset AVSSDAC xlvdi AVDDRTC xtalrtci xtalrtco AVSSRTC AVDDADC xsarin2 xsarin1 xsarin0 DVDD xgpio[12] VSS VD HD PCLK OVDD
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JUL. 10, 2008 Preliminary Version: 0.3 (Draft)

Preliminary
SPCA1528A
6.1.3. LQFP 176-pin Package
a l ly ti n On de e fi n Us o y C g ia lo ed no M ch m e us el T pl v u n -L e S i H or F
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JUL. 10, 2008 Preliminary Version: 0.3 (Draft)