EBGA reliability study
Reliability Study of High Density EBGA Packages Using the Cu Metallized Silicon
Liyu Yang and Joseph Bernstein
Abstract
The reliability of high density Enhanced Ball Grid Array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm2) and the die size (approximately 15 mm2) provided additional manufacturing and reliability challenges.
The die-edge defects induced during the wafer sawing process were exhibited to be the culpits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very roust based on the board level reliability testing results.
The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.
Keywords: Die cracking, Reliability, Thin film delamination, Wafer sawing.
1. Introduction 1.1 Background
The application of the silicon process using advanced copper interconnects has been on the rise in recent years. Driven by the low cost and available assembly infrastructures, there were significant efforts to make the Cu metallized silicon work with wire bonding technologies.
An EBGA package was generally preferred for high performance devices using the wire bonding technology (a package cross section was shown in Figure 1). The schematic drawing of the packages, which could dissipate eight to fifteen watts at a case temperature of 115 o C, was demonstrated in Figure 2 showing the solder balls and die attach fillets shown. The large package size plus the complexity of the silicon device (maximum 8-layer metallization) and substrate structures (up to four layers) presented many challenges for the package to meet a designed reliability performance. The uniqueness of the substrate structure was using the Cu heat spreader as a ground plane (GND) and the high density organic build-up layers on top of the GND [1, 2]. With little knowledge of interactions between the new substrate technology and the complex silicon technology, the package had a high level of reliability risks. Table 1 summarized the possible failure mechanisms for this package technology.
Figure 1: A cross section image of an EBGA package
Copper Heat Spreader
Silicon Die
Encapsulant
Die Attach layer
Cu
metallization and dielectric
layers
Au bonding wire
Figure 2: A schematic diagram of EBGA packages
Layer 1Heat Spreader/VSS layer
Silicon Die
Layer 2Layer 3Layer 4
Solder Ball
Bonding Wires
Encapsulant
Die attach layer
Dam
(a) A schematic diagram of the EBGA package stack-up
Silicon Die
Die attach fillet
Crack Line/Delamination Interface
Bond wire
(b) A cross section view showing the die and the die attach fillet height
Table 1: Possible failure mechanisms expected from the EBGA package reliability tests
Failure Category
Failure
Mechanism
Driving Forces
Thin-film
cracking and
delamination
CTE mismatch; passivation materials; die sizes; edge micro-
cracks from the wafer sawing; thermal mechanical stresses.
Die
Die cracking Mechanical loads during the processing; defects induced in
wafer saw process; thermo-mechanical stresses.
Die attach Interface
delamination Surface contaminations; oxidation and moisture absorption; voids at the interfaces; thermal mechanical stresses.
Broken
wires/lift wires Thermal mechanical stresses; wire bonding loop profiles; bonding parameters; stress conditions; bonding pad metal contaminations; die surface delamination.
Wire bonding
Bonding pad cratering Wire bonding defects; CTE mismatch and pad metallization/stack-ups. Wire bonding parameters.
Via
cracking/delam- nation Substrate Tg; CTE mismatch; stress concentrations; moisture ingression; adhesion strength degradation.
Interface delamination Substrate Tg; material CTE mismatch; poor substrate process controls; moisture absorption; Interface adhesion strengths; stress loads.
Solder mask cracking Surface flaws and stress concentration. Mechanical damages and CTE mismatch.
Substrates
Dielectric cracking Copper trace layouts; copper surface roughness; dielectric material properties; CTE mismatch and stress loads.
Encapsulant cracking CTE mismatch; stress concentration; stress loads and material properties.
Encapsulation
Encapsulant interface delamination CTE mismatch; stress concentration due to defects; material properties; moisture absorption; interface adhesion degradation; interface contaminations; passivation materials.
Solder joint cracking CTE mismatch; pad surface finishes; solder materials and test conditions.
Solder joint
Missing solder balls Handling; CTE mismatch; pad surface finishes and contaminants; mechanical impacts during ATE testing; trays.
One of the risks involving thermo-mechanical failures for the Cu metallization structures was thin film delamination and cracking. The delamination and cracking could happen during the wafer processing or during the package assembly [2,3, 4, 5]. The interface adhesion was critical to prevent the cracking and delamination failures [6]. The die edge cracking and thin film delamination were mainly caused by the deformation of the metallization and cracks of brittle passivation layers on die surfaces. These failures were highly dependent on the die sizes [7]. There was a dependence of the die edge cracking seen in FCBGA packages on wafer sawing processes used. The energy release rate increases significantly when the initial die edge defects sizes increased. It was pointed out that the size of initial die edge defects could be tolerated if right packaging materials were selected [8]. More over, the rigidness of the substrate significantly influenced the stress on the die. Although
copper interconnects are increasingly favored over aluminum interconnects for the process and the performance, the Cu silicon was more likely to have reliability risks and causing failures [9].
A large amount of reliability test data had been collected for EBGA packages using 0.18 μm Al metallization silicon and there were no catastrophic failures observed [1]. However, with the adoption of 0.13 μm copper metallization processes , there were unexpected challenges for this reliability study because of
(1) Eight Cu metallization layers in the silicon. The top metal layer was much thicker than other layers. Cu has a tendency to cause issues during wafer sawing. (2) The large package and die sizes.
(3) The substrate technology, including the variation of dielectric materials and the substrate cavity machining process. 1.2 Key Failure Mechanisms
(1)Die cracking and thin film delamination
A high failure rate due to die-edge cracks and the thin film delamination were observed during the EBGA reliability study. Extensive failure analyses revealed the cracks or the thin film delamination originated from the die edges, then extended into the interfaces of the copper metallization and dielectric layers. Figure 3 showed the views of the die cracks (seen after the decapsulation process) and the thin film delamination in the die (seen from FI
B analysis). Key factors influencing the die cracking mechanism were investigated, including wafer defects after sawing, assembly processes and materials, stress distributions due to the coefficient of thermal expansion (CTE) mismatches, and package configurations.
(a) Top view of the die cracks seen after the decapsulation process
Bonding pad Test pad Chipping after Live circuits on the die
With wire bonds
structures With chipping (scribe street)
wafer sawing
Crack lines
Guard ring
Bulk silicon
(b) The cross section view of thin film delamination at interfaces (FIB analysis)
Figure 3: Images of die cracks / the thin film delamination in the silicon
(2) Missing solder ball failures
Missing solder ball failures were common issues seen in BGA packages. The failures could be caused by pure intrinsic design issues, environmental conditions, test conditions, and/or materials used. In this case, missing ball failures were observed after automatic electrical testing (ATE). The pogo pins of the sockets applied large forces on the solder balls during the insertion, plus the momentum force due to misalignment between the solder balls and pin tips, the solder balls would be knocked off. In order to estimate the impact of missing ball failures on the solder joint reliability, both the ball pull and shear data were collected to verify the joint formation quality at the component level. In addition, a board level air-to-air temperature cycling test were conducted to estimate the lifetime of the solder joints.
The die cracking failures were dominant and would influence the product release. The focus of this paper would be on the die cracking / thin film delamination failures and the solder joint reliability.
2. Materials and Methods
2.1 Package and Silicon Attributes
The EBGA substrate was a multi-layer build-up structure with thick metal layer as a build-up base. The substrate was unique in terms of structures and manufacturing processes involved. A thick metal heat spreader functioned as a die attachment pad and a GND plane as well. A machined cavity in the substrate would be where the die was sitting in. Build-up circuit layers and dielectric layers were about 0.2 mm in thickness compared to a 0.8 mm thickness of the metal heat spreader. The coefficient of thermal expansion (CTE) of the substrate was not far different to that of Cu (e.g. 16 ppm/ o C). The impact of the CTE mismatch between the die and the substrate would be significant during the assembly and the subsequent reliability stress testing.
The package sizes studied were ranged from 35 mm to 45 mm square with a 1.49 mm in thickness. The test device was using the 0.13 μm Cu metallization silicon technology with a maximum eight-layer metal stack. The minimum scribe width on the wafer was 80 μm. The bonding pad structure was a Al cap on the Cu metallization. A combination of multiple layers of the metallization, a high copper density at the scribe and a large die size would challenge the reliability performance of the package. Table 2 showed the package and device attributes. Figure 4 showed a diagram of the substrate stack-up.
Table 2: Package and device attributes
Type Item Attributes
Type EBGA
Size & Thickness 45x45 mm2
x1.49 mm 35x35 mm2 x1.49 mm
2nd Level interconnects Au bonding wires
Ball count 1140 672
Ball size 0.65 mm in diameter
Solder mask opening 400 μm
Packages
Substrate layer count &
thickness
4 layers & 0.99 mm
Die size 15 x15 mm2 12.5x 12.5 mm2
# of bonding pads 1400 900
Die thickness 15 mil (381 μm)
Pad structure Al cap on Cu
Silicon
Metallization Cu
Microvia
Figure 4: The diagram of a substrate stack-up
The dielectric and copper metallization layers on the substrate were thin comparing with the Cu heat spreader layer. The thick Cu layer would influence the stresses on the die surface or the die edge significantly. In addition, the die was protected by a high CTE encapsulant and die attach materials, a large stress would be experienced on the die surface due to the CTE mismatch of the materials.
2.2 Key Modules of the Packaging Process
(1) Wafer preparation
The wafer thinning and sawing process would cause serious defects on the die edge and the die backside. The defects would act as stress concentration points for future failures. In addition, the presence of copper structures at scribe streets would increase peeling and chipping defects on the die edge during the wafer sawing. It was observed the higher of the density of the copper structures in the sawing path, the higher the risk of causing the die edge defects.
(2) Die attachment
The properties of die attach materials and their curing profiles were critical to stresses applied on the die. Plus, processes monitoring parameters includes the bonding line thickness and the fillet height of the die
attachment would contribute to the final stress distribution on the die. The surface flatness of the substrate cavity would affect the overall bonding line thickness, the die tilting angle as well as the fillet height.
(3) Wire bonding
Three different wire loop profiles were used to meet the bonding wire density needs and the specification of the solder ball stand-off heights after reflowing [10]. Because of the single tier structure of the substrates, there was a great challenge to achieve reliable wire bond contacts and the overall package specification, e.g. solder ball stand-offs.
(4) Liquid encapsulation
Encapsulation materials had different CTE values comparing to that of the silicon. As a result, a large thermal mechanical stress could be applied on the silicon during the thermal cycling and the encapsulant curing process. Low stress encapsulation materials were generally preferred to reduce the stress.
(5) Solder ball attachment and reflowing
The packages will need to go through a peak temperature shock as high as 220-260 o C during the solder reflowing process. Thermal stress generated during the reflowing process could cause the die cracking and the interface delamination. The solder joint reliability was evaluated through the board level temperature cycling test and/or other mechanical impact tests.
2.3 Experimental Set-up and Descriptions
Hypothesis studies ( in Table 3) showed the critical factors causing die-edge cracks and the silicon thin film delamination. Top suspects were associated with local damages on the die edge, as well as the stress generated during the assembly and the subsequent stress tests. Moreover, geometry variations from the die attach process would affect the stress distribution on the die significantly. A series of studies were conducted to validate the hypothesis. The board level solder joint reliability was proceeded to understand if missing ball failures was a long term threat to the package reliability performance.
Table 3: A hypothesis summary for the die crack and thin film delamination failures
Categories Characteristics Description
Eight-layer metal silicon processes
Silicon reliability data showed no die cracking failures found. Max die sizes used were around 13 mm for the qualification. Package types used were 225 PBGAs and CBGAs.
Scribe width and metal densities in the scribe A large amount of test structures were in the cutting path of the scribe street.
Silicon process
Die size
A biggest die size for this silicon technology used. Wafer sawing processes Peeling and chipping defects due to the sawing process. Sawing parameters and types of blades could be optimized. Assembly materials Low stress die attach materials and encapsulation materials needed to reduce the stress on the die.
Process parameters Materials volume, bonding line thickness and die attach fillet height controls.
Assembly process
Package substrate stack-ups and substrate materials
Structure effects on the stress distribution.
Blade degradation during the sawing A blade life and blade addressing cycle monitoring. Blade dressing should help improve the quality of the wafer sawing process.
Process excursion
Process set-ups
Damage of the silicon during the set-up, e.g. inter-layer delamination/cracks.
Package
intrinsic features
Package types
EBGA structures variation on the stress distribution on the die edge.
2.3.1 Wafer sawing study
The defects during the wafer sawing were the initiation points of the die cracking and the delamination at thin film interfaces. Cracks would extend with the help of the die-edge tensile stress associated with the CTE mismatch between the packaging materials, and process geometries, such as the fillet height of the die attach adhesives and the bonding line thickness (BLT). A dual step sawing approach was evaluated. The first step of the sawing was to cut into the scribe at a certain depth instead of cutting through the silicon, the second step was followed by cutting through the wafer using a narrower blade. The theory was to reduce the impacts of the metallization in the scribe streets on the edge of the die.
Figure 5 The schematic diagram of the test chip showing the scribe street
Figure 5 illustrated the top view of the die surfaces with scribe lines and test structures. Test structures were seen on both 80 μm and 240 μm scribe streets. The guard ring was implemented to prevent the peelings or the cracking into the live die area. An example of key sawing factors including blade grit sizes, cutting kerf widths, feed speeds, blade RPMs and first step cutting depths were shown in Table 4.
Table 4: Parameters of the dual step wafer sawing implemented
Items 1st Blade 2nd
blade Blade type A B Blade Grit size 2-4 μm 2-4 μm Kerf width 25~30 μm 20~25 μm Feed Spreed 35 mm/s 35 mm/s RPM 45k
45k
Cutting Depth
10 mil (254 μm)
5 mil (127 μm)
Additional studies related to the wafer sawing were carried out to help fully understand the mechanics of the die-edge cracking and thin film delamination failures, including
(1) A wider scribe street. By simulating a wider scribe street, the buffer zone between the guard ring and
the die edge would be larger, and the assumption was the die edge peeling damages could then be tolerated.
(2) Resin blades instead of mechanical diamond blades. Resin blades were soft comparing with diamond
blades. In theory, the stress on the die edge would be smaller by using resin blades, then caused less damages on the die edges.
Temperature cycling tests were used to evaluate the effectiveness of the wafer sawing schemes. The electrical test was performed to detect the failures. In addition, CSAM was used to help detect the cracking/delamination failures (sample images shown in Figure 6) effectively, even for very fine cracks underneath the die surface. Figure 7 showed typical damages on the die edges on both 80 um and 240 um scribe streets. The electrical test often showed few failures comparing with the results from the CSAM analysis.
Figure 7 Chipping damages at the die edges after the dual step wafer sawing
Bonding Chipping on 80 um Test pad in pads
Guard ring
pad
scribe street
the scribe st.
Bonding
Bonding wires
Die
delamination at the die edge
Die
Figure 6: CSAM images showing the die cracking /thin film delamination
2.3.2 Encapsulation and die attach materials study
One of the significant factors affecting the stress on the die was packaging materials, including the encapsulant and the die attach materials. There were a significant coefficient of thermal expansion delta between the silicon and the assembly materials, then thermomechanical stresses would be induced on the die surfaces and edges during the temperature cycling test. Low stress encapsulation materials and die attach materials were studied through Finite Element Analysis (FEA) simulation.
2.3.3 Package substrate and geometry study
Variations of the substrate stack-ups were studied. 1/8 3-D FEM model was constructed considering the symmetry of structures. Table 5 shows the key dimension of the package used in the FEA simulation.
Table 5: Package dimensions for the simulation study
Components Package Attributes
Package size, mm x mm 45x45 and 35x35
Die size, mm x mm 12.5 to 15.4
Cavity size, mm x mm 14 to 16.7
Cu thickness under the die, mm 0.387 to 0.466
Cu heat spreader thickness, mm 0.786
Solder mask thickness, mm 0.023 to 0.046
Cu/Dielectric thickness, mm 0.141 to 0.186
3. Experimental Results and Discussions
Table 6 listed overall reliability testing results during the package qualification.
Stress Types Conditions Test Results
(# of failures /total sample
size) Preconditioning JEDEC MSL 4 (peak Temp: 220
o C)
0/450
Temperature cycling 1000 cycles at condition “B” (-55
o C +125 o C) 12/230. Die edge cracking was the failure mechanism.
Unbias HAST 100 hrs at 130 o C/85% RH 0/119. High temperature bake 1000 hrs at 150 o C 0/231.
TC ‘X’: 1000 cycles (-40 o C to 85 o C) 0/38 after 1000 cycles.
Board level temperature
cycling test
TC ‘J’: 3500 cycles (0-100 o C) 0/30 after 7000 cycles.
Both the component level and board level reliability data were reported (shown in Table 6). The dominant failure mechanism was the die cracking/think film delamination which was seen after the temperature cycling test.
3.1 Impacts of wafer sawing methodologies
A high die cracking failure rate (over 10% @ 90% CL) was seen with EBGA packages using a single step wafer sawing scheme. By converting to a dual step wafer sawing process, which cut through the first 5-10 mils on the scribe street and then finish the cut using a narrow blade, a much lower failure rate (in the range of 2-3% @ 90% confidence level) due to the die cracking and thin film delamination was reported. However, it showed sawing damages and die cracking failures could not be eliminated by only optimizing the sawing methodology. Figure 8 showed the die edge cracking/chipping damages observed after the temperature cycling test. Clearly,
the cracks were already existed before the assembly (encapsulant were seen inside the crack lines) and the metal layers in the vicinity of the scribe street were pulling upwards due to the mechanical force from the wafer
sawing.
Bonding Au Cracking line Guard ring
wire
to wafer sawing
seen after wafer sawing
(a) A image from the decapsulation analysis
(b) A image from the FIB analysis
Figure 8: The thin film delamination and metal peeling in the vicinity of the scribe street The blade dressing process was critical to maintain a clean and controlled cutting edge. Experimental results demonstrated a blade dressing was required to be done every twenty five wafers and the blade needed to cut meters of silicon to make the dressing effective. 3.1.1 The influence of increasing scribe street width
Based on the available failure analysis data, the majority of the die cracking was seen in the narrow
scribe street (80 μm). A proposal to increase the scribes from 80 μm to 160 μm was evaluated. The
implementation was carried out by sacrificing one column of dice adjacent to a 80 μm street every other column to make a 160 um scribe street. The scribe of finished dice would have a 160 μm width on one side and a 240 μm scribe width on the other. As a result, the dead silicon area between the die edge and the guard ring was Bulk Silicon
about 70 μm and 110 μm respectively. Total 205 units were assembled and sent for the reliability testing for this study. Fifteen units from 205 sample units were seen die cracking right after 250 cycles of the temperature cycling test, and another twelve units failed after 500 cycles of the temperature cycling test, additional two units failed after 1000 cycles. The failure data was analyzed using non-parametric analysis since the distribution is unknown.
The error bound for the number of failures at each test intervals could be calculated as [11]
1
?±
n n
n (1)
Where n is the number of failures observed from known time intervals.
Taking a 250-cycle period as a time interval, and we observed 15 failures in the first interval. Using the
equation (1), we would have 11-19 failures for the same time interval and it would be constant as 15 failures. In the second 250 cycles interval, we observed 12 failures which was within the estimated bounds and the failure rate was constant. However, it was also obvious that the number if failures dropped significantly after 500 cycles. The majority of the failures were seen before 500 cycles with a constant failure and a very low failure numbers was seen between 500 and 1000 cycles.
The root causes for the failures was due to the serious metal peeling when the saw blade cut through the
bonding pads of the adjacent dice. The impacts of the peelings or micro-cracks due to the wafer sawing on final package failures were significant even with the increased scribe street width. 3.1.2 A resin blade study
It was clear that the wafer sawing using the resin blade presented the best visual images in terms of the
kerf width control and the size and number of chippings on the die edges (Figure 9). It demonstrated that the resin blades can significantly reduce the number of chipping as well as the size of the chipping at the die edges, especially in the area where metal structures were presented. Total 113 samples were built with the dice from the study and sent through the temperature cycling test. There were total four failures after 1000 cycles and the bounds for the failure at 1000 cycles intervals was 2-6. The reliability of the package was significantly improved with a failure rate of 2400 FIT based on an acceleration factor of 7.3 based on a 0-70C use conditions.
The dominant failures were early failures due to the initial defects of micro-cracks after the wafer
sawing process. The parts sawn using the resin blade did show a higher reliability. It demonstrated, with a right
sawing blade and optimized dual step sawing parameters, die cracking failures and thin film delamination failures could be reduced or eliminated in the field application. The resin blade approach presented a very robust reliability performance comparing with others.
Figure 9: Visual images of the defects after the wafer sawing using resin blades
Table 7: Summary of the dual step wafer sawing studies
Studies (Dual step sawing) Failure Rate
Reliability
Diamond blade study 9.417E-5 0.9243-0.9621 Resin blade study 5.213e-5 0.9561-0.9826 Wide scribe study
0.0003
0.8585-0.9268
3.2 Impacts of package attributes
FEA results validated that the large tensile stress was located at the edges of the die for both 35 mm and 45 mm EBGA packages. Similar die principle stresses were shown on the die surface during cycling tests as well. It demonstrated the impact of the substrate size on the stress was minimal. However, a variation of EBGA with different dielectric materials, thinner copper slug thickness and different cavity milling process generated smaller tensile stress on the die. Experimental results of the revised EBGA substrate using a thinner Cu heat spreader showed a much lower failure rate due to the die cracking and thin film delamination failure
Test Edge chipping 80 um scribe street
240 um scribe street
pads
Kerf width
Edge chipping
mechanisms. The difference on the die surface stress distribution was believed due to the Cu thickness and the cavity features of the substrates. Figure 10 showed the stress distribution on the die.
Figure 10: Die placement contour from the finite element analysis It should be pointed out that the stress force obtained in all cases was no way large enough to break a perfect silicon unless the silicon was flawed and micro cracks existed before the stress applied. The presence of the die edge chippings and peelings helped introduce the failures seen during tests. It should be mentioned that the die cracking failures were not observed in parts using a Aluminum metallization silicon. The silicon using Al metallization layers showed a very stable and a clean sawing edge and there was no subsequent die cracking failures found after the assembly and the stress testing.
3.3 Impacts of assembly materials for encapsulation and die attachment
From the physical understanding, low stress die attach and encapsulation materials can reduce the stress on the die and then reduce the possibility of die cracking failures. Table 8 showed the three material types studied.
Table 8: low stress die attach and encapsulation material properties used in FEA
Encapsulan t Categories Material properties A Modulus, Mpa 9.4231221.531174.02++?T T
CTE, ppm/C T T T E 4323.00022.006323+??
B Modulus, Mpa T T T 64.2822176.10013.023+?
CTE, ppm/C T T T E 6616.0004.006523?+??
C Modulus, Mpa T T T 78.4388653.1002.023+?
CTE, ppm/C
T T T E 3233.00019.006223?+??
Die Attach Adhesive
E Modulus, Mpa T T T 01.128572.00006.023+?
CTE, ppm/C T T T E 6717.00054.006723?+??
F Modulus, Mpa T e 0153.065200?
CTE, ppm/C 138
G Modulus, Mpa T T T E 4209.90402.005423+??
CTE, ppm/C
T T T E 9052.00018.006223+??
The finite element study showed the low stress encapsulation materials would help reduce the substrate warpage and the stress on the die significantly. Type C die attach materials generated a smallest warpage on the packages. The combination of the type A encapsulant and the type C die attach material generated the smallest stress on the die surface. The application of low stress materials will reduce the risks of the die cracking and thin delamination failures. The accurate stress analysis with corner/biomaterial interface involved can use a fracture mechanics based approach to predict the failures [12]. 3.4 Impacts of the assembly process control
The fillet height of the die attach materials as well as the substrate cavity flatness were identified as two key process factors influencing the die cracking and the thin film delamination failures of the packages. The cavity milling process during the substrate manufacturing process created cavity surfaces with a high peak area and the pin-wheel like effects. For example, lower areas toward the outer regions of the cavity (shown in Figure 11). The potential risk of the cavity surface variation was causing the interfacial delamination and bonding line thickness variations, then affecting the fillet height of the die attach materials. Finite element analysis showed if the fillet height was over 95% of the die thickness, the tensile stress would significantly increased (Figure 12). Failure analysis demonstrated that several failed units had fillet heights over 93%-100% of the die thickness. The recommended fillet height criteria were 50% and no higher than 75% of the die thickness.
The limitation of the die cavity flatness was controlled at ~2 mil to reduce their impacts on the process variations. The cavity flatness might be driven by the stress relief during the panel singulation or the machining process. A 2nd pass machining operation might help improve the cavity flatness and the die-attach process control. The cavity profile /flatness with a large die size resulted a much poorer die attach control.
Figure 11: A contour plot showing the substrate cavity flatness measurement
(Example flatness: ~95.92 μm)
Figure 12: The impact of the die fillet height on a die stress of EBGA packages
3.5 Solder joint reliability study
Corner of Center of the cavity
the cavity
Peak line