CS-221342-DS-3-CSR8811A08 0.5mm WLCSP DataSheet

Features BlueCore ? CSR8811? A08 0.5mm WLCSP

■Dual-mode Bluetooth ?/Bluetooth low energy

radio ■Fully qualified Bluetooth v4.0 IC ■Bluetooth Smart Ready ■Can form part of Bluetooth v4.0 + HS system ■Class 1 or Class 2 Bluetooth power levels ■High-sensitivity Bluetooth and Bluetooth low

energy receiver

■Full-speed Bluetooth operation with full piconet

and scatternet support

■On-chip balun and minimal BOM

■Low-power selectable 1.2 to 3.6V I/O

■Integrated I/O and core regulators

■High-speed UART port (up to 4Mbps)

■HFP v1.6 wide-band speech supported on-chip

■On-chip encoding of SBC and aptX ? codecs for

A2DP music streaming

■PCM/I 2S digital audio interface

■Support for IEEE 802.11 coexistence

■Green (RoHS and no antimony or halogenated

flame retardants)

■Optimised for use on low-cost PCBs

Bluetooth v4.0

Bluetooth low energy

Production Information

CSR8811A08-ICXR-R

Issue 3

General Description The CSR8811? is a product from CSR's Connectivity Centre. It is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems including EDR to 3Mbits/s and Bluetooth low energy.CSR8811's dual-mode radio enables it to connect to the billions of Bluetooth products already on the market, as well as a new generation of Bluetooth low energy devices.Bluetooth low energy allows mobile devices to exchange simple data sets with very low consumption.Example use cases include watches, medical sensors and fitness trainers that can operate for many years from a small coin cell battery. CSR8811 brings Bluetooth low energy to the mobile phone, allowing it to connect to this new class of devices.When used with CSR Synergy Software? and a CSR UniFi ? wireless chip, CSR8811 provides a system fully qualifiable to the Bluetooth v4.0 + HS system for faster file transfer.

This family of Bluetooth products includes:■CSR8311? A08 for automotive applications ■CSR8510? A06 for PCs and USB dongles Products requiring a standalone Bluetooth low energy radio should use CSR1000? or CSR1001? ICs.

Applications

■Low-cost phones, Feature phones, Smartphones

■

Personal Navigation Devices (PNDs)

■Portable media Players (PMPs)

CSR designed CSR8811 to reduce PCB area and the

number of external components:

■The high-power Class 1 Bluetooth transmitter

removes the requirement for external

amplification.

■The balun is integrated, which results in a single-

ended 50Ω port that does not require additional

matching components.

■Integrated LDOs, with minimum decoupling

components, allow the chip to be operated directly

from the battery or a regulated supply.

■No requirement for external inductors.

This ensures that production costs are minimised.

The device incorporates auto-calibration and BIST

routines to simplify development, type approval and

production test.

To improve the performance of both Bluetooth and

IEEE 802.11b/g/n co-located systems a wide range of

coexistence features are supported.

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

Device Details

Bluetooth low energy

■Dual mode Bluetooth low energy radio

■Supports simultaneous Bluetooth BR/EDR and multiple low energy connections

■Support for on-chip AES encryption

■Adaptive Bluetooth/Bluetooth low energy scheduler ■On-chip whitelist support

Bluetooth Radio

■On-chip balun (50Ω impedance in TX and RX modes)

■No external trimming is required in production

■Bluetooth v4.0 specification compliant

Bluetooth Transmitter

■Class 1, Class 2 and Class 3 support without need for external power amplifier or TX/RX switch

■DQPSK and 8DPSK

Bluetooth Receiver

■Integrated channel filters

■Digital demodulator for improved sensitivity and co-channel rejection

■Real time digitised RSSI available on HCI interface ■Fast AGC for enhanced dynamic range

■Channel classification for AFH

■DQPSK and 8DPSK

Baseband and Software

■Internal RAM allows full-speed data transfer, mixed voice and data, and full piconet operation, including all medium rate packet types

■Logic for forward error correction, header error control, access code correlation, CRC,

demodulation, encryption bit stream generation,

whitening and transmit pulse shaping. Includes

support for eSCO and AFH

■Transcoders for A-law, μ-law and linear voice from host and A-law, μ-law and CVSD voice over air Bluetooth Stack

■CSR's Bluetooth Protocol Stack runs on the on-chip

MCU in the configuration Standard HCI over UART Synthesiser

■Fully integrated synthesiser requires no external

VCO varactor diode, resonator or loop filter

■Compatible with external clock 19.2MHz to 40MHz

■Can be operated from external crystal

Physical Interfaces

■UART interface with programmable baud rate up to

4Mbits/s

■BCSP, H4, H4DS and H5 support

■PCM/I2S interface

■Synchronous serial interface up to 4Mbits/s for

system debugging

Auxiliary Features

■Power management includes digital shutdown, and

wake up commands with an integrated low power

oscillator for ultra low power Park/Sniff/Hold mode

■Auto Baud Rate setting, depending on host

interface

■On-chip linear regulators:

■ 1.8V output from typical 2.5 to 4.8V (5.5V for

short periods) input (load current 100mA)

■Low dropout linear regulators producing

internal supply voltages from 1.8V, and

allowing operation directly from a battery

■Power-on-reset cell detects low supply voltage

■Arbitrary sequencing of power supplies is permitted

Package

■28-ball 2.57 x 3.21 x 0.6mm, 0.5mm pitch WLCSP

Note:

This IC has the same package size as the

previous CSR8811 WLCSP 0.5mm pitch

versions and the CSR8810 WLCSP 0.5mm

pitch ICs.

■Can be used on low-cost PCBs without the need for

blind vias

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

Document History

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

Status Information

The status of this Data Sheet is Production Information.

CSR Product Data Sheets progress according to the following format:

Advance Information

Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-production Information

Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

All electrical specifications may be changed by CSR without notice.

Production Information

Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

Production Data Sheets supersede all previous document versions.

Life Support Policy and Use in Safety-critical Applications

CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.

CSR Green Semiconductor Products and RoHS Compliance

CSR8811 devices meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).

CSR8811 devices are also free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products.

Trademarks, Patents and Licences

Unless otherwise stated, words and logos marked with ? or ? are trademarks registered or owned by CSR plc or its affiliates. Bluetooth ? and the Bluetooth ? logos are trademarks owned by Bluetooth ? SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners.

The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc and/or its affiliates.

CSR reserves the right to make technical changes to its products as part of its development programme.

While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors.

Refer to https://www.360docs.net/doc/af2030125.html, for compliance and conformance to standards information.CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

Contents

Device Details (2)

Functional Block Diagram (3)

1Package Information (10)

1.1Pinout Diagram (10)

1.2Device Terminal Functions (11)

1.3Package Dimensions (13)

1.4PCB Design and Assembly Considerations (14)

1.5Typical Solder Reflow Profile (14)

2Bluetooth Modem (15)

2.1Bluetooth Radio Ports (15)

2.1.1BT_RF (15)

2.2Bluetooth Receiver (15)

2.2.1Low Noise Amplifier (15)

2.2.2 RSSI Analogue to Digital Converter (15)

2.3RF Transmitter (15)

2.3.1IQ Modulator (15)

2.3.2Power Amplifier (16)

2.4Bluetooth Radio Synthesiser (16)

2.5Baseband (16)

2.5.1Burst Mode Controller (16)

2.5.2Physical Layer Hardware Engine (16)

3Clock Input and Generation (17)

3.1Input Frequencies (17)

3.2External Reference Clock (17)

3.2.1Input: XTAL_IN (17)

3.2.2XTAL_IN Impedance in External Mode (18)

3.2.3Clock Start-up Delay (18)

3.3Crystal Oscillator: SYS_CLK and XTAL_OUT (18)

3.3.1Load Capacitance (20)

3.3.2Frequency Trim (20)

3.3.3Transconductance Driver Model (21)

3.3.4Negative Resistance Model (21)

3.3.5Crystal PS Key Settings (22)

3.4Timing for Frequency (22)

3.5Sleep Clock (22)

4Bluetooth Stack Microcontroller (24)

4.1Programmable I/O Ports (24)

4.2WLAN Coexistence Interface (24)

5Memory Interface and Management (25)

5.1Memory Management Unit (25)

5.2System RAM (25)

5.3Internal ROM Memory (5Mb) (25)

6Host Interface (26)

6.1 UART Interface ................................................................................................................................... 26CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

6.1.1UART Configuration While Reset is Active (27)

7Programming and Debug Interface (28)

8Audio Interfaces (29)

8.1PCM Interface (29)

8.1.1PCM Interface Master/Slave (29)

8.1.2Long Frame Sync (30)

8.1.3Short Frame Sync (31)

8.1.4Multi-slot Operation (31)

8.1.5GCI Interface (32)

8.1.6Slots and Sample Formats (32)

8.1.7Additional Features (33)

8.1.8PCM Timing Information (34)

8.1.9PCM_CLK and PCM_SYNC Generation (38)

8.1.10PCM Configuration (38)

8.2Digital Audio Interface (I2S) (41)

9Power Control and Regulation (46)

9.1High-voltage Linear Regulator (46)

9.1.1Regulator Control (46)

9.2Low-voltage VDD_DIG Linear Regulator (46)

9.3Low-voltage VDD_ANA Linear Regulator (46)

9.4Low-voltage VDD_AUX Linear Regulator (46)

9.5Reset (47)

9.6Power-on Sequencing (47)

10Example Application Schematic (48)

11Electrical Characteristics (49)

11.1Absolute Maximum Ratings (49)

11.2Recommended Operating Conditions (49)

11.3Input/Output Terminal Characteristics (50)

11.3.1High-voltage Linear Regulator (50)

11.3.2Low-voltage VDD_DIG Linear Regulator (50)

11.3.3Low-voltage VDD_AUX Linear Regulator (50)

11.3.4Low-voltage VDD_RADIO Linear Regulator (50)

11.3.5Digital (51)

11.3.6Clock (51)

11.3.7Sleep Clock (52)

11.4ESD Protection (52)

12Software (53)

12.1On-chip Software (53)

12.1.1BlueCore HCI Stack (53)

12.2Off-chip Software (54)

12.2.1CSR Synergy (54)

13CSR Green Semiconductor Products and RoHS Compliance (55)

14Ordering Information (56)

14.1Chip Marking (56)

15Tape and Reel Information (57)

15.1Tape Orientation (57)

15.2Tape Dimensions ................................................................................................................................. 57CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

15.3Reel Information (58)

15.4Moisture Sensitivity Level (59)

16Document References (60)

Terms and Definitions (61)

List of Figures

Figure 1.1Pinout Diagram (10)

Figure 2.1Simplified Circuit BT_RF (15)

Figure 3.1Crystal Driver Circuit (19)

Figure 3.2Crystal Equivalent Circuit (19)

Figure 3.3Example Sleep Clock Application Circuit (23)

Figure 6.1Universal Asynchronous Receiver Transmitter (UART) (26)

Figure 6.2Break Signal (27)

Figure 8.1PCM Interface Master (29)

Figure 8.2PCM Interface Slave (30)

Figure 8.3Long Frame Sync (Shown with 8-bit Companded Sample) (30)

Figure 8.4Short Frame Sync (Shown with 16-bit Sample) (31)

Figure 8.5Multi-slot Operation with 2 Slots and 8-bit Companded Samples (31)

Figure 8.6GCI Interface (32)

Figure 8.716-bit Slot Length and Sample Formats (33)

Figure 8.8PCM Master Timing Long Frame Sync (35)

Figure 8.9PCM Master Timing Short Frame Sync (36)

Figure 8.10PCM Slave Timing Long Frame Sync (37)

Figure 8.11PCM Slave Timing Short Frame Sync (38)

Figure 8.12Digital Audio Interface Modes (43)

Figure 8.13Digital Audio Interface Slave Timing (44)

Figure 8.14Digital Audio Interface Master Timing (45)

Figure 12.1Example Firmware Architecture (53)

Figure 12.2CSR Synergy Framework (54)

Figure 14.1CSR8811A08 Chip Marking (56)

Figure 15.1Tape Orientation (57)

Figure 15.2Tape Dimensions (57)

Figure 15.3Reel Dimensions (58)

List of Tables

Table 3.1External Clock Specifications (17)

Table 3.2Crystal Specification (19)

Table 6.1Possible UART Settings (27)

Table 8.1PCM Master Timing (34)

Table 8.2PCM Master Mode Timing Parameters (34)

Table 8.3PCM Slave Timing (36)

Table 8.4PCM Slave Mode Timing Parameters (37)

Table 8.5PSKEY_PCM_LOW_JITTER_CONFIG Description (39)

Table 8.6PSKEY_PCM_CONFIG32 Description (40)

Table 8.7Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 41CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

Table 8.8PSKEY_DIGITAL_AUDIO_CONFIG (42)

Table 8.9Digital Audio Interface Slave Timing (44)

Table 8.10I2S Slave Mode Timing (44)

Table 8.11Digital Audio Interface Master Timing (45)

Table 8.12I2S Master Mode Timing Parameters, WS and SCK as Outputs (45)

Table 11.1Sleep Clock Specification (52)

Table 11.2ESD Handling Ratings (52)

Table 15.1Tape Dimensions (58)

Table 15.2Reel Dimensions (58)

List of Equations

Equation 3.1Load Capacitance (20)

Equation 3.2Trim Capacitance (20)

Equation 3.3Frequency Trim (20)

Equation 3.4Pullability (20)

Equation 3.5Transconductance Required for Oscillation (21)

Equation 3.6Equivalent Negative Resistance (21)

Equation 8.1PCM_CLK Frequency Generated Using the Internal 48MHz Clock (38)

Equation 8.2PCM_SYNC Frequency Relative to PCM_CLK (38)

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

1

Package Information 1.1Pinout Diagram

G

-

T W

-0

04

7

4

.

3

.2

Orientation from top of device

A 124356

B C D E E1C1B1A1E2D2C2B2A2E3D3C3A3E4D4C4B4A4E5D5C5B5A5E6D6

C6

B6

A6

Figure 1.1: Pinout Diagram

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

1.2Device Terminal Functions

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

1.4PCB Design and Assembly Considerations

This section lists recommendations to achieve maximum board-level reliability of the 2.57 x 3.21 x 0.6mm WLCSP 28-ball package:

■NSMD lands (that is, lands smaller than the solder mask aperture) are preferred because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation.

■Ideally, use via-in-pad technology to achieve truly NSMD lands. Where this is not possible, a maximum of one trace connected to each land is preferred and this trace should be as thin as possible, this needs to take into consideration its current carrying and the RF requirements.

■35μm thick (1oz) copper lands are recommended rather than 17μm thick (0.5oz). This results in a greater standoff which has been proven to provide greater reliability during thermal cycling.

■Use 300μm ±10μm land diameters to achieve optimum reliability.

■Solder paste is preferred to flux during the assembly process, because this adds to the final volume of solder in the joint, increasing its reliability.

■When using a nickel gold plating finish, keep the gold thickness below 0.5μm to prevent brittle gold/tin intermetallics forming in the solder.

■The WLCSP is designed so that ball lands do not lie on top of sensitive areas of the active silicon.■WLCSP components often have the ball array mid-point offset to the centre of the component outline. This requires careful consideration during component PCB footprint design.

1.5Typical Solder Reflow Profile

See Typical Solder Reflow Profile for Lead-free Devices for information.

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

2Bluetooth Modem

2.1Bluetooth Radio Ports

2.1.1BT_RF

CSR8811 contains an on-chip balun which combines the balanced outputs of the PA on transmit and produces the balanced input signals for the LNA required on receive. No matching components are needed as the receive mode

impedance is 50Ω and the transmitter has been optimised to deliver power in a 50Ω load.

G

-

T W

-0

4

7

99

.

1

.

2

BT_RF

Figure 2.1: Simplified Circuit BT_RF

2.2Bluetooth Receiver

The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die.Sufficient out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to GSM and W-CDMA cellular phone transmitters without being desensitised.

For both basic rate and EDR, an ADC digitises the IF received signal.

2.2.1Low Noise Amplifier

The LNA operates in differential mode and takes its input from the balanced port of the on-chip balun.

2.2.2 RSSI Analogue to Digital Converter

The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain is changed according to the measured RSSI value, keeping the mixer input signal within a limited range. This improves the dynamic range of the receiver, so improving performance in interference limited environments.

2.3RF Transmitter

2.3.1IQ Modulator

The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

2.3.2Power Amplifier

The internal PA output power is software controlled and configured through a PS Key. The internal PA on the CSR8811 has a maximum output power that enables it to operate as a Class 1, Class 2 and Class 3 Bluetooth radio without requiring an external RF PA.

2.4Bluetooth Radio Synthesiser

The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v4.0 specification.

2.5Baseband

2.5.1Burst Mode Controller

During transmission the BMC constructs a packet from header information previously loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception, the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor during transmission and reception.

2.5.2Physical Layer Hardware Engine

Dedicated logic performs the following:

■Forward error correction

■Header error control

■Cyclic redundancy check

■Encryption

■Data whitening

■Access code correlation

■Audio transcoding

Firmware performs the following voice data translations and operations:

■A-law/μ-law/linear voice data (from host)

■A-law/μ-law/CVSD (over the air)

■Voice interpolation for lost packets

■Rate mismatches CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

3Clock Input and Generation

The Bluetooth reference clock for the system is generated from an external clock source frequency of between 19.2and 40MHz, or an external crystal.

All CSR8811 internal digital clocks are generated using a phase locked loop, which is locked to the frequency of the clock source.

3.1Input Frequencies

CSR8811 must be configured to operate with the chosen reference frequency (using the appropriate PS Key, etc.).This can be any reference frequency between 19.2 and 40MHz. Until a clock reference frequency has been explicitly set from an off-chip source no radio operation is possible. This can be done using the debug and programming interface. Otherwise the default, along with various internal firmware checks, enables communication over the host interface for a limited range of baud rates. Once a host communication is established, PS Keys pertaining to the clock scheme can be configured. This depends on the firmware build. Full details are in the Release Note for the CSR8811 firmware build on https://www.360docs.net/doc/af2030125.html, .

3.2External Reference Clock

3.2.1Input: XTAL_IN

CSR8811 can use a TCXO reference clock input into XTAL_IN. In this mode, ground XTAL_OUT.

The external clock can be either a digital level square wave or sinusoidal, and this may be directly coupled to XTAL_IN without the need for additional components. A digital level reference clock gives superior noise immunity, as the high slew rate clock edges have lower voltage to phase conversion. If peaks of the reference clock are either below VSS or above VDD_AUX, it must be driven through a DC blocking capacitor (approximately 33 to 100pF) connected to XTAL_IN.

Table 3.1 lists the specification for the external reference clock signal.

CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

Table 3.1: External Clock Specifications

(a)The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies

(b)VDD_AUX is 1.35V nominal

(c)If driven via a DC blocking capacitor max amplitude is reduced to 700mV pk-pk for non 50:50 duty cycle

3.2.2XTAL_IN Impedance in External Mode

The impedance of XTAL_IN does not change significantly between deep sleep and active modes.

3.2.3Clock Start-up Delay

CSR8811 hardware incorporates a default 5ms delay after the assertion of the system clock request signal before running firmware. This is suitable for most applications using an external clock source. However, there are scenarios where the clock is not guaranteed to either exist or be stable after this period. Under these conditions, CSR8811 firmware provides a software function that extends the system clock request signal by a period stored in

PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from 1ms to 31ms. Zero is the default for 5ms delay.

This PS Key enables system optimisation where clock stability latencies are longer or shorter than 5ms, keeping the current consumption of CSR8811 as low as possible. CSR8811 consumes about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.

Clock accuracy must be within 20ppm after the delay specified in PSKEY_CLOCK_STARTUP_DELAY. This is to ensure that the radio meets the RF specification. Refer to your product software documentation for a description of PSKEY_CLOCK_STARTUP_DELAY.

3.3Crystal Oscillator: SYS_CLK and XTAL_OUT

CSR8811 contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator. Figure 3.1 shows the external crystal is connected to pins XTAL_IN, XTAL_OUT.CSR8811 A08 0.5mm pitch WLCSP Data Sheet

G

-

T

W

-0

19

1

.5

.

2

Figure 3.1: Crystal Driver Circuit

Figure 3.2 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors.

Figure 3.2: Crystal Equivalent Circuit The resonant frequency is trimmable with the crystal load capacitance. CSR8811 contains variable internal capacitors to provide a fine trim.

Table 3.2: Crystal Specification

The CSR8811 driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT.CSR8811 A08 0.5mm pitch WLCSP

Data Sheet

3.3.1Load Capacitance

For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. CSR8811 provides some of this load with the capacitors C trim and C int. The remainder should be from the external capacitors labelled C t1 and C t2. C t1 should be three times the value of C t2 for best noise performance. This maximises the signal swing and slew rate at XTAL_IN (to which all on-chip clocks are referred).

Crystal load capacitance, C l is calculated using Equation 3.1:

C l=C int+(C t2+C trim)C t1 C t2+C trim+C t1

Equation 3.1: Load Capacitance

Note:

C trim = 3.4pF nominal (mid-range setting)

C int = 1.5pF

C int does not include the crystal internal self capacitance; it is the driver self capacitance.

3.3.2Frequency Trim

CSR8811 enables frequency adjustments to be made. This feature is typically used to remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load capacitance with an on-chip trim capacitor, C trim. The value of C trim is set by a 6-bit word in PSKEY_ANA_FTRIM. Its value is calculated as follows:

C trim=125fF×PSKEY_ANA_FTRIM

Equation 3.2: Trim Capacitance

The C trim capacitor is connected between XTAL_IN and ground. When viewed from the crystal terminals, the combination of the tank capacitors and the trim capacitor presents a load across the terminals of the crystal which varies in steps of typically 125fF for each least significant bit increment of PSKEY_ANA_FTRIM.

Equation 3.3 describes the frequency trim.

Δ(F x) F x =pullability×0.110×(C t1

C t1+C t2+C trim)(ppm/LSB)

Equation 3.3: Frequency Trim

Note:

F x = crystal frequency

Pullability is a crystal parameter with units of ppm/pF

Total trim range is 0 to 63

If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 3.4.

?(F X)?(C l)=F X?

C m

2(C l+C O)2

Equation 3.4: Pullability CSR8811 A08 0.5mm pitch WLCSP

Data Sheet