PKA345L Datasheet Rev[1][1][1].1____ 20100720
Small, Low Power, 3-Axis ±3g
Di PROKEY
TECHNOLOGY
gital Accelerometer
FEATURES 3-axis sensing
Small, 4mm x 4mm 20-pin LGA package Low power consumption
Operating V oltage: 2.4V to 3.6V 11 bits ADC with SPI and I2C digital interface
Over 2,500g shock survival
Operating temperature: -20℃ to +75℃
APPLICATIONS
Low power, motion detecting and tilt-sensing applications. Mobile devices Gaming controller Free-fall protection
Image stabilization
Sports and health devices
DESCRIPTION
The PKA345L is a compact low power 3-axis digital accelerometer. It includes a digital interface able to provide the
measured acceleration to the external world through SPI and I2C serial interface. The PKA345L is well suited for portable mobile device and game controlling applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock.
FUNCTION BLOCK
P r
e l i
m
i n
a r
y &
C
o n
f i
d e n
t i
Small, Low Power, 3-Axis ±3g
Digital Accelerometer
PROKEY
TECHNOLOGY
ELECTRICAL CHARACTERISTICS
All the parameters are specified @A VDD=3.0V , T=25 unless otherwise noted ℃
Specification Parameter Condition Min.
Typ.
Max.
Unit
Operating V oltage A VDD T=-25℃~+75℃ 2.4 3 3.6 V Digital V oltage DVCC T=-25℃~+75℃ 2.4 3 3.6 V Interface V oltage VIF T=-25℃~+75℃ 1.7 3.6 V Current consumption (Active)
250
500 μA
Current consumption (Shutdown) CE=0V
5 μA
Measurement Range -3 3 G Gain
880 V/V
Sensitivity 11 Bit ADC 330 code/G
Zero g offset level 25℃ -135 135 mG
Frequency Response refer to Digital Detection response rate
refer to Digital
Low Level Input voltage
CE, SCL, SDI, SDO -0.3 0.2 VIF
V High Level Input voltage CE, SCL, SDI, SDO 0.8 VIF VIF+0
.3
V
Low Level Output voltage INT 0.1 VIF V
High Level Output voltage INT 0.9 VIF
V
Temp. sensor sensitivity 11 Bit ADC 16 code/℃Temp. sensor accuracy 0~75℃
-3 0 3
℃ Operating temp. range -25 75
℃
P r
e l i
m
i n
a r
y &
C
o n
f i d e
n
t i a l
PIN ASSIGNMENT Pin No.
Name
Description
1 DGND Digital ground
2 DVCC Digital power
3 AVDD Analog power
4 AGND Analog ground
5 GND Power ground
6 INT2 Interrupt 2
7 NC No connection
8 NC No connection
9
Reserved Reserved and do not connect
10 NC No connection
11 AVDD Analog power
12 CE Chip enable
13 DVCC Digital power
14 SCK Digital interface
15 NC No connection 16 SDI
Digital interface
17 SDO Digital interface
18 INT1 Interrupt 1
19 CS Digital interface 20 NC
No connection
Digital Interface Pin Name Description
CS I2C/SPI enable ( 0:I2C; 1:SPI ) SCK (SCL)
I2C/SPI clock
P r
e l
i
m
i n
a r
y
&
C
o n
f i
d e
n
t i a l
SDI
I2C :I2C serial data (SDA) SPI :SPI serial
data input (SDI)
SDO
I2C :LSB of I2C device address SPI :SPI serial data output (SDO)
I2C Serial Interface
PARAMETER Symbol Min. Typ. Max. Unit SCL clock frequency SCL - - 400 kHz Clock low period t LOW 1.2 - - us Clock high period t HIGH 0.6 - - us Bus free to new start t BUF 1.2 - - us Start hold time t HD.STA 0.6 - - us Start setup time t SU.STA 0.6
- - us Data-in hold time t HD.DAT 0
- - us Data-in setup time t SU.DAT
100 - - ns Stop setup time t SU.STO 0.6 - - us Data-out hold time t DH
50
-
-
ns
I2C Timing Waveform
I2C Slave address Slave Address RW Slave Address + RW Read/Write Fix Sdo
001110 0 0 0011 1000 (38h) Write 001110 0 1 0011 1001 (39h) Read 001110
1
0011 1010 (3Ah)
Write
P r
e l i
m
i n
a r
y &
C
o n
f i
d e n
t i a l
001110 1
1
0011 1011 (3Bh)
Read
I2C Access Format
SPI Serial Interface
PARAMETER Symbol Min. Typ. Max. Unit CS setup time
t s0 300 - - ns Data setup time t s1 150 - - ns CS hold time t h0 150 - - ns Data hold time
t h1 150 - - ns SCLK pulse low width t w1L 160 - - ns SCLK pulse high width t w1H 160 - - ns CS pulse low width t w2
1.0
-
-
us
SPI Single Read
P r
e l i
m
i n
a r
y &
C
o n
f i
d e
n
t i a l
Register Mapping Table Name Reg. address
Default Type Comment
SPI (13-bit) I2C (8-bit)
Hex Binary
Binary
Tout[10:3] 00 0 0000 0000 0000
0000 0000 r Tout[10:3] Tout[ 2:0] 01 0 0000 0000 0001
0000 0001
r Tout[ 2:0] Yout[10:3] 02 0 0000 0000 0010 0000 0010
r Xout[10:3] Yout[ 2:0] 03 0 0000 0000 0011 0000 0011
r Xout[ 2:0] Xout[10:3] 04 0 0000 0000 0100
0000 0100
r Yout[10:3] Xout[ 2:0] 05 0 0000 0000 0101 0000 0101 r Yout[ 2:0] Zout[10:3] 06 0 0000 0000 0110 0000 0110
r Zout[10:3] Zout[ 2:0] 07 0 0000 0000 0111
0000 0111
r
Zout[ 2:0] Ctrl_1 08 0 0000 0000 1000
0000 1000 0000 0000 r/w Int enable; Filter setting
Ctrl_2 09 0 0000 0000 1001
0000 1001 0100 0011 r/w Freefall threshold Ctrl_3 0A
0 0000 0000 1010 0000 1010 0000 1000 r/w Click threshold Ctrl_4 0B
0 0000 0000 1011
0000 1011
0000 0000 r
Interrupt flag
Ctrl_1 (08h)
FFIE YIE XIE ZIE Tms1 Tms0 N1 N0
Name Function
FFIE Freefall interrupt enable XIE
X-axis click interrupt enable
P r
e l i
m
i n
a r
y &
C
o n
f i
d e n
t i
a l
YIE Y-axis click interrupt enable ZIE Z-axis click interrupt enable Tms1 Tms0 Sampling period select
N1 N0
Average order select FFIE ﹕FreeFall interrupt enable control register. If FFIE=1 and FreeFall event
occurred (All X, Y, Z-axis signals are less than FreeFall threshold), INT pin will be latched to logic-1.
XIE ﹕X-axis click interrupt enable register. If XIE=1 and X-axis click event
occurred, INT pin will be latched to logic-1.
YIE ﹕Y-axis click interrupt enable register. If YIE=1 and Y-axis click event
occurred, INT pin will be latched to logic-1.
ZIE ﹕Z-axis click interrupt enable register. If ZIE=1 and Z-axis click event
occurred. INT pin will be latched to logic-1.
Bandwidth table
Ctrl_2 (09h)
FFth[7] FFth[6] FFth[5] FFth[4] FFth[3] FFth[2] FFth[1] FFth[0] FFth[7:0]﹕FreeFall threshold control register with 6mg per code. The effective setting range from A6h (996mg) to 01h (6mg) and the default value is 43h (402mg). Ctrl_3 (0Ah)
---- ---- ---- ----
Clickth[3]Clickth[2]
Clickth[1] Clickth[0]
n
a r
y &
C
o n
f i
d e n
t i a l
Clickth[3:0]﹕Click threshold control register with 194mg per code. The effective
setting range from 0Fh (2.91g) to 01h (194mg) and the default value is 08h (1.552g). Ctrl_4 (0Bh)
---- FF_Int Y_Int_P Y_Int_N
X_Int_P X_Int_N
Z_Int_P Z_Int_N
Ctrl_4 register is interrupt status register. The INT pin is latched to logic-1 when interrupt occurred and user can read this register to observe what kinds of interrupt are triggered. The INT pin will pull to logic-0 after reading this register. FF_Int ﹕FreeFall interrupt flag.
X_Int_P ﹕X-axis positive direction click flag. When X_Int_P=1, it means
X-axis signal ever larger than positive click threshold and the smaller than it. X_Int_N ﹕X-axis negative direction click flag. When X_Int_N=1, it means X-axis signal ever smaller than negative click threshold and then larger than it. Y_Int_P ﹕Y-axis positive direction click flag. When Y_Int_P=1, it means Y-axis signal ever larger than positive click threshold and then smaller than it. Y_Int_N ﹕Y-axis negative direction click flag. When Y_Int_N=1, it means
Y-axis signal ever smaller than negative click threshold and then larger than it. Z_Int_P ﹕Z-axis positive direction click flag. When Z_Int_P=1, it means Z-axis
signal ever larger than positive click threshold and then smaller than it.
Z_Int_N ﹕Z-axis negative direction click flag. When Z_Int_N=1, it means Z-axis
signal ever smaller than negative click threshold and then larger than it.
Package Bottom View
i
m
i n
a r
y &
C
o n
f i
d e n
t i a l