使用MATLAB和Simulink设计高级通信系统

MATLAB
Simulink
统系信通级高计设 统系信通级高计设 统系信通级高计设 统系信通级高计设
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2010
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5/27/2010
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Fires, Beacons, Smoke Signals
范规行执可的统系信通 范规行执可的统系信通 范规行执可的统系信通 范规行执可的统系信通
作工续后 证验和现实计设 计设的统系信通的定特 绍介
Telegraph
Carrier Pigeon
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程日议会 程日议会 程日议会 程日议会

5/27/2010
1980s
1990s
* Gordon Gekko – Wall Street, 1987
Today and Beyond
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Communications Systems Design
Challenges
Fast Changing Standards
o o
What if we could…
Do Faster Design Iterations
Rich libraries of pre-built blocks for multiple domains & applications Rapid system construction and faster simulations
High Data-Rate Transceivers
Have Reusable and Reconfigurable Designs
o o o
OFDM, MIMO within 802.16e, 802.20m, 802.11n, LTEadvanced Receiver Synchronization, Symbol/Timing Recovery, Equalizers Multi-Rate, Feedback, State Machines
System Complexity
Use Integrated Design and Simulation Platform
o o o
Incorporate RF, baseband, and control logic components Include and co-simulate analog, mixed-signal, and digital designs Reuse intellectual property in C, MATLAB, HDL
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Demo: Model-Based Design Workflow
Weaver's "Third Method" of SSB Generator TX
**About the design: Bandlimited audio input (250-3250 Hz) is translated by it's approximate center freq (1600 Hz) and filtered to create a complex baseband spectrum centered at DC. This complex spectrum is then translated to the desired RF output frequency and re-combined to create a real (bandpass) signal.
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Model-Based Design for Communication Systems
RESEARCH REQUIREMENTS
The process we followed:
Collect Requirements and Define Specifications
o Collected requirements like audio signal bandwidth, RF carrier frequency, etc o Created Simulink executable model, simulated behavioral model to verify against specs TEST & VERIFICATION TEST & VERIFICATION
DESIGN Baseband PHY Layer
RF
RX Sync
OFDM/ OFDMA
DPD
Fixed Point
Design Elaboration and Prototyping
o Elaborated and prototyped model to include additional details such as filter designs, AGC, polyphase filters, interp/decim, ddc, duc and RF o Added implementation details such as fixed-point conversion, partition the model to match HW architecture
IMPLEMENTATION C, C++
MCU DSP
VHDL, Verilog
FPGA ASIC
Implementation
o Generated target specific C and HDL code with automatic code generation and co-simulation capabilities
Continuous Verification Radio Hardware
o Verify against requirements during every stage of the process
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Communications Design Successes
AT4
Develop test systems for LTE wireless equipment
"Our physical layer model in MATLAB and Simulink enabled us to better understand the LTE specifications, and Model-Based Design enabled us to verify that our FPGA implementation conformed to those specifications."
BridgeWave Communications
Deliver high-capacity data links for wireless backhaul
"MathWorks tools enabled us to evaluate different design approaches and parameters, verify the design, and then examine the details of our implementation. We tested and simulated all aspects of the system before building a hardware prototype."
ETRI
Develop and prove a complex 4G communications design
"The intuitive block diagram environment of Simulink enabled us to implement our base station system design precisely and ensure optimal synchronous performance." 15
Executable Specifications of Communications System
RESEARCH REQUIREMENTS
DESIGN Baseband PHY Layer TEST & VERIFICATION
Our Goal
Quickly construct a functional baseline executable model from specification Verify the design against requirements Interact with design and rapidly iterate and prototype the design Run fast simulations
RF
RX Sync
OFDM/ OFDMA
DPD
Fixed Point
IMPLEMENTATION C, C++
MCU DSP
VHDL, Verilog
FPGA ASIC
Radio Hardware 16
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QPSK Transceiver from Specification
Modulation: QPSK Constellation: Gray Code Data Rate: 1Mbps RRCOS Filter Group Delay: 3 Rolloff = .25; Upsample Factor: 8 Verify System with AWGN Channel
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Verify Design: AWGN Channel, BER Analysis and BERTool
BERTool
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Demo: Speeding Up Simulation
Simple techniques to try:
Modeling Tip Baseline Graphics Disabled Frame Based Simulink Accelerator TOTAL SPEED UP Simulation Time 30 seconds 3.7 seconds 3.3 seconds 0.1 seconds Speed Up Factor N/A 8.1 0.12 33 300X
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Low Bit Error Rate and Other Intensive Computations
Don't let graphics be the bottleneck
Turn off scopes after you have debugged the model
Use frame-based processing
Frames are sequences of samples, grouped together for efficient execution
Use Simulink Accelerator
Additional optimizations are performed during initialization
Use parallel computing ("server farm")
Use PCT to distribute tasks on multi-core processes Use MDCS to distribute tasks on computing cluster
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Task Parallel Applications
Worker
TOOLBOXES
BLOCKSETS
Worker Worker
Worker
Task 1
Task 2
Task 3
Task 4
Time
Time
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Parallel Computing with MATLAB
No code changes
Implicit Multithreaded MATLAB Built-in Toolbox Support:
Optimization Toolbox Genetic Algorithm and Direct Search Bioinformatics Toolbox Model Calibration Toolbox SystemTest Simulink Design Optimization
Replace for loop
Task Parallel
parfor
Some code changes
job and tasks
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Parallel Computing
with MATLAB and Simulink
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Large Datasets (Data Parallel)
11 26 41 12 27 42 13 28 43 14 29 44 15 30 45 16 31 46 17 32 47 17 33 48 19 34 49 20 35 50 21 36 51 22 37 52
11 26 41 12 27 42 13 28 43 14 29 44 15 30 45 16 31 46
TOOLBOXES
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BLOCKSETS
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IEEE 802.11a System
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Summary:
Executable Specifications of Communications System
Quickly constructed a functional baseline executable model by using libraries of pre-defined communications algorithms Verified the designs per specifications using qualitative methods (Scatter plots, spectrum scopes, eye diagrams) and quantitative methods (BER, SNR, etc) Rapidly iterated and prototyped the design with interactive, tunable executable model and advanced visualizations Increased simulation speed through options such as frame based processing, Simulink Accelerator and parallel computing
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Advanced Communication System Designs
RESEARCH REQUIREMENTS DESIGN Baseband PHY Layer
RF
MCU
计设的统系信通的定特 计设的统系信通的定特 计设的统系信通的定特 计设的统系信通的定特
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范规行执可的统系信通 绍介 作工续后 证验和现实计设
RX Sync
OFDM/ OFDMA
程日议会 程日议会 程日议会 程日议会
Designs that typically require domain expertise
RF Receiver Synchronization OFDM/OFDMA Digital Pre-Distortion Fixed Point MAC Layer Control Mixed Signal
TEST & VERIFICATION
DPD MAC Layer
IMPLEMENTATION C, C++
DSP
VHDL, Verilog
FPGA ASIC
Radio Hardware
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How to Bridge the Gap Between Engineers Who Speak Different Languages?
RF
Eb/N0 Amplitude@nominal 1 Intersymbol interference Delay spread BER
Huh?
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How to Bridge the Gap Between Engineers Who Speak Different Languages?
Noise figure Power@50 S-parameters IP3
Huh?
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Share RF behavior between RF engineer and Communication System engineer
RF Blockset
"Here's the specs"
"Design and simulate the behavior of RF systems and components in a wireless system"
"Here's the verification model"
RF Toolbox
"Design and analyze networks of RF components"
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RF Blockset Key Features
"Design and simulate the behavior of RF systems and components in a wireless system"
Fast, baseband-complex, time-domain modeling
–
Compatible with Simulink modeling paradigm
High fidelity simulation with measured network parameter data files Cascade components with RF connection lines:
–
Network parameters and noise figure of:
Filters, Transmission lines, Linear and nonlinear amplifiers, Linear and non-linear mixers
Visualize frequency response with rectangular and polar plots and Smith charts
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Example: IEEE 802.11a System
Demo >> wlan_eml_rf
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Voice of Customers: Challenges in Receiver Design and Simulation
Modeling decoupled clocks/logic in transmitter and receiver
"We need asynchronous models because nodes are running on their own clocks. We need a system-level model to produce asynchronous clocks for the transmitter and receiver models." "Even with one transmit-receive link, you have asynchronous clocks. In wireless, with multiple users, you have hundreds of them."
RX Sync
Designing and simulating receiver synchronization algorithms
"One of the biggest challenges of radio design is that the receiver and transmitter are not synchronized." "Major problem of radio design is synchronization." "We need models and examples for users."
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Receiver Synchronization
Transmitter (Tx) Modulator DAC Radio
Preamble
Data Symbols
Path Delay: 4 s Doppler Shift: 150 Hz
Detect preamble to find start of data frame
DAC: 8.0001 MHz ADC: 7.9999 MHz
Tx Carrier: 2440.03 MHz Rx LO: 2439.98 MHz
Data Symbols
Demodulator
Synchronization
ADC
Radio
Receiver (Rx)
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Carrier Synchronization
Loop Filter Phase Detector K1 ej(w0*n - θ)
arg()
K2 Z-1
Synchronization
DDS
e-j(0*n - θ)
ej()
Z-1
Rice, M. (2008). Digital Communications: A Discrete-Time Approach, Prentice Hall.
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Carrier Recovery Design
Error Detection algorithm
– Calculate rotation from ideal QPSK constellation points
ej(w0*n - θ)
Phase Detector
arg()
P+I Loop Filter
– Set gain constants to produce desired step response
Loop Filter K1
DDS
– Phase accumulator and complex sinusoid generator
DDS
K2 Z1
ej()
Demo >> edit SyncTest1.m >> CarrierSyncSolution_eml
Z-1
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Carrier Synchronization with MATLAB
Connect to Simulink Built in communication functions
Synchronization loop Custom Functions
Data visualization
Memory and persistence
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5/27/2010
QPSK Receiver Synchronization: Complete Solution
Timing Recovery
– – – – Error Detector Loop Filter Timing Control Unit Farrow Fractional Delay Filter
RX Sync
MATLAB for:
Algorithm design
Simulink for:
Closed loop control Complex timing relationships Interactivity and visualization Self documenting design
Demo >> cont_time_sync
Carrier Recovery
Error Detector Loop Filter DDS Multiplier
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System Level OFDM Model
OFDM Specs
– 64 tones, 48 carrying data, 4 carrying pilots, 12 guard band tones – 4-QAM modulation for each data tone – 1 Mbps data rate
Standard Channel Impairments
– Phase/Frequency Offset – Dispersive Channel – AWGN – I/Q imbalance
End-to end BER Simulation
Demo >> ofdm_basic
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