M21L216128A-10T中文资料

SRAM

128 K x 16 SRAM

HIGH SPEED CMOS SRAM

FEATURES

ORDERING INFORMATION

T Fast access times : 10, 12, and 15ns T Fast OE access times : 5, 6, and 7ns T Single +3.3V ± 0.3V power supply

T Fully static -- no clock or timing strobes necessary T All inputs and outputs are TTL-compatible T Three state outputs

T Center power and ground pins for greater noise immunity T Easy memory expansive with CE and OE options T Automatic CE power down

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44-pin 400mil SOJ

44-pin 400mil TSOP (TypeII)

PRODUCT NO.Acess Time

(ns)

PACKING TYPE M21L216128A-10J SOJ M21L216128A-10T 10

TSOP M21L216128A-12J SOJ M21L216128A-12T 12

TSOP M21L216128A-15J SOJ M21L216128A-15T

TSOP

GENERAL DESCRIPTION

The M21L216128A is a high speed, low power asynchronous SRAM containing 2,097,152 bits and organized as 131,072 by 16 bits, it is produced by high performance CMOS process.

This device offers center power and ground pins for improved performance and noise immunity. Static design

eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE ), separate byte enable controls (LB and HE ) and output enable (OE ) with this organization.

PIN ASSIGNMENT

SOJ Top View

TSOP (TypeII) Top View

123456789A4A3A2A1A0C E DQ1DQ2DQ3444342414039383736A5A6A7OE H B LB DQ 16DQ 15DQ 1410111213141516171819202122DQ 4V C C G N D DQ 5DQ 6DQ 7DQ 8W E A16A15A14A13A12

35343332313029282726252423

DQ 13G N D VC C DQ 12DQ 11DQ 10DQ9N C A8A9A10A11N C

1234567891011A4A3A2A1A0C E D Q 1D Q 2D Q 3D Q 4V C C G N D D Q 5D Q 6D Q 7D Q 8W E A16A15A14A13A12

4443424140393837363534A5A6A7O E H B LB D Q 16D Q 15D Q 14D Q 13G N D V C C D Q 12D Q 11D Q 10D Q 9N C A8A9A10A11N C

12131415161718192021223332313029282726252423

Block Diagram

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512 X 4096MEMORY ARRAY

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??a???Pin Descriptions

Pin No.Symbol Description

1 - 5, 18 - 22,24-27, 4

2 - 44

A0 - A16Address Inputs 6

Chip Enable Input 7 - 10, 13 - 16,29 - 32, 35 - 38

DQ1 - DQ16

Data Inputs/Outputs 17WE Write Enable Input

39LB Lower Byte Enable Input (DQ1 to DQ8)40

Higher Byte Enable Input (DQ9 to DQ16)

41OE

Output Enable Input 11, 33VCC Power 12, 34GND Ground 23, 28

No Connection

ABSOLUTE MAXIMUM RATINGS *

Voltage on V CC Supply Relative to Vss … ……-0.5V to +4.6V V IN …………………………………………..….-0.5V to V CC +1.0V Operating Temperature, Topr ………………….. 0C ° to +70C °Storage Temperature (plastic) ……………….-55C °to +125C °Junction Temperature ……………………………………+125C °Power Dissipation …..…………………………………….…1.0W Short Circuit Output Current ………………………………50mA

*Stresses greater than those listed under Absolute Maximum. Ratings may permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATIONS

(All Temperature Ranges ; V CC = 3.3V ± 0.3V unless otherwise noted)

DESCRIPTION

CONDITIONS

SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage V IH 2.2V CC +0.5V 1,2Input Low (Logic 0) Voltage V II -0.50.8V 1,2

Input Leakage Current 0V ≤V IN ≤ V CC I LI -1010μA Output Leakage Current Output(s) disable 0V ≤V OUT ≤ V CC I LO -55

μA Output High Voltage I OH = -4.0 mA V OH 2.4

V 1Output Low Voltage I OL = 8.0 mA

V OL 0.4V 1Supply Voltage

V CC

3.0 3.6V

1MAX DESCRIPTION

CONDITIONS

SYMBOL

-10-12-15UNITS NOTES Power Supply

Current : Operating Device selected; CE ≤V IL ; V CC =MAX;f=f MAX ; outputs open I CC 190160130mA 3

TTL Standby CE ≥ V IH ; V CC =MAX; f=f MAX I SB1353025mA CMOS Standby

1CE ≥V CC -0.2; V CC = MAX;

all other inputs ≤ GND +0.2 or ≥V CC -0.2;all inputs static ; f=0

I SB2

CAPACITANCE

DESCRIPTION

CONDITIONS SYMBOL

MAX UNITS NOTES Input Capacitance

C I 6pF 4Input/Output Capacitance(DQ)

T A =C 25°; f=1 MHz

V CC =3.3V

C I/O

AC ELECTRICAL CHARACTERISTICS

(Note 5)(All Temperature Ranges; V CC =3.3V±0.3V)

-10-12-15Notes

UNIT DESCRIPTION SYMBOL

MIN MAX MIN MAX MIN MAX

Read Cycle

Read Cycle Time t RC101215ns

Access access time t AA101215ns

Chip Enable access time t ACE101215ns

Output hold from address change t OH344ns

Chip Enable to output in Low-Z t CLZ344ns4,7 Chip disable to output in High-Z t CHZ567ns4,6,7 Output Enable access time t OE567ns

Output Enable to output in Low-Z t OLZ000ns

Output Disable to output in High-Z t OHZ567ns4,6 Byte Enable access time t BE678ns

Byte Enable to output in Low-Z t BLZ000ns4,7 Byte disable to output in High-Z t BHZ567ns4,6,7 Write Cycle

Write cycle time t WC101215ns

Chip Enable to end of write t CW889ns

Address valid to end of write, with

t AW889ns

OE HIGH

Address setup time t AS000ns

Address hold from end of write t WR000ns

Write pulse width t WP2101011ns

Write pulse width, with OE HIGH t WP1889ns

Data setup time t DW567ns

Data hold time t DH000ns

Write disable to output in Low-Z t OW345ns4,7 Byte Enable to output in High-Z t WHZ567ns4,6,7 Byte Enable to end of write t BW889ns

TRUTH TABLE

MODE

DQ1-DQ8

DQ9-DQ16POWER LOW BYTE READ (DQ1-DQ8)L H L L H Q HIGH-Z ACTIVE HIGH BYTE READ (DQ9-DQ16)L H L H L HIGH-Z Q ACTIVE WORD READ (DQ1-DQ16)L H L L L Q Q ACTIVE LOW BYTE WRITE (DQ1-DQ8)L L X L H D HIGH-Z ACTIVE HIGH BYTE WRITE (DQ9-DQ16)L L X H L HIGH-Z D ACTIVE WORD WRITE (DQ1-DQ16)

L L X L L D D ACTIVE L

X X H H HIGH-Z HIGH-Z ACTIVE OUTPUT DISABLE

H H X X HIGH-Z HIGH-Z ACTIVE STANDBY

HIGH-Z

STANBY

AC TEST CONDITIONS

Input plus levels 0V to 3.0V Input rise and fail times 1.5ns Input timing reference levels 1.5V Output reference levels 1.5V

Output load

See Figures 1 and 2

351DQ

5pF

Z0 =5030pF

50 3.3V 317è

Vt=1.5V

Fig.1 OUTPUT LOAD EQUIVALENT

Fig.2 OUTPUT LOAD EQUIVALENT

NOTES

1. All voltages referenced to GND (VSS).

2. Overshoot : V IH≤+6.0V for t≤t RC /2.

Undershoot : V IL≤-2.0V for t≤t RC /2.

3. I CC is given without output current. ICC increases with greater output loading and faster cycle times.

4. This parameter is sampled.

5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.

6. Output loading is specified with CL=5pF as in Fig.2. Transition is measured±500mV from steady static voltage.

7. At any give temperature and voltage conditions, t CHZ is less than t CLZ and t WHZ is less than t OW

8. WE is High for Read cycle.

9. Device is continuously selected. Chip enable and output enables are held in their active state.

10. Address valid prior to, or coincident with, latest occurring chip enable.

11. t RC=Read Cycle Time.

12. Chip Enable and Write Enable can initiate and terminate a Write cycle.

13. Capacitance derating applies to capacitance different from the load capacitance shown in

Fig. 1.

Timing Waveforms Read Cycle 1(8, 9)

Read Cycle 2(7, 8, 9, 10)

A d d r e s s

t R C

t C

t A A

D o u t

: D O N 'T C A R E : U N D E F I N E D

A d d r e s s

t R C

t A A

t C L Z

t B L Z t O L Z

C E

O E

D o u t

t C H Z

t O H Z

H B ,L B

t A C E t B E

t O E

t B H Z

Write Cycle 1(7, 12, 13)

(Write Enable Controlled with Output Enable OE active LOW)

D O N 'T C A R E

U N D E F I

N E D

A d d r e s s

t W C

t W R

t B W

C E

H B ,L B

W E

Di n

t C W t D H

D o u t

t A S

t W H Z

t W P 2

t D W

t O W

t A W

Write Cycle 2(12, 13)

(Write Enable Controlled with Output Enable OE active HIGH)

D O N 'T C A R E

U N D E F

I N E D

A d d r e s s

t W C

t W R

t B W

C E

H B ,L B

W E

Di n

t C W t D H

D o u t t A S

t W P 1

t D W

t A W

H I G H -Z

Write Cycle 3(12, 13)

(Chip Enable Controlled)

D O N 'T C A R E

U N D E F I

N E D

A d d r e s s

t W C

t W R

t B W

C E

H B ,L B

W E

D i n

t C W t D H

D o u t t W P 1

t D W

t A W

H I G H -Z

t A S

Write Cycle 4(12, 13)

(Byte Enable Controlled)

D O N 'T C A R E

U N D E F

I N E D

A d d r e s s

t W C

t B W

t W R

t A S

C E

H B ,L B

W E

D i n

t C W

t D H

D o u t t W P 1

t D W

t A W

H I G H -Z

PACKING DIMENSIONS

44-LEAD SOJ SRAM(400mil)

DIMENSION ( INCH )DIMENSION ( MM ) SYMBOL

MIN NOM MAX MIN NOM MAX A0.1280.1380.148 3.25 3.51 3.76

A10.082-- 2.08--

A20.025--0.60--

b0.015-0.0200.38-0.51

b10.015-0.0180.38-0.46

c0.007-0.0130.18-0.21

c10.0070.0080.0110.180.200.28

D 1.120 1.125 1.13028.4528.5828.70

E0.4350.4400.44511.0511.1811.30

E10.3940.4000.40510.0110.1610.29

e0o10o0o10o

e0.050BSC 1.27 BSC

PACKING DIMENSIONS

44-LEAD TSOP(II)SRAM(400mil)

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max

A 1.200.047

A10.050.150.002 0.006

A20.95 1.00 1.050.0370.0390.042

B0.300.450.0120.018

B10.300.350.400.0120.0140.016

C0.120.210.0050.008

C10.100.160.0040.006

D18.2818.4118.540.7200.7250.730

ZD0.805 REF0.0317 REF

E11.5611.7611.960.4550.4630.471

E110.0310.1610.290.3950.4000.4

L0.400.590.690.0160.0230.027

L10.80 REF0.031 REF

e0.80 BSC0.0315 BSC

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