PEB20591中文资料

Data Sheet, DS4, March 2001

Wired

Communications

Edition 2001-03-01

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München, Germany

? Infineon Technologies AG 2001.

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Infineon T echnologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon T echnologies Office in Germany or our Infineon T echnologies Representatives worldwide (see address list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.

Infineon T echnologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

Wired

Communications

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VIP, VIP-8

Versatile ISDN Port

PEB 20590 Version 2.1

PEB 20591 Version 2.1

Data Sheet, DS4, March 2001

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at https://www.360docs.net/doc/c217316946.html,

ABM ?, AOP ?, ARCOFI ?, ARCOFI ?-BA, ARCOFI ?-SP, DigiTape ?, EPIC ?-1, EPIC ?-S, ELIC ?, FALC ?54, FALC ?56, FALC ?-E1, FALC ?-LH, IDEC ?, IOM ?, IOM ?-1, IOM ?-2, IPAT ?-2, ISAC ?-P, ISAC ?-S, ISAC ?-S TE, ISAC ?-P TE, ITAC ?, IWE ?, MUSAC ?-A, OCTAT ?-P, QUAT ?-S, SICAT ?, SICOFI ?, SICOFI ?-2, SICOFI ?-4, SICOFI ?-4μC, SLICOFI ? are registered trademarks of Infineon Technologies AG.

ACE ?, ASM ?, ASP ?, POTSWIRE ?, QuadFALC ?, SCOUT ? are trademarks of Infineon Technologies AG.

PEB 20590, PEB 20591PRELIMINARY Revision History:2001-03-01DS4

Previous Version:01.00

Page

Subjects (major changes since last revision)

Page 15Pull-ups for the signals TMS, TDI, TRST Page 34ID-Code for TAP controller Page 29Maximum wander tolerance Page 35VIP version register

Page 46Primary inductance for recommended S/T transformer Page 46External S/T Receiver Circuitry Page 38-Page 45

Electrical Characteristics

Note:This revision history is not 100% complete.

Table of Contents Page

1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2Logic Symbol Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1Overview of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2U PN Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2U PN Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.3Receive PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.4Receive Signal Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3S/T Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2S/T Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3Receive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3.1LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3.2LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.4Reference Clock Selection in LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.5Receive Signal Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4IOM-2000 Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1IOM-2000 Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.1.1Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.1TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4Analog Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5Monitoring of Code Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5Recommended 15.36-MHz Crystal Parameters . . . . . . . . . . . . . . . . . . . . 41

Table of Contents Page

5.6AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.7REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.8Upn Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.9IOM-2000 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.10JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.11U PN Transmitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.12S/T Transmitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1VIP External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.1Recommended Line Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.2U PN Interface External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.3S/T Interface External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2Wiring Configurations in LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3Loop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

8Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

List of Figures Page Figure1Top-Level Block Diagram of the VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure2Logic Symbol PEB 20590 (72 of 80 Pins used). . . . . . . . . . . . . . . . . . . 6 Figure3Logic Symbol PEB 20591 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure4VIP in Mixed S/T and U PN Line Cards (e.g. 8 S/T and 16 U PN). . . . . . . 7 Figure5VIP in a Small PBX Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure6DELIC-PB and VIP in a PC Card for 8/16 S/T Interfaces . . . . . . . . . . . 8 Figure7Pin Diagram, PEB 20590. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure8Pin Diagram, PEB 20591. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure9U PN Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure10AMI Coding on the U PN Interface in VIP . . . . . . . . . . . . . . . . . . . . . . . 19 Figure11Transceiver Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure12Equalizer Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure13Receive Signal Oversampling on U PN Interface . . . . . . . . . . . . . . . . . 22 Figure14Frame Structure at Reference Points S and T (ITU-T I.430). . . . . . . . 23 Figure15S/T Interface Line Code (without Code Violation) . . . . . . . . . . . . . . . . 24 Figure16Receiver Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure17Clock Recovery in LT-T Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure18LT-T Reference Clock Channel Selection for Cascaded VIPs. . . . . . . 28 Figure19Receive Signal Oversampling in S/T Receiver . . . . . . . . . . . . . . . . . . 29 Figure20Overview of IOM-2000 Interface Structure (Example with One VIP). . 30 Figure21IOM-2000 Data Sequence (1VIP with 8 Channels) . . . . . . . . . . . . . . 32 Figure22IOM-2000 Data Order (3VIPs with 24 Channels) . . . . . . . . . . . . . . . . 33 Figure23Recommended Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure24Input/Output Wave Form for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure25IOM-2000 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure26JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure271:1 Transformer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure28External Transceiver Circuitry of the VIP in U PN Mode . . . . . . . . . . . . 47 Figure29Overview of External Circuitry of the VIP in S/T Mode . . . . . . . . . . . . 47 Figure30External S/T Transmitter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure31External S/T Receiver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure32Wiring Configurations in User Premises (LT-S Mode). . . . . . . . . . . . . 49 Figure33Internal and External Loop-Back Modes . . . . . . . . . . . . . . . . . . . . . . . 50

List of Tables Page Table1VIP Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table2PEB 20590: U PN and S/T Line Interface . . . . . . . . . . . . . . . . . . . . . . . 11 Table3PEB 20591: U PN and S/T Line Interface . . . . . . . . . . . . . . . . . . . . . . . 12 Table4IOM-2000 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table5Clock Signals and Dedicated Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table6Power Supply and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table7JTAG Boundary Scan Test Interface (IEEE 1149.1) . . . . . . . . . . . . . . 15 Table8Control Bits in S/T Mode on DR Line. . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table9Control Bits in S/T Mode on DX Line. . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table10TAP Controller Instruction Codes Overview . . . . . . . . . . . . . . . . . . . . 34 Table11DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table12I/O Capacitances (except line interfaces and clocks) . . . . . . . . . . . . . 41 Table13Recommended Crystal Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table14IOM-2000 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table15JTAG Boundary Scan Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . 45

Preface

This document provides reference information on VIP1) (Versatile ISDN Port).

Organization of this Document

This Data Sheet is divided into 9 chapters. It is organized as follows:

?Chapter1, Introduction

Gives a general description of the VIP, lists the key features, and presents some typical applications.

?Chapter2, Pin Description

Lists pin locations with associated signals, categorizes signals according to function, and describes signals.

?Chapter3, Interface Description

Describes the VIP external interfaces.

?Chapter4, Operational Description

Describes the VIP operations reset, initialization, analog test loops and the monitoring of illegal code violations.

?Chapter5, Electrical Characteristics

Contains the DC and AC specification and timing diagrams.

?Chapter6, Application Hints

Provides information on external line interface circuitry in U PN and S/T mode, such as transformers and line protection.

?Chapter7, Package Outlines

?Chapter8, Glossary

?Chapter9, Index

1)Throughout this document the name VIP will be used to refer to both chip versions PEB 20590 and PEB 20591.

PRELIMINARY

Your Comments

We welcome your comments on this document. We are continuously trying to improve our documentation. Please send your remarks and suggestions by e-mail to

sc.docu_comments@https://www.360docs.net/doc/c217316946.html,

Please provide in the subject of your e-mail:

device name (VIP), device number (PEB 20590), device version (Version 2.1),

and in the body of your e-mail:

document type (Data Sheet), issue date (2001-03-01) and document revision number (DS4).

Related Documentation

?Data Sheet for DELIC Version2.3 or higher (PEB20570, PEB20571)

1Introduction

This chapter gives a general overview of the VIP including a top-level block diagram and the logic symbol diagram, it lists the key features, and presents some typical applications.

1.1Overview

VIP (Versatile ISDN Port) is a highly-integrated multiple layer-1 transceiver IC connecting to

?U PN subscriber line interfaces (2-wire) and

?S/T subscriber or trunk line interfaces (4-wire).

VIP integrates the complete analog line interface circuitry as well as the transceiver logic required for eight full-duplex channels.

Typical VIP applications include PBX line cards (U

, S/T or mixed), and small PBXs.

PN

VIP must be operated in combination with DELIC1), which is required for configuration and control/activation of VIP’s layer-1 transceivers. The communication path between the DELIC and the VIP is the serial IOM-2000 interface with a data rate of up to 12.288 Mbit/s. DELIC also processes the signaling information of each VIP channel by providing a dedicated HDLC controller per subscriber. For more information on DELIC and the IOM-2000 interface, please refer to the DELIC-LC/-PB Data Sheet.

1)Infineon Technologies DELIC: DSP Embedded Line and Port Interface Controller. The DELIC is available in

two versions: PEB 20570 and PEB 20571.

The VIP is available in two different versions, which differ in the possible interface combinations:

Table1VIP Product Family

Device Available Interfaces

VIP PEB 20590Four channels are programmable to either S/T or U PN mode, and

the other four channels can be operated in U PN mode only.

?

Maximum Number of U PN and S/T channels

U PN876543210

S/T012344444

VIP-8 PEB 20591All eight channels are programmable to either S/T or U PN mode.

?

Maximum Number of U PN and S/T channels

U PN876543210

S/T012345678

Figure1Top-Level Block Diagram of the VIP

Versatile ISDN Port VIP, VIP-8

PEB 20590PEB 20591

Version 2.1CMOS

Type

Package PEB 20590, PEB 20591

P-MQFP-80-1

PRELIMINARY

1.2

VIP Key Features

VIP is a universal ISDN transceiver IC for different interface modes (S/T or U PN ).

?Eight 2B+D line interfaces with full duplex transceivers

–S/T interfaces at 192 kbit/s with line transceivers according to ITU-T I.430, ETSI 300.012 and ANSI T1.605

–U PN interfaces at 384 kbit/s with line transceivers according to ZVEI standard –Receive timing recovery

–Conversion between pseudo-ternary and binary codes

–Conversion between U PN or S/T frames and IOM-2000 frame structures –Execution of test loops

–Frame alignment in trunk applications with maximum wander correction of ± 25μs –U PN interface compatible to OCTAT-P (PEB 2096)1)–S/T interface compatible to QUAT-S (PEB 2084)2)

?

IOM-2000 interface to DELIC supporting up to three VIPs (24 channels)–Transceiver initialization and configuration –Control of layer-1 activation/deactivation

–Exchange of command and status information

?Signaling control for all VIP channels by dedicated HDLC controllers in DELIC ?Single 3.3 V power supply

?

JTAG IEEE1149.1-compliant test interface with dedicated reset input

Note:U PN refers to a version of the U P0 interface (meeting the ZVEI standard) with a

reduced loop length of up to 1.3 km, depending on the type of cable.

1)Infineon Technologies OCTAT-P (PEB 2096): Octal Transceiver for U PN -Interfaces.2)

Infineon Technologies QUAT-S (PEB 2084): Quadruple Transceiver for S/T-Interface.

1.3Logic Symbol Diagrams

Figure2Logic Symbol PEB 20590 (72 of 80 Pins used)

Figure3Logic Symbol PEB 20591

1.4Typical Applications

Typical VIP applications are PBX line cards (U PN, S/T or mixed), and small PBXs.

The following figures illustrate sample configurations in which the VIP shows its flexibility.

Figure4VIP in Mixed S/T and U PN Line Cards (e.g. 8 S/T and 16 U PN)

Figure5VIP in a Small PBX Solution

Figure6DELIC-PB and VIP in a PC Card for 8/16 S/T Interfaces

2Pin Description

The VIP is available in an 80-pin Plastic Metric Quad Flat Package (P-MQFP-80-1). This chapter presents a simple layout of the 80-pin MQFP package with pin and signal callouts and a table of signal definitions.

2.1Pin Configuration

Figure7Pin Diagram, PEB 20590

Figure8Pin Diagram, PEB 20591

2.2Pin Descriptions

Table2PEB 20590: U PN and S/T Line Interface

Pin No.Symbol In (I)

Out(O)

During

Reset

Function

25 26 39 40 62 61 76 75SR1a/LI1a

SR1b/LI1b

SR3a/LI3a

SR3b/LI3b

SR5a/LI5a

SR5b/LI5b

SR7a/LI7a

SR7b/LI7b

I / I/O I S/T Receive Channel 1, 3, 5, 7/

U PN Transmit/Receive Channel 1, 3, 5, 7

12 13 28 27 48 47 73 74LI0a

LI0b

LI2a

LI2b

LI4a

LI4b

LI6a

LI6b

I/O I U PN Transmit/Receive Channel 0, 2, 4, 6

21 22 35 36 66 65 80 79SX1a

SX1b

SX3a

SX3b

SX5a

SX5b

SX7a

SX7b

O O S/T Transmit Channel 1, 3, 5, 7

8, 9,

31,

32,

51,

52,

69,

70

n.c.--n ot c onnected

Table3PEB 20591: U PN and S/T Line Interface

Pin No.Symbol In (I)

Out(O)

During

Reset

Function

12 13 25 26 27 28 39 40 48 47 62 61 73 74 76 75SR0a/LI0a

SR0b/LI0b

SR1a/LI1a

SR1b/LI1b

SR2a/LI2a

SR2b/LI2b

SR3a/LI3a

SR3b/LI3b

SR4a/LI4a

SR4b/LI4b

SR5a/LI5a

SR5b/LI5b

SR6a/LI6a

SR6b/LI6b

SR7a/LI7a

SR7b/LI7b

I / I/O I S/T Receive Channel /

U PN Transmit/Receive Channel

8 9 21 22 32 31 35 36 52 51 66 65 69 70 80 79SX0a

SX0b

SX1a

SX1b

SX2a

SX2b

SX3a

SX3b

SX4a

SX4b

SX5a

SX5b

SX6a

SX6b

SX7a

SX7b

O O S/T Transmit Channel