中科院_段成华_专用集成电路设计_作业 2

Assignment 2

1. (7.10)Implement a NAND gate model using the IEEE nine-valued system.

For the RS flip-flop shown in Figure 7.60, assume that both gate outputs are initially U, and that the two inputs R——and S——are initially 0 and switch to 1 simultaneously. Simulate the circuit at logic gate level when:

a.Both gates have identical delays.

b.The two gates have different delays. Compare your results.

Y

Y’

Figure 7.60 R-S flip-flop

------------------------------------------------------------------------------------------------------- ----------------------------------------RS触发器的门级模型----------------------------------- ------------------------------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity RS is

port ( NS,NR: in std_logic;

Y,NY : out std_logic);

end entity RS;

architecture rtl of RS is

component nand0 is

port (a,b:in std_logic;

c:out std_logic);

end component;

signal z1,z2:std_logic;

begin

NY<=z2;

Y<=z1;

u1:nand0 port map(NS,z2,z1);

u2:nand0 port map(NR,z1,z2);

end architecture rtl;

------------------------------------------------------------------------------------------------------- ----------------------------------RS触发器的门级模型测试激励----------------------------- ------------------------------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity RS_TB is

end entity RS_TB;

architecture RTL of RS_TB is

component RS is

port ( NS,NR: in std_logic;

Y,NY: out std_logic);

end component;

signal NY :std_logic:='1';

signal Y :std_logic:='1';

signal NS :std_logic:='0';

signal NR :std_logic:='0';

begin

DUT:RS port map(

NS => NS,

NR => NR,

y => y,

NY => NY);

process

begin

NS <= '0';

NR <= '0';

wait for 0.1 us;

NS <= '1';

NR <= '1';

wait for 0.1 us;

end process;

end architecture RTL;

------------------------------------------------------------------------------------------------------- --------------共同延迟的RS电路门级仿真、此次采用的是VCS 2009.12--------------- -------------------------------------------------------------------------------------------------------

一、建立和设置环境变量

二、分析

三、Elaboration

四、仿真

1、调用DVE

2、查看仿真波形

3、根据DVE检查波形，分析功能

上图是VCS图形界面的DVE工具显示的波形图，从上面可以得到一下几个结论：

1、初始状态输出端为‘U’，输入端均为‘0’；

2、在1ns的反应延迟之后，输出端根据当前状态被置为‘1’；

3、在100ns时，输入端同时置‘1’，此时输出端出现震荡状态。

4、当200ns时，输入端回到‘0’状态，输出端稳定为‘0’。

------------------------------------------------------------------------------------------------------- -------------------------------不同延迟的RS电路门级仿真---------------------------------- ------------------------------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity RS is

port ( NS,NR: in std_logic;

Y,NY : out std_logic);

end entity RS;

architecture rtl of RS is

component nand0 is

port(a,b:in std_logic;

c:out std_logic);

end component;

signal z1,z2:std_logic;

component nand1 is

port(aa,bb:in std_logic;

cc:out std_logic);

end component;

begin

U1:nand0 port map(NS,z2,z1);

U2:nand1 port map(NR,z1,z2);

Y <=z1;

NY<=z2;

end architecture rtl;

library ieee;

use ieee.std_logic_1164.all;

entity nand0 is

port(a,b:in std_logic;

c:out std_logic);

end nand0;

architecture Behavioral of nand0 is

begin

c<=not(a and b) after 1 ns;-- delay 1ns end Behavioral;

library ieee;

use ieee.std_logic_1164.all;

entity nand1 is

port(aa,bb:in std_logic;

cc:out std_logic);

end nand1;

architecture Behavioral of nand1 is

begin

cc<=not(aa and bb) after 3 ns;-- delay 3ns end behavioral;

------------------------------------------------------------------------------------------------------- -------------------------用于测试的RS电路门级仿真testbench---------------------------- ------------------------------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity RS_TB is

end entity RS_TB;

architecture RTL of RS_TB is

component RS is

port (NS,NR: in std_logic;

Y,NY: out std_logic);

end component;

signal NY:std_logic;

signal Y :std_logic;

signal NS:std_logic:='0';

signal NR:std_logic:='0';

begin

DUT:RS port map(

NS => NS,

NR => NR,

y => y,

NY => NY);

process

begin

NS <= '0';

NR <= '0';

wait for 0.1 us;

NS <= '1';

NR <= '1';

wait for 0.1 us;

NS <= '0';

NR <= '0';

wait for 0.1 us;

end process;

end architecture RTL;

DVE中观测到的测试波形

通过分析可以得到下面几个结论：

1、默认初始的是‘U’和‘0’状态

2、在100ns时，两个输入信号翻转为‘1’，但由于延迟的作用，Y端并没有立刻

跳变。

3、由于设置的NS和Y的延迟比较小，当Y变为‘0’状态以后将会对NY的输出

产生影响。出现一直处于高电平的状态。

2. Simulate this circuit (Figure 7.60) at transistor-level.

利用synopsys的Design Compiler综合工具，在没有映射的逻辑电路图，可以发现电路图如下，和7.6图一样。

---利用真值表，生成RS的RTL级描述

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity RS is

port ( NS,NR: in std_logic;

Y,NY : out std_logic);

end entity RS;

architecture rtl of RS is

signal d:std_logic_vector (1 downto 0);

signal q0,q1:std_logic;

begin

d<=NR&NS;

y<=q0;

NY<=q1;

process( d )

begin

case d is

when "00" => q0<='1'; q1<='1';

when "01" => q0<='1'; q1<='0';

when "10" => q0<='0'; q1<='1';

when "11" => q0<=q0 ; q1<=q1 ;

when others => null;

end case;

end process;

end architecture rtl;

--------------------------------------RTL级的测试激励----------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity RS_tb is

end entity RS_tb;

architecture rtl_tb of RS_tb is

component RS is

port (NS,NR: in std_logic;

Y,NY : out std_logic);

end component;

signal NS,NR:std_logic:='0';

signal Y,NY :std_logic;

begin

U1: RS port map(NS,NR,Y,NY);

Process

Begin

NS <= '0';

NR <= '0';

Wait for 0.02 us;

NS <= '1';

NR <= '1';

Wait for 0.02 us;

End process;

End rtl_tb;

分析：当NS和NR为‘0’时，出现非定义的Y=NY=1的状态，当同时回到高电平时，锁存器的状态难以确定。