SW2103_Datasheet_v1.1_release

Mode: SW2103 (V1.1) https://www.360docs.net/doc/d813218508.html,

第 1 页共 12 页 SW2103

Datasheet

Designed for Type-C Logic Detect and Control

Version 1.1

珠海智融科技有限公司

ZHUHAI ISMARTWARE TECHNOLOGY CO., LTD.

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Table of Content

1. General Description (4)

2. Applications (4)

3. Features (4)

4. Schematic Circuit Diagram (5)

5. Application Function Description (5)

6. Pin Configuration and Function (6)

6.1 Pin Configuration (6)

6.2 Pin Descriptions (6)

7. Absolute Maximum Ratings (7)

8. SWB (Single Wire Bus) (8)

8.1 Write Timing (8)

8.2 Read Timing (9)

9. Register List (10)

9.1 REG 00: Mode Configure (10)

9.2 REG 01:CTRL Register (10)

9.3 REG 02: IRQ Indication (11)

10. Mechanical and Packaging (11)

10.1 Package Summary (11)

10.2 Package Outline and Dimensions (12)

1. General Description

SW2103 is a USB Type-C logic detect and control IC, equipment with BC1.2 DCP support. It could realize the function of enabling the traditional USB device to support the transformation of Type-C interface. SW2103 uses CC pins to determine port attach/detach status and orientation, role type and current mode, provides VBUS enable signal output. It provides PMODE pin for current mode configure, swap key for role which makes it convenient in power bank applications. It also provides single wire bus which make it easy to dynamically configure role and current mode for phone and pads. It supports Battery Charging Spec BC1.2 for DCP. It is compatible with Apple mode and Samsung mode.

T he SW2103 have an alternate configuration as a DFP or UFP according to the Type-C specifications. The CC logic block monitors the CC1 and CC2 pins for pullup or pulldown resistances to determine when a USB port have been attached, the orientation of the cable, and the role detected. The CC logic detects the Type-C current mode as standard, 1.5A or 3.0A depending on the role detected. VBUS detection is implemented to determine a successful attach in UFP and DRP.

2. Applications

?Power Bank

?Power Supply Adapter

?Car Charger

?Mobile phone and Pads

3. Features

?Support USB Type-C specification 1.1

?Support Strong-DRP/DRP/DFP/UFP role

?Support Type-C standard, 1.5A and 3A mode

?Support VBUS enable signal output, can be as USB ID control signal

?Provide key swap for Type-C role

?Provide VCONN power

?Support Dead Battery

?Support BC1.2 DCP

?Support Apple & Samsung device

?Support YD/T 1591-2009 Chinese telecommunication industry standard

?Single wire bus (rate < 5kbps)

?Under-V oltage lock out protection

?Available in QFN16 (3×3mm) package

?Operating voltage: 2.7V~6V(without DP/DM)

4. Schematic Circuit Diagram

SW2103

VBUS

VCC

GND

IRQ

CC2_TACH

CC1CC2

Vbus_En

SWB Type-C receptacle

50k

1uF

GND

VBUS

CC2

CC1GPIO

IRQ

Analog Switch

TX+TX-RX+RX-TX1+TX1-RX1+RX1-TX2+TX2-RX2+RX2-Micro-B receptacle D+D-GND

VBUS ID DP DP DM DM VBUS DM DP ID GND

Vbat

VBUS SEL

SEL SEL 10k

10k

2.2k

Phone&Pad Application Diagram

5. Application Function Description SW2103 support DFP/StrDRP/DRP/UFP role.

When it attached with Type-C device successfully, the

VBUS_EN and CC2_TACH will change according to role and orientation.

SW2103_Role_Function

Application Scene (SW2103 VS device)

Detach

Attached

SW2103 role

device role SW2103 role device role Adapter VS Adapter

DFP

(VBUS_EN=LOW CC2_TACH=LOW)

DFP

detached

Adpater VS Powerbank /phone/u-disk

StrDRP or DRP

or UFP

DFP

(VBUS_EN=HIGH

CC2_TACH=HIGH)

UFP

Powerbank VS Adapter

StrDRP

(VBUS_EN=LOW CC2_TACH=LOW)

DFP

UFP

(VBUS_EN=LOW CC2_TACH=HIGH) DFP

Powerbank VS Powerbank

StrDRP rand role

(CC2_TACH=HIGH)

rand role

Powerbank VS phone /u-disk

DRP or UFP

DFP

(VBUS_EN=HIGH CC2_TACH=HIGH) UFP

phone VS adapter /powerbank DRP

(VBUS_EN=LOW CC2_TACH=LOW)

DFP or StrDRP

UFP

(VBUS_EN=LOW CC2_TACH=HIGH)

DFP

phone VS phone

DRP rand

rand

phone VS u-disk UFP

DFP

(VBUS_EN=HIGH CC2_TACH=HIGH) UFP

u-disk VS adapter /powerbank/phone

UFP

(VBUS_EN=LOW

CC2_TACH=LOW)

DFP or StrDRP

or DRP

UFP

(VBUS_EN=LOW CC2_TACH=HIGH)

DFP

A: in this table, the cable orientation attached with SW2103 is CC2.

6. Pin Configuration and Function

6.1 Pin Configuration

QFN16 Top View

1211109

76513

16GND PAD

IRQ PMODE VBUS_EN

SWB

N C

V B U S

N C

V C C

CC2_TACH

CC2CC1DP

N C D M D _S E L

N C

6.2 Pin Descriptions

Item Name Type Function Description

1 IRQ O Open drain output, Interrupt output to AP 2

PMODE

Power level mode setting

Float : standard

GND : 1.5A

VCC : 3.0 A

3 VBUS_EN O Push-pull output, Control signal of VBUS

4 SWB IO Open drain input-output, Single wire bus

5 NC NC /

6 VBUS I Type-C VBUS input

7 VCC PI Power supply

8 NC NC /

9 CC2_TACH O Open drain output, Indication of CC2 tach, provide Type-C cable orientation identification

10 CC2 IO Type-C configure channel CC2

11 CC1 IO Type-C configure channel CC1

12 DP IO BC1.2 Host DP

13 NC NC /

14 DM IO BC1.2 Host DM

15 D_SEL I Digital input, Type-C role swap key. More than 3 times low level (>32ms) in 3 second will enable role swap.

16 NC NC /

7. Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise specified)

Parameters Symbol MIN Max Unit Input Supply V oltage VCC -0.3 10 V Type-C VBUS Supply Voltage VBUS -0.3 20 V Type-C interface Signal CC1,CC2 -0.3 10 V

Storage Temperature Range -40 +150 ℃Electronic Static Discharge(HBM) ESD 4 KV

【Notice】Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability

Recommended Operation Conditions

Parameters Symbol MIN Typical Max Unit Input supply Voltage VCC 2.7 6 V Type-C VBUS Supply voltage VBUS 3.3 5 6 V Operation Temperature -40 125 ℃

8. SWB (Single Wire Bus)

Within the 32 host clock cycle and after read/write command is sent out, if the host cannot receive the effective response, the device is regarded as read/write failure and should resend the command.

SWB adopts high byte order for sending data. During the first phase, the 7th represents for parity check code. The write command concludes the register address and data written which contains 16 bits parity check code. The read command concludes the register address which contains 8 bits parity check code. Similarity, responding to write command in the device and during the first phase, the 7th represents for the address received by the device and parity check code of the data, and the 8th always be the 0. Responding to read command in the device and during the first phase, the 7th represents for the parity check code of the received address, and the 8th presents for the read data of a total of 8 bits parity check code results.

During the first phase, the 9th and the 4th in register and data are generated from the logical invert by the one bit before the adjacent.

8.1 Write Timing

Example: Register address is D8h, Write Data is 75h

sync code 010b

device

address

10b

first phase

second phase register address D8h

write data 75h

write

third phase

parity

check

Request

from

host

antilogic

phase

antilogic

phase

Host Write Timing Diagram

Goodparity

sync code 010b

device

address

10b

parity

check

good

parity

check

from

device

antilogic

phase

first phase Slave Respond to the Write Timing Diagram

8.2 Read Timing

Example: Register address is D8h, read data is 75h

Request

sync code 010b

device

address

10b read

parity

check

from

host

first phase

antilogic

phase

second phase register address D8h

antilogic

phase

Host Reading Timing Diagram

Goodparity

second phase

sync code 010b

device

address

10b

Good

parity

check

from

device

first phase

parity

check

antilogic

phase

read data 75h

antilogic

phase

Slave Respond to the Read Timing Diagram

9. Register List

9.1 REG 00: Mode Configure

Default: 0x00H

Bit Description R/W Default

7-6 BC1.2 default mode

0: apple divider 1 mode;

1: apple divider 2 mode;

x: reserved

The default value is determined by internal memory status.

R/W -

5 IRQ enable

0: IRQ disable

1: IRQ enable

R/W 0x0

4 AP mode only for power level

0: device mode

1: AP mode

In device mode, the power level is determined by PMODE pin.

In AP mode, the power level is determined by register configuration.

R/W 0x0

3-2 CC default role mode

0: UFP;

1: DFP;

2: DRP;

3: strong DRP;

The default value is determined by internal memory status.

R/W -

1-0 UFP power level info

0: standard power

1: 1.5A

2: 3.0A

3: reserved

R -

9.2 REG 01:CTRL Register

Default: 0x00H

Bit Description R/W Default 7-6 / / /

5-4 CC current role under DRP mode

0:untach;

1: UFP;

2: DFP;

3: reserved

R -

3-2 DFP configure power level

0: standard power

1: 1.5A

2: 3.0A

R/W 0x0

3: reserved

1 EMARKER exist

0: not exist

1: exist

If emarker exist, host can get this status through read this bit.

R -

0 Role swap indication

0: nothing

1: role swap enable

In AP mode writing 1 to this bit to enable role swap; in device mode

it indicates role swap enabled when this bit is set to 1.

R/W -

9.3 REG 02: IRQ Indication

Default: 0x00H

Bit Description R/W Default

7-5 IRQ indication

0: dfp tach

1: ufp tach

2: dfp detach

3: ufp detach

4: ufp pwr level change

R -

4-1 / / /

0 IRQ pending bit

0: nothing

1: IRQ is pending

This bit is cleared by writing 1 to this bit.

R/W 0x0

10. Mechanical and Packaging

The following pages include mechanical packaging information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document.

10.1 Package Summary

10.2 Package Outline and Dimensions