KFG1216D2A-DID5中文资料

OneNAND TM SpecificationDensity Part No.V CC(core & IO)Temperature PKG512Mb KFG1216Q2A 1.8V(1.7V~1.95V)Extended63FBGA(LF)/63FBGA KFG1216D2A 2.65V(2.4V~2.9V)Extended63FBGA(LF)/63FBGAKFG1216U2A 3.3V(2.7V~3.6V)Industrial63FBGA(LF)/63FBGAVersion: Ver. 1.0Date: May 17th, 20051.0 INTRODUCTIONThis specification contains information about the Samsung Electronics Company OneNAND™‚ Flash memory product family. Section 1.0 includes a general overview, revision history, and product ordering information.Section 2.0 describes the OneNAND device. Section 3.0 provides information about device operation. Electrical specifications and timing waveforms are in Sections 4.0 though 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the OneNAND. Package dimensions are found in Section 8.0INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALLINFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similarapplications where Product failure could result in loss of life or personal or physical harm, or any military ordefense application, or any governmental procurement to which special terms or provisions may apply.OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their rightful owners.Copyright © 2005, Samsung Electronics Company, LtdDocument Title OneNANDRevision HistoryRevision No.0.00.10.20.30.4RemarkPreliminaryPreliminaryPreliminaryPreliminaryPreliminaryDraft DateNov. 4, 2004Dec. 7, 2004Dec. 24, 2004Jan. 13, 2005Feb. 25, 2005HistoryInitial issue.1. Corrected Errata2. Revised cache read flow chart3. Revised standby current4. Revised spare area description5. Added CE don’t care state for Asynch Write, Load, Program, and BlockErase timing diagram1. Added Copy Back Operation with Random Data Input2. Changed tBA from 11ns to 11.5ns3. Pended Active Erase Current1. Corrected the errata2. Revised typical value of ISB from 50uA to 10uA3. Revised maximum value of ISB from 100uA to 50uA4. Revised maximum value of tCE, tAA and tACC from 70ns to 76ns5. Revised Vcc-IO description6. Revised Spare Area description7. Added extra information on Controller Status Register8. Added commands related to Interrupt Status Register bits9. Revised Write Protection Status on Chapter 3.4.310. Revised Copy-Back Program Operation description11. Added extra information on Multi-Block Erase Operation12. Disabled FBA restriction in OTP operation13. Revised Cache Read Flow Chart14. Revised Reset Parameter descriptions15. Added RDY information on Warm Reset Timing diagram16. Added information on Data Protection Timing During Power Down17. Revised Interrupt pin rise and falling slope graph18. Added restriction on address register setting on Dual Operations19. Added restriction on address register setting on Cache Read Operation1. Corrected the errata2. Updated DC parameters to RMS values3. Added Speed Information on Product Number4. Revised tOEZ description5. Revised OTP register setting restriction6. Added Boot Sequence Infrormation on Technical Notes7. Added Cint Information1.1 Revision HistoryRevision HistoryRevision No.1.0RemarkFinalDraft DateMay. 17, 2005History1. Corrected the errata2. Added Data Protection flow chart.3. Removed Cache Read Operation.4. Added additional information on command register.5. Revised Interrupt status register information.6. Added INT pin schematic.7. Changed tPGM1 to 205 from 320us, tPGM2 to 220 from 350us.8. Revised AC/DC parameters9. Revised ECC Bypass Description.10. Revised Reset Parameters and Timing Diagrams.Samsung offers a variety of Flash solutions including NAND Flash, OneNAND™ and NOR Flash. Samsung offers Flash products both component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia.To determine which Samsung Flash product solution is best for your application, refer the product selector chart.Application RequiresSamsung Flash ProductsNAND OneNAND NORFast Random Read•Fast Sequential Read••Fast Write/Program••Multi Block Erase• (Max 64 Blocks)•Erase Suspend/Resume••Copyback• (EDC)• (ECC)Lock/Unlock/Lock-Tight••ECC External (Hardware/Software)Internal X Scalability••1.3 Ordering Information1.2 Flash Product Type SelectorK F G 12 1 6 Q 2 A - x x B 5SamsungOneNAND MemoryDevice TypeG : Single ChipDensity 12: 512Mb Operating Temperature RangeE = Extended Temp. (-30 °C to 85 °C) I = Industrial Temp. (-40 °C to 85 °C) Page Architecture2 : 2KB PageVersion2nd GenerationProduct Line desinatorB : Include Bad BlockD : Daisy SampleOperating Voltage Range Q : 1.8V(1.7 V to 1.95V)D : 2.65V(2.4V to 2.9V)U : 3.3V(2.7 V to 3.6V)PackageD : FBGA(Lead Free) F : FBGA(Leaded)Organizationx16 Organization Speed5 : 54MHz6 : 66MHz1.4 Architectural BenefitsOneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory array.The chip integrates system features including:• A BootRAM and bootloader• Two independent bi-directional 2KB DataRAM buffers• A High-Speed x16 Host Interface• On-chip Error Correction• On-chip NOR interface controllerThis on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that would otherwise have to use more NOR components.OneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the synchronous read performance of NOR. The NOR Flash host interface makes OneNAND an ideal solution for applications like G3 Smart Phones, Camera Phones, and mobile applications that have large, advanced multimedia applications and operating systems, but lack a NAND controller.When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-perfor-mance, small footprint solution.The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.Device Architecture• Design Technology:• Supply Voltage: • Host Interface: • 5KB Internal BufferRAM: • SLC NAND Array:Device Performance• Host Interface Type:- Up to 54MHz clock frequency- Linear Burst 4-, 8-, 16, 32-words with wrap around - Continuous 1K word Sequential Burst• Programmable Burst Read Latency• Multiple Sector Read:• Multiple Reset Modes:• Multi Block Erase:• Low Power Dissipation:- Standby current : 10uA@1.8Vdevice,35uA@2.65V/3.3V device- Synchronous Burst Read current : 12mA@1.8Vdevice22mA@2.65V/3.3V device - Load current : 30mA@all device- Program current : 25mA@1.8v device28mA@2.65V/3.3V device - Erase current : 20mA@1.8V device23mA@2.65V/3.3V device - Multi Block Erase current : 20mA@1.8V device23mA@2.65V/3.3V deviceSystem Hardware• Voltage detector generating internal reset signal from Vcc • Hardware reset input (/RP)• Data Protection Modes• User-controlled One Time Programmable(OTP) area • Internal 2bit EDC / 1bit ECC• Internal Bootloader supports Booting Solution in system • Handshaking Feature • Detailed chip informationPackaging 90nm1.8V (1.7V ~ 1.95V),2.65V (2.4 ~ 2.9V),3.3V (2.7 ~3.6V)16 bit1KB BootRAM, 4KB DataRAM(2K+64)B Page Size, (128K+4K)B Block SizeSynchronous Burst Read Asynchronous Random Read - 76ns access time Asynchronous Random WriteLatency 3(up to 40MHz), 4, 5, 6, and 7Up to 4 sectors using Sector Count Register Cold/Warm/Hot/NAND Flash Resets up to 64 blocks Typical Power, - Write Protection for BootRAM - Write Protection for NAND Flash Array - Write Protection during power-up - Write Protection during power-down- INT pin indicates Ready / Busy- Polling the interrupt register status bit - by ID register63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA1.5 Product Features1.6 General OverviewOneNAND™‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes control logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 4KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed of ~76ns.The device operates up to a maximum host-driven clock frequency of 54MHz for synchronous reads at Vcc(or Vccq. Refer to chapter 4.2)with minimum 4-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are deter-mined by programmable read latency.OneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register. The device includes one block-sized OTP (One Time Programmable) area that can be used to increase system security or to provide identification capabilities.2.0 DEVICE DESCRIPTION2.1Detailed Product DescriptionThe OneNAND is an advanced generation, high-performance NAND-based Flash memory.It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for the Flash array, and a one-time-programmable block.The combination of these memory areas enable high-speed pipelining of reads from host, BufferRAM, Page Buffer, and NAND Flash Array memory.Clock speeds up to 54MHz with a x16 wide I/O yields a 68MByte/second bandwidth.The OneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup from the NAND Array without the need for off-chip boot device.One block of the NAND Array is set aside as an OTP memory area. This area, available to the user, can be configured and locked with secured user information.On-chip controller interfaces enable the device to operate in systems without NAND Host controllers.B (capital letter)Byte, 8bitsW (capital letter)Word, 16bitsb (lower-case letter)BitECC Error Correction CodeCalculated ECC ECC that has been calculated during a load or program accessWritten ECC ECC that has been stored as data in the NAND Flash array or in the BufferRAM BufferRAM On-chip internal buffer consisting of BootRAM and DataRAMBootRAM A 1KB portion of the BufferRAM reserved for Boot Code bufferingDataRAM A 4KB portion of the BufferRAM reserved for Data bufferingSector Part of a Page ; 512B for the main data area and 16B for the spare area.It is also the minimum Load/Program/Copy-Back Program unitduring a 1~4 sector operation is available.Data unit Possible data unit to be read from memory to BufferRAM or to be programmed to memory. - 528B of which 512B is in main area and 16B in spare area- 1056B of which 1024B is in main area and 32B in spare area- 1584B of which 1536B is in main area and 48B in spare area- 2112B of which 2048B is in main area and 64B in spare area2.2 DefinitionsNC NC NC NCINT A0A1NC A10A6NC NC NCWE RP DQ14V SS V SS DQ13DQ12DQ8DQ1OE DQ9V CC DQ7DQ4DQ11DQ10DQ3V CC DQ15A12DQ0DQ5DQ6CE DQ2NC NC A9AVD A7A11A8A4A5A2A3NCNC NC NC NCNC NC NC NCCore IOCLK A15A13A14RDY (TOP VIEW, Balls Facing Down)63ball FBGA OneNAND Chip63ball, 9.5mm x 12mm x max 1.0mmt , 0.8mm ball pitch FBGA2.3 Pin ConfigurationNOTE:Do not leave power supply(Vcc-Core/Vcc-IO, V SS ) disconnected.Pin Name TypeNameand DescriptionHost InterfaceA15~A0IAddress Inputs- Inputs for addresses during read and write operation, which are for addressing BufferRAM & Register.DQ15~DQ0I/OData Inputs/Outputs- Inputs data during program and commands during all operations, outputs data for memory array/ register read cycles.Data pins float to high-impedance when the chip is deselected or outputs are disabled.INT OInterruptNotifies the Host when a command is completed. It is open drain output with internal resistor(~50kohms). After power-up, it is at hi-z condition. Once IOBE is set to 1,it does not float to hi-z condition even when the chip is deselected or when outputs are disabled.RDY OReadyIndicates data valid in synchronous read modes and is activated while CE is low CLK IClockCLK synchronizes the device to the system bus frequency in synchronous read mode.The first rising edge of CLK in conjunction with AVD low latches address input.WE IWrite EnableWE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge AVD IAddress Valid DetectIndicates valid address presence on address inputs. During asynchronous read operation, all addresses are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one clock cycle.> Low : for asynchronous mode, indicates valid address ;for burst mode,causes starting address to be latched on rising edge on CLK> High : device ignores address inputsRP IReset PinWhen low, RP resets internal operation of OneNAND. RP status is don’t care during power-up and bootloading.CE IChip EnableCE-low activates internal control logic, and CE-high deselects the device, places it in standby state,and places DQ in Hi-ZOE IOutput EnableOE-low enables the device’s output data buffers during a read cycle.Power Supply V CC -Core / Vcc Power for MuxOneNAND CoreThis is the power supply for OneNAND Core.V CC -IO / Vccq Power for MuxOneNAND I/OThis is the power supply for OneNAND I/OVcc-IO / Vccq is internally separated from Vcc-Core / Vcc. V SSGround for OneNANDetc.DNU Do Not UseLeave it disconnected. These pins are used for testing.NCNo ConnectionLead is not internally connected.2.4 Pin DescriptionBootRAMHost InterfaceCLK CEOE WE RP AVDStateMachine BootloaderInternal Registers(Address/Command/Configuration/Status Registers)Error Correction LogicINT DataRAM0BufferRAM NAND FlashArrayOTP (One Block)RDYA15~A0DQ15~DQ02.6 Memory Array OrganizationThe OneNAND architecture integrates several memory areas on a single chip.2.6.1 Internal (NAND Array) Memory OrganizationThe on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and code. The internal memory is divided into a main area and a spare area.Main AreaThe main area is the primary memory array. This main area is divided into Blocks of 64 Pages. Within a Block, each Page is 2KB and is comprised of 4 Sectors. Within a Page, each Sector is 512B and is comprised of 256 Words.Spare AreaThe spare area is used for invalid block information and ECC storage. Spare area of internal memory is associated with correspond-ing main area of internal memory. Within a Block, each Page has four 16B Sectors of spare area. Each spare area Sector is 8 words.DataRAM12.5 Block DiagramThe on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering.The BootRAM is a 1KB buffer that receives Boot Code from the internal memory and makes it available to the host at start up. There are two independent 2KB bi-directional data buffers, DataRAM0 and DataRAM1. These dual buffers enable the host to execute simultaneous Read-While load, and Write-While-program operations after Boot Up. During Boot Up, the BootRam is used by the host to initialize the main memory, and deliver boot code from NAND Flash core to host.The external memory is divided into a main area and a spare area. Each buffer is the equivalent size of a Sector. The main area data is 512B. The spare area data is 16B.External Memory Array InformationArea BootRAM DataRAM0DataRAM1Total Size 1KB+32B2KB+64B2KB+64BNumber of Sectors 244SectorMain 512B 512B 512B Spare16B16B16BHostOTP BlockNand ArrayBoot code (1KB)BootRAM (1KB)DataRAM0 (2KB)DataRAM1 (2KB)External (BufferRAM)MemoryInternal (Nand Array)Memory2.6.2 External (BufferRAM) Memory OrganizationExternal Memory Array OrganizationBootRAM 0BootRAM 1BootRAMDataRAM 1_0DataRAM 1_1 DataRAM 1_2 DataRAM 1_3DataRAM1{Main area dataSpare area dataDataRAM 0_0DataRAM 0_1 DataRAM 0_2 DataRAM 0_3DataRAM0Sector: (512 + 16) Byte{(512B)(16B)The following tables are the memory maps for the OneNAND.2.7.1 Internal (NAND Array) Memory Organization The following tables show the Internal Memory address map in word order.Block Block Address Page and SectorAddressSize Block Block AddressPage and SectorAddressSizeBlock00000h0000h~00FFh128KB Block320020h0000h~00FFh128KB Block10001h0000h~00FFh128KB Block330021h0000h~00FFh128KB Block20002h0000h~00FFh128KB Block340022h0000h~00FFh128KB Block30003h0000h~00FFh128KB Block350023h0000h~00FFh128KB Block40004h0000h~00FFh128KB Block360024h0000h~00FFh128KB Block50005h0000h~00FFh128KB Block370025h0000h~00FFh128KB Block60006h0000h~00FFh128KB Block380026h0000h~00FFh128KB Block70007h0000h~00FFh128KB Block390027h0000h~00FFh128KB Block80008h0000h~00FFh128KB Block400028h0000h~00FFh128KB Block90009h0000h~00FFh128KB Block410029h0000h~00FFh128KB Block10000Ah0000h~00FFh128KB Block42002Ah0000h~00FFh128KB Block11000Bh0000h~00FFh128KB Block43002Bh0000h~00FFh128KB Block12000Ch0000h~00FFh128KB Block44002Ch0000h~00FFh128KB Block13000Dh0000h~00FFh128KB Block45002Dh0000h~00FFh128KB Block14000Eh0000h~00FFh128KB Block46002Eh0000h~00FFh128KB Block15000Fh0000h~00FFh128KB Block47002Fh0000h~00FFh128KB Block160010h0000h~00FFh128KB Block480030h0000h~00FFh128KB Block170011h0000h~00FFh128KB Block490031h0000h~00FFh128KB Block180012h0000h~00FFh128KB Block500032h0000h~00FFh128KB Block190013h0000h~00FFh128KB Block510033h0000h~00FFh128KB Block200014h0000h~00FFh128KB Block520034h0000h~00FFh128KB Block210015h0000h~00FFh128KB Block530035h0000h~00FFh128KB Block220016h0000h~00FFh128KB Block540036h0000h~00FFh128KB Block230017h0000h~00FFh128KB Block550037h0000h~00FFh128KB Block240018h0000h~00FFh128KB Block560038h0000h~00FFh128KB Block250019h0000h~00FFh128KB Block570039h0000h~00FFh128KB Block26001Ah0000h~00FFh128KB Block58003Ah0000h~00FFh128KB Block27001Bh0000h~00FFh128KB Block59003Bh0000h~00FFh128KB Block28001Ch0000h~00FFh128KB Block60003Ch0000h~00FFh128KB Block29001Dh0000h~00FFh128KB Block61003Dh0000h~00FFh128KB Block30001Eh0000h~00FFh128KB Block62003Eh0000h~00FFh128KB Block31001Fh0000h~00FFh128KB Block63003Fh0000h~00FFh128KB 2.7 Memory MapBlock Block Address Page and SectorAddressSize Block Block AddressPage and SectorAddressSizeBlock640040h0000h~00FFh128KB Block960060h0000h~00FFh128KB Block650041h0000h~00FFh128KB Block970061h0000h~00FFh128KB Block660042h0000h~00FFh128KB Block980062h0000h~00FFh128KB Block670043h0000h~00FFh128KB Block990063h0000h~00FFh128KB Block680044h0000h~00FFh128KB Block1000064h0000h~00FFh128KB Block690045h0000h~00FFh128KB Block1010065h0000h~00FFh128KB Block700046h0000h~00FFh128KB Block1020066h0000h~00FFh128KB Block710047h0000h~00FFh128KB Block1030067h0000h~00FFh128KB Block720048h0000h~00FFh128KB Block1040068h0000h~00FFh128KB Block730049h0000h~00FFh128KB Block1050069h0000h~00FFh128KB Block74004Ah0000h~00FFh128KB Block106006Ah0000h~00FFh128KB Block75004Bh0000h~00FFh128KB Block107006Bh0000h~00FFh128KB Block76004Ch0000h~00FFh128KB Block108006Ch0000h~00FFh128KB Block77004Dh0000h~00FFh128KB Block109006Dh0000h~00FFh128KB Block78004Eh0000h~00FFh128KB Block110006Eh0000h~00FFh128KB Block79004Fh0000h~00FFh128KB Block111006Fh0000h~00FFh128KB Block800050h0000h~00FFh128KB Block1120070h0000h~00FFh128KB Block810051h0000h~00FFh128KB Block1130071h0000h~00FFh128KB Block820052h0000h~00FFh128KB Block1140072h0000h~00FFh128KB Block830053h0000h~00FFh128KB Block1150073h0000h~00FFh128KB Block840054h0000h~00FFh128KB Block1160074h0000h~00FFh128KB Block850055h0000h~00FFh128KB Block1170075h0000h~00FFh128KB Block860056h0000h~00FFh128KB Block1180076h0000h~00FFh128KB Block870057h0000h~00FFh128KB Block1190077h0000h~00FFh128KB Block880058h0000h~00FFh128KB Block1200078h0000h~00FFh128KB Block890059h0000h~00FFh128KB Block1210079h0000h~00FFh128KB Block90005Ah0000h~00FFh128KB Block122007Ah0000h~00FFh128KB Block91005Bh0000h~00FFh128KB Block123007Bh0000h~00FFh128KB Block92005Ch0000h~00FFh128KB Block124007Ch0000h~00FFh128KB Block93005Dh0000h~00FFh128KB Block125007Dh0000h~00FFh128KB Block94005Eh0000h~00FFh128KB Block126007Eh0000h~00FFh128KB Block95005Fh0000h~00FFh128KB Block127007Fh0000h~00FFh128KBBlock Block Address Page and SectorAddressSize Block Block AddressPage and SectorAddressSizeBlock1280080h0000h~00FFh128KB Block16000A0h0000h~00FFh128KB Block1290081h0000h~00FFh128KB Block16100A1h0000h~00FFh128KB Block1300082h0000h~00FFh128KB Block16200A2h0000h~00FFh128KB Block1310083h0000h~00FFh128KB Block16300A3h0000h~00FFh128KB Block1320084h0000h~00FFh128KB Block16400A4h0000h~00FFh128KB Block1330085h0000h~00FFh128KB Block16500A5h0000h~00FFh128KB Block1340086h0000h~00FFh128KB Block16600A6h0000h~00FFh128KB Block1350087h0000h~00FFh128KB Block16700A7h0000h~00FFh128KB Block1360088h0000h~00FFh128KB Block16800A8h0000h~00FFh128KB Block1370089h0000h~00FFh128KB Block16900A9h0000h~00FFh128KB Block138008Ah0000h~00FFh128KB Block17000AAh0000h~00FFh128KB Block139008Bh0000h~00FFh128KB Block17100ABh0000h~00FFh128KB Block140008Ch0000h~00FFh128KB Block17200ACh0000h~00FFh128KB Block141008Dh0000h~00FFh128KB Block17300ADh0000h~00FFh128KB Block142008Eh0000h~00FFh128KB Block17400AEh0000h~00FFh128KB Block143008Fh0000h~00FFh128KB Block17500AFh0000h~00FFh128KB Block1440090h0000h~00FFh128KB Block17600B0h0000h~00FFh128KB Block1450091h0000h~00FFh128KB Block17700B1h0000h~00FFh128KB Block1460092h0000h~00FFh128KB Block17800B2h0000h~00FFh128KB Block1470093h0000h~00FFh128KB Block17900B3h0000h~00FFh128KB Block1480094h0000h~00FFh128KB Block18000B4h0000h~00FFh128KB Block1490095h0000h~00FFh128KB Block18100B5h0000h~00FFh128KB Block1500096h0000h~00FFh128KB Block18200B6h0000h~00FFh128KB Block1510097h0000h~00FFh128KB Block18300B7h0000h~00FFh128KB Block1520098h0000h~00FFh128KB Block18400B8h0000h~00FFh128KB Block1530099h0000h~00FFh128KB Block18500B9h0000h~00FFh128KB Block154009Ah0000h~00FFh128KB Block18600BAh0000h~00FFh128KB Block155009Bh0000h~00FFh128KB Block18700BBh0000h~00FFh128KB Block156009Ch0000h~00FFh128KB Block18800BCh0000h~00FFh128KB Block157009Dh0000h~00FFh128KB Block18900BDh0000h~00FFh128KB Block158009Eh0000h~00FFh128KB Block19000BEh0000h~00FFh128KB Block159009Fh0000h~00FFh128KB Block19100BFh0000h~00FFh128KBBlock Block Address Page and SectorAddressSize Block Block AddressPage and SectorAddressSizeBlock19200C0h0000h~00FFh128KB Block22400E0h0000h~00FFh128KB Block19300C1h0000h~00FFh128KB Block22500E1h0000h~00FFh128KB Block19400C2h0000h~00FFh128KB Block22600E2h0000h~00FFh128KB Block19500C3h0000h~00FFh128KB Block22700E3h0000h~00FFh128KB Block19600C4h0000h~00FFh128KB Block22800E4h0000h~00FFh128KB Block19700C5h0000h~00FFh128KB Block22900E5h0000h~00FFh128KB Block19800C6h0000h~00FFh128KB Block23000E6h0000h~00FFh128KB Block19900C7h0000h~00FFh128KB Block23100E7h0000h~00FFh128KB Block20000C8h0000h~00FFh128KB Block23200E8h0000h~00FFh128KB Block20100C9h0000h~00FFh128KB Block23300E9h0000h~00FFh128KB Block20200CAh0000h~00FFh128KB Block23400EAh0000h~00FFh128KB Block20300CBh0000h~00FFh128KB Block23500EBh0000h~00FFh128KB Block20400CCh0000h~00FFh128KB Block23600ECh0000h~00FFh128KB Block20500CDh0000h~00FFh128KB Block23700EDh0000h~00FFh128KB Block20600CEh0000h~00FFh128KB Block23800EEh0000h~00FFh128KB Block20700CFh0000h~00FFh128KB Block23900EFh0000h~00FFh128KB Block20800D0h0000h~00FFh128KB Block24000F0h0000h~00FFh128KB Block20900D1h0000h~00FFh128KB Block24100F1h0000h~00FFh128KB Block21000D2h0000h~00FFh128KB Block24200F2h0000h~00FFh128KB Block21100D3h0000h~00FFh128KB Block24300F3h0000h~00FFh128KB Block21200D4h0000h~00FFh128KB Block24400F4h0000h~00FFh128KB Block21300D5h0000h~00FFh128KB Block24500F5h0000h~00FFh128KB Block21400D6h0000h~00FFh128KB Block24600F6h0000h~00FFh128KB Block21500D7h0000h~00FFh128KB Block24700F7h0000h~00FFh128KB Block21600D8h0000h~00FFh128KB Block24800F8h0000h~00FFh128KB Block21700D9h0000h~00FFh128KB Block24900F9h0000h~00FFh128KB Block21800DAh0000h~00FFh128KB Block25000FAh0000h~00FFh128KB Block21900DBh0000h~00FFh128KB Block25100FBh0000h~00FFh128KB Block22000DCh0000h~00FFh128KB Block25200FCh0000h~00FFh128KB Block22100DDh0000h~00FFh128KB Block25300FDh0000h~00FFh128KB Block22200DEh0000h~00FFh128KB Block25400FEh0000h~00FFh128KB Block22300DFh0000h~00FFh128KB Block25500FFh0000h~00FFh128KBBlock Block Address Page and SectorAddressSize Block Block AddressPage and SectorAddressSizeBlock2560100h0000h~00FFh128KB Block2880120h0000h~00FFh128KB Block2570101h0000h~00FFh128KB Block2890121h0000h~00FFh128KB Block2580102h0000h~00FFh128KB Block2900122h0000h~00FFh128KB Block2590103h0000h~00FFh128KB Block2910123h0000h~00FFh128KB Block2600104h0000h~00FFh128KB Block2920124h0000h~00FFh128KB Block2610105h0000h~00FFh128KB Block2930125h0000h~00FFh128KB Block2620106h0000h~00FFh128KB Block2940126h0000h~00FFh128KB Block2630107h0000h~00FFh128KB Block2950127h0000h~00FFh128KB Block2640108h0000h~00FFh128KB Block2960128h0000h~00FFh128KB Block2650109h0000h~00FFh128KB Block2970129h0000h~00FFh128KB Block266010Ah0000h~00FFh128KB Block298012Ah0000h~00FFh128KB Block267010Bh0000h~00FFh128KB Block299012Bh0000h~00FFh128KB Block268010Ch0000h~00FFh128KB Block300012Ch0000h~00FFh128KB Block269010Dh0000h~00FFh128KB Block301012Dh0000h~00FFh128KB Block270010Eh0000h~00FFh128KB Block302012Eh0000h~00FFh128KB Block271010Fh0000h~00FFh128KB Block303012Fh0000h~00FFh128KB Block2720110h0000h~00FFh128KB Block3040130h0000h~00FFh128KB Block2730111h0000h~00FFh128KB Block3050131h0000h~00FFh128KB Block2740112h0000h~00FFh128KB Block3060132h0000h~00FFh128KB Block2750113h0000h~00FFh128KB Block3070133h0000h~00FFh128KB Block2760114h0000h~00FFh128KB Block3080134h0000h~00FFh128KB Block2770115h0000h~00FFh128KB Block3090135h0000h~00FFh128KB Block2780116h0000h~00FFh128KB Block3100136h0000h~00FFh128KB Block2790117h0000h~00FFh128KB Block3110137h0000h~00FFh128KB Block2800118h0000h~00FFh128KB Block3120138h0000h~00FFh128KB Block2810119h0000h~00FFh128KB Block3130139h0000h~00FFh128KB Block282011Ah0000h~00FFh128KB Block314013Ah0000h~00FFh128KB Block283011Bh0000h~00FFh128KB Block315013Bh0000h~00FFh128KB Block284011Ch0000h~00FFh128KB Block316013Ch0000h~00FFh128KB Block285011Dh0000h~00FFh128KB Block317013Dh0000h~00FFh128KB Block286011Eh0000h~00FFh128KB Block318013Eh0000h~00FFh128KB Block287011Fh0000h~00FFh128KB Block319013Fh0000h~00FFh128KB。