LINEAR LTC6804-1

TYPICAL APPLICATIONFEATURESDESCRIPTIONThe L TC ®6804 is a 3rd generation multicell battery stack monitor that measures up to 12 series connected battery cells with a total measurement error of less than 1.2mV. The cell measurement range of 0V to 5V makes the LTC6804 suitable for most battery chemistries. All 12 cell voltages can be captured in 290µs, and lower data acquisition rates can be selected for high noise reduction.Multiple LTC6804 devices can be connected in series, permitting simultaneous cell monitoring of long, high volt-age battery strings. Each LTC6804 has an isoSPI interface for high speed, RF-immune, local area communications. Using the LTC6804-1, multiple devices are connected in a daisy-chain with one host processor connection for all devices. Using the LTC6804-2, multiple devices are con-nected in parallel to the host processor, with each device individually addressed.Additional features include passive balancing for each cell, an onboard 5V regulator, and 5 general purpose I/O lines. In sleep mode, current consumption is reduced to 4µA. The LTC6804 can be powered directly from the battery, or from an isolated supply.L , L T, L TC , L TM, Linear Technology and the Linear logo are registered and isoSPI is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.Total Measurement Errorvs Temperature of 5 Typical UnitsAPPLICATIONSnMeasures Up to 12 Battery Cells in Series n Stackable Architecture Supports 100s of Cells n Built-In isoSPI™ Interface:1Mbps Isolated Serial CommunicationsUses a Single T wisted Pair, Up to 100 Meters Low EMI Susceptibility and Emissions n 1.2mV Maximum Total Measurement Error n 290µs to Measure All Cells in a Systemn Synchronized Voltage and Current Measurement n 16-Bit Delta-Sigma ADC with Frequency Programmable 3rd Order Noise Filtern Engineered for ISO26262 Compliant Systems n Passive Cell Balancing with Programmable Timer n 5 General Purpose Digital I/O or Analog Inputs: Temperature or other Sensor Inputs Configurable as an I 2C or SPI Master n 4μA Sleep Mode Supply Current n 48-Lead SSOP PackagenElectric and Hybrid Electric Vehicles n Backup Battery SystemsnGrid Energy StoragenHigh Power Portable Equipment12S1P++++++TEMPERATURE (°C)M E A S U R E M E N T E R R O R (m V )1.5680412 TA01b0–1.0–1.5–2.02.01.00.5–0.5TABLE OF CONTENTSFeatures (1)Applications (1)Typical Application (1)Description (1)Absolute Maximum Ratings (3)Pin Configuration (3)Order Information (4)Electrical Characteristics (4)Pin Functions (17)Block Diagram (18)Operation (20)State Diagram (20)LTC6804 Core State Descriptions (20)isoSPI State Descriptions (21)Power Consumption (21)ADC Operation (21)Data Acquisition System Diagnostics (26)Watchdog and Software Discharge Timer (30)I2C/SPI Master on LTC6804 Using GPIOS (31)Serial Interface Overview (34)4-Wire Serial Peripheral Interface (SPI) Physical Layer (35)2-Wire Isolated Interface (isoSPI) Physical Layer (35)Data Link Layer (41)Network Layer (41)Programming Examples (52)Simple Linear Regulator (56)Improved Regulator Power Efficiency (56)Fully Isolated Power (57)Reading External Temperature Probes (57)Expanding the Number of Auxiliary Measurements 58 Internal Protection Features (58)Filtering of Cell and GPIO Inputs (58)Cell Balancing with Internal Mosfets (60)Cell Balancing with External MOSFETS (60)Discharge Control During Cell Measurements (60)Power Dissipation and Thermal Shutdown (61)Method to Verify Balancing Circuitry (61)Current Measurement with a Hall Effect Sensor (64)Current Measurement with a Shunt Resistor (64)Using the LTC6804 with Less Than 12 Cells (65)Connecting Multiple LTC6804-1 on theSame PCB (65)Connecting a MCU to an LTC6804-1 with an isoSPI Data Link (65)Configuring the LTC6804-2 in a Multi-Drop isoSPI Link (65)Transformer Selection Guide (67)Package Description (71)Typical Application (72)Related Parts (72)ABSOLUTE MAXIMUM RATINGSTotal Supply Voltage V + to V –....................................75V Input Voltage (Relative to V –)C0 .........................................................–0.3V to 0.3V C12 ........................................................–0.3V to 75V C(n) .....................................–0.3V to MIN (8 • n, 75V) S(n) .....................................–0.3V to MIN (8 • n, 75V) IPA, IMA, IPB, IMB ....................–0.3V to V REG + 0.3V DRIVE Pin ................................................–0.3V to 7V All Other Pins ...........................................–0.3V to 6V Voltage Between Inputs (Note 2)C(n) to C(n – 1) ........................................–0.3V to 8V S(n) to C(n – 1) ........................................–0.3V to 8V C12 to C8 ...............................................–0.3V to 25V C8 to C4 .................................................–0.3V to 25V C4 to C0 .................................................–0.3V to 25V(Note 1)PIN CONFIGURATIONCurrent In/Out of PinsAll Pins Except V REG , IPA, IMA, IPB, IMB, S(n) ..10mA IPA, IMA, IPB, IMB .............................................30mA Operating Temperature RangeLTC6804I .............................................–40°C to 85°C LTC6804H ..........................................–40°C to 125°C Specified Temperature RangeLTC6804I .............................................–40°C to 85°C LTC6804H ..........................................–40°C to 125°C Junction Temperature ...........................................150°C Storage Temperature..............................–65°C to 150°C Lead Temperature (Soldering, 10sec)....................300°CORDER INFORMATIONELECTRICAL CHARACTERISTICSSYMBOLPARAMETERCONDITIONSMIN TYP MAX UNITS ADC DC SpecificationsMeasurement Resolution l0.1mV/bit ADC Offset Voltage (Note 2)l 0.1mV ADC Gain Error(Note 2)l0.01 0.02% %Total Measurement Error (TME) in Normal ModeC(n) to C(n – 1), GPIO(n) to V – = 0±0.2mVC(n) to C(n – 1) = 2.0±0.1±0.8mV C(n) to C(n – 1), GPIO(n) to V – = 2.0l±1.4mV C(n) to C(n – 1) = 3.3±0.2±1.2mV C(n) to C(n – 1), GPIO(n) to V – = 3.3l ±2.2mV C(n) to C(n – 1) = 4.2±0.3±1.6mV C(n) to C(n – 1), GPIO(n) to V – = 4.2l ±2.8mV C(n) to C(n – 1), GPIO(n) to V – = 5.0±1mV Sum of Cellsl ±0.2±0.75%Internal Temperature, T = Maximum Specified Temperature ±5°CV REG Pin l ±0.1±0.25%V REF2 Pinl ±0.02±0.1%Digital Supply Voltage V REGDl ±0.1±1%The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. The test conditions are V + = 39.6V, V REG = 5.0V unless otherwise noted.LEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6804IG-1#PBF LTC6804IG-1#TRPBF LTC6804G-148-Lead Plastic SSOP –40°C to 85°C LTC6804HG-1#PBF LTC6804HG-1#TRPBF LTC6804G-148-Lead Plastic SSOP –40°C to 125°C LTC6804IG-2#PBF LTC6804IG-2#TRPBF LTC6804G-248-Lead Plastic SSOP –40°C to 85°C LTC6804HG-2#PBFLTC6804HG-2#TRPBFLTC6804G-248-Lead Plastic SSOP–40°C to 125°CConsult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult L TC Marketing for information on nonstandard lead based finish parts.For more information on lead free part marking, go to: /leadfree/For more information on tape and reel specifications, go to: /tapeandreel/ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSTotal Measurement Error (TME) in Filtered Mode C(n) to C(n – 1), GPIO(n) to V– = 0±0.1mV C(n) to C(n – 1) = 2.0±0.1±0.8mV C(n) to C(n – 1), GPIO(n) to V– = 2.0l±1.4mV C(n) to C(n – 1) = 3.3±0.2±1.2mV C(n) to C(n – 1), GPIO(n) to V– = 3.3l±2.2mV C(n) to C(n – 1) = 4.2±0.3±1.6mV C(n) to C(n – 1), GPIO(n) to V– = 4.2l±2.8mV C(n) to C(n – 1), GPIO(n) to V– = 5.0±1mV Sum of Cells l±0.2±0.75% Internal Temperature, T = MaximumSpecified Temperature±5°C V REG Pin l±0.1±0.25% V REF2 Pin l±0.02±0.1% Digital Supply Voltage V REGD l±0.1±1%Total Measurement Error (TME) in Fast Mode C(n) to C(n – 1), GPIO(n) to V– = 0±2mV C(n) to C(n – 1), GPIO(n) to V– = 2.0l±4mV C(n) to C(n – 1), GPIO(n) to V– = 3.3l±4.7mV C(n) to C(n – 1), GPIO(n) to V– = 4.2l±8.3mV C(n) to C(n – 1), GPIO(n) to V– = 5.0±10mV Sum of Cells l±0.3±1% Internal Temperature, T = MaximumSpecified Temperature±5°C V REG Pin l±0.3±1% V REF2 Pin l±0.1±0.25% Digital Supply Voltage V REGD l±0.2±2%Input Range C(n), n = 1 to 12l C(n – 1)C(n – 1) + 5VC0l0GPIO(n), n = 1 to 5l05VI L Input Leakage Current When InputsAre Not Being Measured C(n), n = 0 to 12l10±250nA GPIO(n), n = 1 to 5l10±250nAInput Current When Inputs Are Being Measured C(n), n = 0 to 12±2µA GPIO(n), n = 1 to 5±2µAInput Current During Open Wire Detectionl70100130µA The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. The test conditions are V+ = 39.6V, V REG = 5.0V unless otherwise noted.ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSI VP V+ Supply Current(See Figure 1: LTC6804 OperationState Diagram)State: Core = SLEEP, isoSPI = IDLE V REG = 0V 3.86µAV REG = 0V l 3.810µAV REG = 5V 1.63µAV REG = 5V l 1.65µA State: Core = STANDBY183250µAl103260µA State: Core = REFUP or MEASURE 0.40.550.7mAl0.3750.550.725mAI REG(CORE)V REG Supply Current(See Figure 1: LTC6804 OperationState diagram)State: Core = SLEEP, isoSPI = IDLE V REG = 5V 2.24µAV REG = 5V l 2.26µA State: Core = STANDBY103560µAl63565µA State: Core = REFUP0.20.450.7mAl0.150.450.75mA State: Core = MEASURE10.811.512.2mAl10.711.512.3mAI REG(isoSPI)Additional V REG Supply Current ifisoSPI in READY/ACTIVE StatesNote: ACTIVE State CurrentAssumes t CLK = 1µs, (Note 3)LTC6804-2: ISOMD = 1,R B1 + R B2 = 2kREADY l 3.9 4.8 5.8mAACTIVE l 5.1 6.17.3mA LTC6804-1: ISOMD = 0,R B1 + R B2 = 2kREADY l 3.7 4.6 5.6mAACTIVE l 5.7 6.88.1mA LTC6804-1: ISOMD = 1,R B1 + R B2 = 2kREADY l 6.57.89.5mAACTIVE l10.211.313.3mA LTC6804-2: ISOMD = 1,R B1 + R B2 = 20kREADY l 1.3 2.13mAACTIVE l 1.6 2.5 3.5mA LTC6804-1: ISOMD = 0,R B1 + R B2 = 20kREADY l 1.1 1.9 2.8mAACTIVE l 1.5 2.3 3.3mA LTC6804-1: ISOMD = 1,R B1 + R B2 = 20kREADY l 2.1 3.3 4.9mAACTIVE l 2.7 4.1 5.8mA The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. The test conditions are V+ = 39.6V, V REG = 5.0V unless otherwise noted.ELECTRICAL CHARACTERISTICSt CYCLE (Figure 3)Measurement + Calibration CycleTime When Starting from theREFUP State in Normal ModeMeasure 12 Cells l212023352480µsMeasure 2 Cells l365405430µsMeasure 12 Cells and 2 GPIO Inputs l284531333325µs Measurement + Calibration CycleTime When Starting from theREFUP State in Filtered ModeMeasure 12 Cells l183201.3213.5msMeasure 2 Cells l30.5433.635.64msMeasure 12 Cells and 2 GPIO Inputs l244268.4284.7ms Measurement + Calibration CycleTime When Starting from theREFUP State in Fast ModeMeasure 12 Cells l101011131185µsMeasure 2 Cells l180201215µsMeasure 12 Cells and 2 GPIO Inputs l142015641660µst SKEW1 (Figure 6)Skew Time. The Time Differencebetween C12 and GPIO2Measurements, Command =ADCVAXFast Mode l189208221µsNormal Mode l493543576µst SKEW2 (Figure 3)Skew Time. The TimeDifference between C12 and C0Measurements, Command = ADCVFast Mode l211233248µsNormal Mode l609670711µst WAKE Regulator Start-Up Time V REG Generated from Drive Pin (Figure 28)l100300µst SLEEP Watchdog or Software DischargeTimer SWTEN Pin = 0 or DCTO[3:0] = 0000l 1.82 2.2sec SWTEN Pin = 1 and DCTO[3:0] ≠ 00000.5120mint REFUP (Figure 1, Figures 3 to 7)Reference Wake-Up Time State: Core = STANDBY l 2.7 3.5 4.4msState: Core = REFUP l0msf S ADC Clock Frequency l 3.0 3.3 3.5MHz SPI Interface DC SpecificationsV IH(SPI)SPI Pin Digital Input Voltage High Pins CSB, SCK, SDI l 2.3V V IL(SPI)SPI Pin Digital Input Voltage Low Pins CSB, SCK, SDI l0.8V V IH(CFG)Configuration Pin DigitalInput Voltage HighPins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3l 2.7VV IL(CFG)Configuration Pin DigitalInput Voltage Low Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3l 1.2V The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. The test conditions are V+ = 39.6V, V REG = 5.0V unless otherwise noted.ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I LEAK(DIG)Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN,A0 to A3l±1µA V OL(SDO)Digital Output Low Pin SDO Sinking 1mA l0.3V isoSPI DC Specifications (See Figure 16)V BIAS Voltage on IBIAS Pin READY/ACTIVE StateIDLE State l 1.9 2.02.1VVI B Isolated Interface Bias Current R BIAS = 2k to 20k l0.1 1.0mAA IB Isolated Interface Current Gain V A ≤ 1.6V I B = 1mAI B = 0.1mA ll181820202224.5mA/mAmA/mAV A T ransmitter Pulse Amplitude V A = |V IP – V IM|l 1.6V V ICMP Threshold-Setting Voltage on ICMPPinV TCMP = A TCMP • V ICMP l0.2 1.5V I LEAK(ICMP)Input Leakage Current on ICMP Pin V ICMP = 0V to V REG l±1µA I LEAK(IP/IM)Leakage Current on IP and IM Pins IDLE State, V IP or V IM = 0V to V REG l±1µA A TCMP Receiver Comparator ThresholdVoltage GainV CM = V REG/2 to V REG – 0.2V, V ICMP = 0.2V to 1.5V l0.40.50.6V/V V CM Receiver Common Mode Bias IP/IM Not Driving(V REG – V ICMP/3 – 167mV)V R IN Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB l273543kΩisoSPI Idle/Wakeup Specifications (See Figure 21)V WAKE Differential Wake-Up Voltage t DWELL = 240ns l200mV t DWELL Dwell Time at V WAKE Before WakeDetectionV WAKE = 200mV l240ns t READY Startup Time After Wake Detection l10µs t IDLE Idle Timeout Duration l 4.3 5.5 6.7ms isoSPI Pulse Timing Specifications (See Figure 19)t1/2PW(CS)Chip-Select Half-Pulse Width l120150180ns t INV(CS)Chip-Select Pulse Inversion Delay l200ns t1/2PW(D)Data Half-Pulse Width l405060ns t INV(D)Data Pulse Inversion Delay l70ns SPI Timing Requirements (See Figure 15 and Figure 20)t CLK SCK Period (Note 4)l1µs t1SDI Setup Time before SCK RisingEdgel25nst2SDI Hold Time after SCK RisingEdgel25ns t3SCK Low t CLK = t3 + t4 ≥ 1µs l200ns t4SCK High t CLK = t3 + t4 ≥ 1µs l200ns t5CSB Rising Edge to CSB FallingEdgel0.65µst6SCK Rising Edge to CSB RisingEdge(Note 4)l0.8µst7CSB Falling Edge to SCK RisingEdge (Note 4)l1µs The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. The test conditions are V+ = 39.6V, V REG = 5.0V unless otherwise noted.ELECTRICAL CHARACTERISTICSSYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSisoSPI Timing Specifications (See Figure 19)t 8SCK Falling Edge to SDO Valid (Note 5)l 60ns t 9SCK Rising Edge to Short ±1 T ransmitl 50ns t 10CSB T ransition to Long ±1 T ransmit l 60ns t 11CSB Rising Edge to SDO Rising (Note 5)l 200ns t RTN Data Return Delayl 430525ns t DSY(CS)Chip-Select Daisy-Chain Delay l 150200ns t DSY(D)Data Daisy-Chain Delay l 300360ns t LAG Data Daisy-Chain Lag (vs Chip-Select)l 03570ns t 6(GOV)Data to Chip-Select Pulse Governorl0.81.05µsThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. The test conditions are V + = 39.6V, V REG = 5.0V unless otherwise noted.Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The ADC specifications are guaranteed by the Total Measurement Error specification.Note 3: The ACTIVE state current is calculated from DC measurements. The ACTIVE state current is the additional average supply current into V REG when there is continuous 1MHz communications on the isoSPI ports with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply current. See Applications Information section for additional details.Note 4: These timing specifications are dependent on the delay through the cable, and include allowances for 50ns of delay each direction. 50ns corresponds to 10m of CAT-5 cable (which has a velocity of propagation of 66% the speed of light). Use of longer cables would require derating these specs by the amount of additional delay.Note 5: These specifications do not include rise or fall time of SDO. While fall time (typically 5ns due to the internal pull-down transistor) is not a concern, rising-edge transition time t RISE is dependent on the pull-up resistance and load capacitance on the SDO pin. The time constant must be chosen such that SDO meets the setup time requirements of the MCU.Note 6: V + needs to be greater than or equal to the highest C(n) voltage for accurate measurements. See the graph Top Cell Measurement Error vs V +.Measurement Error vs Input, Normal ModeMeasurement Error vs Input, Filtered ModeMeasurement Error vs Input, Fast ModeMeasurement Error vs TemperatureMeasurement Error Due to IR ReflowMeasurement Error Long- Term DriftTYPICAL PERFORMANCE CHARACTERISTICSMeasurement Noise vs Input, Normal ModeMeasurement Noise vs Input, Filtered ModeMeasurement Noise vs Input, Fast ModeT A = 25°C, unless otherwise noted.TEMPERATURE (°C)M E A S U R E M E N T E R R O R (m V )1.5680412 G010–1.0–1.5–2.02.01.00.5–0.5CHANGE IN GAIN ERROR (ppm)N U M B E R O F P A R T S202530680412 G021510535TIME (HOURS)0M E A S U R E M E N T E R R O R (p p m )305251520100680412 G0330001000200025005001500INPUT (V)M E A S U R E M E N T E R R O R (m V )–0.500.53680412 G04–1.0–1.5–2.01.01.52.0INPUT (V)M E A S U R E M E N T E R R O R (m V )–0.500.535680412 G05–1.0–1.5–2.01241.01.52.0INPUT (V)M E A S U R E M E N T E R R O R (m V )2610680412 G06–2–6048–4–8–10INPUT (V)P E A K N O I S E (m V )0.60.81.04680412 G070.40.20.50.70.90.30.101235INPUT (V)P E A K N O I S E (m V )0.60.81.04680412 G080.40.20.50.70.90.30.101235INPUT (V)P E A K N O I S E (m V )68104680412 G0942579310123TYPICAL PERFORMANCE CHARACTERISTICSMeasurement Gain Error Hysteresis, HotMeasurement Gain Error Hysteresis, ColdNoise Filter ResponseMeasurement Error vs V REGMeasurement Error V + PSRR vs FrequencyMeasurement Error V REG PSRR vs FrequencyT A = 25°C, unless otherwise noted.CHANGE IN GAIN ERROR (ppm)–50N U M B E R O F P A R T S152025–20030680412 G10105–40–30–101020CHANGE IN GAIN ERROR (ppm)N U M B E R O F P A R T S5101520680412 G112530INPUT FREQUENCY (Hz)10N O I S E R E J E C T I O N (d B )0–50–10–30–20–40–70–60680412 G121M1k 100k 10010k FIL TERED2kHz3kHzADC MODE:NORMAL 15kHz FAST V REG (V)M E A S U R E M E N T E R R O R (m V )00.51.0680412 G13–0.5–1.0–2.0–1.52.01.5FREQUENCY (Hz)P S R R (d B )–60–50–40680412 G14–70–80–65–55–45–75–85–90FREQUENCY (Hz)–20–10068412 G15–30–40–50–60–70P S R R (d B )Cell Measurement Error vs Input RC ValuesGPIO Measurement Error vs Input RC ValuesINPUT RESISTOR, R (Ω)1C E L L M E A S U R E M E N T E R R O R (m V )051010000680412 G16–5–10–20101001000–152015INPUT RESISTANCE, R (Ω)1M E A S U R E M E N T E R R O R (m V )261010000680412 G17–2–6048–4–8–10101001000100000680412 G18TYPICAL PERFORMANCE CHARACTERISTICSCell Measurement Error vs Common Mode VoltageCell Measurement CMRR vs FrequencyMeasurement Error vs V +Sleep Supply Current vs V +Standby Supply Current vs V +REFUP Supply Current vs V +T A = 25°C, unless otherwise noted.C11 VOLTAGE (V)–1.0C E L L 12 M E A S U R E M E N T E R R O R (m V )–0.8–0.4–0.201.00.41020680412 G19–0.60.60.80.230FREQUENCY (Hz)100–90R E J E C T I O N (d B )–80–60–50–4010k1M10M0680412 G20–701k100k –30–20–10V + (V)5M E A S U R E M E N T E R R O R (m V )1.520680412 G210–1.0101525–1.5–2.02.01.00.5–0.5303540V + (V)2S L E E P S U P P L Y C U R R E N T (µA )47680412 G22365V + (V)15540S TA N DB Y S U P P L YC U R R E N T (µA )50802555680412 G2370603565V + (V)155850R E F U P S U P P L Y C U R R E N T (µA )10002555680412 G249509003565Measure Mode Supply Current vs V +Measurement Time vs TemperatureInternal Die TemperatureMeasurement Error vs TemperatureV + (V)M E A S U R E M O D E S U P P L Y C U R R E N T (m A )12.0012.2512.50680412 G2511.7511.5011.2511.00TEMPERATURE (°C)M E A S U R E M E N T T I M E (µs )2420680412 G2623602320230022802440240023802340TEMPERATURE (°C)–50–10T E M P E R A T U R E M E A S U R E M E N T E R R O R (D E G )–8–4–2010405075100680412 G27–6682–2525125TYPICAL PERFORMANCE CHARACTERISTICSV REF2 vs TemperatureV REF2 Load RegulationV REF2 V + Line RegulationV REF2 V REG Line RegulationV REF2 Hysteresis, HotV REF2 Power-UpV REF2 Hysteresis, ColdV REF2 Long-Term DriftV REF2 Change Due to IR ReflowT A = 25°C, unless otherwise noted.TEMPERATURE (°C)–50V R E F 2 (V )3.0013.0023.0032575680412 G283.0002.999–252.9982.997I OUT (mA)0.01C H A N G E I N V R E F 2 (p p m )–600–400680412 G29–800–10000–200V + (V)5C H A N G E I N V R E F 2 (p p m )150******** G300–100152545–150–20020010050–50556575V REG (V)4.5–150C H A N G E I N V R E F 2 (pp m )–100–50050100150 4.755 5.25 5.5680412 G31V R E F 2 (V )C S B1.52.53.5680412 G320.551.02.03.000–51ms/DIVTIME (HOURS)0C H A N G E I N V R E F 2 (p p m )0680412 G33–50–10050050100–25–7525753000CHANGE IN REF2 (ppm)N U M B E R O F P A R T S152025680412 G341050CHANGE IN REF2 (ppm)N U M B E R O F P A R T S812680412 G3540–200–15016610214CHANGE IN REF2 (ppm)0N U M B E R O F P A R T S10203051525–500–300–100100680412 G36300–700TYPICAL PERFORMANCE CHARACTERISTICSDrive and V REG Pin Power-UpV REF1 Power-UpV REF1 vs TemperatureInternal Die Temperature Increase vs Discharge CurrentisoSPI Current (READY) vs TemperatureisoSPI Current (READY/ACTIVE) vs isoSPI Clock FrequencyDischarge Switch On-Resistance vs Cell VoltageDrive Pin Load RegulationDrive Pin Line RegulationT A = 25°C, unless otherwise noted.CELL VOLTAGE (V)0D I S C H A R G E S W I T C H O N -R E S I S T A N C E (Ω)5152025503512680412 G3710404530345I LOAD (mA)0.01C H A N G E I ND R I VE P I N V O L T A G E (m V )–60–401680412 G38–80–1000–20V + (V)515–15C H A N G E I ND R I VE P I N V O L T A G E (m V )–510254555680412 G39–10535657545632100µs/DIV10–1V D R I V E A N D V R E G (V )V R E F 1 (V )C S B1.52.53.50.55–51.02.03.00TEMPERATURE (°C)–503.145V RE F 1 (V )3.1463.1483.1493.1503.1553.15205075100680412 G423.1473.1533.1543.151–2525125INTERNAL DISCHARGE CURRENT (mA PER CELL)I N C R E A S E I N D I E T E M P E R A T U R E (°C )51520255035680412 G431040453060isoSPI CLOCK FREQUENCY (kHz)101214680412 G458642i s o S P I C U RR E N T (m A )TEMPERATURE (°C)4i s o S P I C U R R E N T (m A )69680412 G44587100TYPICAL PERFORMANCE CHARACTERISTICSisoSPI Driver Current Gain (Port A/PortB) vs TemperatureisoSPI Driver Common Mode Voltage (Port A/Port B) vs Pulse AmplitudeisoSPI Comparator Threshold Gain (Port A/Port B) vs Common ModeisoSPI Comparator Threshold Gain (Port A/Port B) vs ICMP VoltageTypical Wake-Up Pulse Amplitude (Port A) vs Dwell TimeI BIAS Voltage vs TemperatureI BIAS Voltage Load RegulationisoSPI Driver Current Gain (Port A/PortB) vs Bias CurrentT A = 25°C, unless otherwise noted.TEMPERATURE (°C)1.98I B I A S P I N V O L T A G E (V )1.992.002.012.02680412 G46BIAS CURRENT (µA)0I B I A S P I N V O L T A G E (V )2.0002.005800408912 G471.9951.99020040060010002.010BIAS CURRENT (µA)C U R R E N T G A I N (m A /m A )212223680412 G48201918TEMPERATURE (°C)18C U R R E N T G A I N (m A /m A )2023680412 G49192221100PULSE AMPLITUDE (V)2.5D R I VE R C O M M O N M O D E (V )3.03.54.04.55.05.50.5 1.0 1.5 2.0680412 G50COMMON MODE VOLTAGE (V)0.44C O M P A R A T O R T H R E S H O LD G A I N (V /V )0.460.480.500.520.56 3.0680412 G510.54ICMP VOLTAGE (V)00.44C O M P A R A T O R T H R E S H O LD G A I N (V /V )0.460.480.500.52680412 G520.540.56WAKE-UP DWELL TIME, t DWELL (ns)W A K E -U P P U L S E A M P L I T U D E , V W A K E (m V )150200600680412 G5310050150300450300250TYPICAL PERFORMANCE CHARACTERISTICST A = 25°C, unless otherwise noted.Write Command to a Daisy-Chained Device (ISOMD = 0)Data Read-Back from a Daisy-Chained Device (ISOMD = 0)Write Command to a Daisy-Chained Device (ISOMD = 1)Data Read-Back from a Daisy-Chained Device (ISOMD = 1)CSB5V/DIV SDI 5V/DIV SCK 5V/DIV SDO 5V/DIV IPB-IMB 2V/DIV (PORT B)1µs/DIV680412 G54ISOMD = V –BEGINNING OF A COMMANDPORT AIPB-IMB 1V/DIV (PORT B)IPA-IMA 1V/DIV (PORT A)1µs/DIV680412 G55ISOMD = V REGBEGINNING OF A COMMANDCSB 5V/DIVSDI 5V/DIVSCK 5V/DIV SDO 5V/DIV IPB-IMB 2V/DIV (PORT B)PORT A1µs/DIV680412 G56ISOMD = V –END OF A READ COMMANDIPB-IMB 1V/DIV (PORT B)IPA-IMA 1V/DIV (PORT A)1µs/DIV680412 G57ISOMD = V REGEND OF A READ COMMAND。