NCP3520中文资料
国内外材料对照表

H13
H1 CG11 Gபைடு நூலகம்0E
HTi10
TH10 G1F T821* T801* T811* T802* T823* T803* T813* T530* T221* T370*
HK15*
WK1 CM3
WK1 WHN33* WTN33*
CP1 CP3 CM2 KM1 CF3
抗拉强度 MPa
Q/BQB3401999
A03560 A13560
356.0 A356.0
A14130
A413.0
—
A03600 A13600 A03550 C33550 A03280 A03281 A03190 A03191
—
A03360 A03361
—
A03541 A03540
— 360.0 A360.0 355.0 C355.0 328.0 328.1
510
550
15MnCuCr-QT
(GB 4172-84)
COR-TEN C
570
SMA570W、P COR-TEN 60
(JISG3114-98)
品种分类
中国 GB
各国最常用铜及铜合金牌号对照表
国际标准
美国
日本
ISO
ASTM
JIS
英国 BS
德国 DIN
紫铜 (红铜) 银铜 黄铜
锡青铜
锌白铜
引线框架
09CuPCrNi-A
SPA-H(厚度≤6mm)
COR-TEN A 、B
(GB 4171-84)
(JIS G3125-87)
490
B490NQR
15MnCuCr
09CuPCrN
SPA-H(厚度>6mm)
TMP320C6202BGLW120资料

Copyright 2004, Texas Instruments Incorporated
POST OFFICE BOX 1443
• HOUSTON, TEMS320C6205 FIXED-POINT DIGITAL SIGNAL PROCESSOR
D
D
D
D
D D
Signal Processor (DSP) − TMS320C6205 − 5-ns Instruction Cycle Time − 200-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600 MIPS VelociTI Advanced-Very-Long-InstructionWord (VLIW) TMS320C62x DSP Core − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional Instruction Set Features − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization 1M-Bit On-Chip SRAM − 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) − 512K-Bit Dual-Access Internal Data (64K Bytes) − Organized as Two 32K-Byte Blocks for Improved Concurrency 32-Bit External Memory Interface (EMIF) − Glueless Interface to Synchronous Memories: SDRAM or SBSRAM − Glueless Interface to Asynchronous Memories: SRAM and EPROM − 52M-Byte Addressable External Memory Space Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel Flexible Phase-Locked-Loop (PLL) Clock Generator
NCP1207A中文资料

5.0 ms Timeout
Timeout Reset
380 ns
L.E.B.
CS
Demag
ÁÁÁÁÁÁMAÁÁÁXIMÁÁÁUMÁÁÁRATÁÁÁINGÁÁÁS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁFRiÁÁÁgautirnÁÁÁeg2.ÁÁÁInteÁÁÁrnaÁÁÁl CiÁÁÁrcuiÁÁÁt ArÁÁÁchitÁÁÁectÁÁÁureÁÁÁÁÁÁÁÁÁÁÁÁSymÁÁÁbolÁÁÁÁÁÁVaÁÁlÁue ÁÁÁÁÁÁUniÁÁtÁs
© Semiconductor Components Industries, LLC, 2004
1
November, 2004 − Rev. 1
Publication Order Number: NCP1207A/D
元器件交易网
NCP1207A
Universal Network
NCP1207ADR2 SOIC−8 2500/Tape & Reel
NCP1207ADR2G NCP1207AP
SOIC−8 (Pb−Free)
PDIP−8
2500/Tape & Reel 50 Units/Tube
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
2
FB
Sets the peak current setpoint By connecting an Optocoupler to this pin, the peak current setpoint is
IMP3520D中文版资料

3520D
自适应整流器控制芯片
应用信息
(续)
内部集成在VCC和VB之间的自举MOSFET将决定高压侧驱动电路的电源电压。由电容CSNUB和二极管 DCP1、DCP2组成的外部电荷泵电路将给低压侧驱动电路提供一个额外的电源。为了保证在第一个脉冲到达HO之 前高压侧的电源已经被充电到了高电平,开始的时候的输出脉冲都是有LO脚输出的。可能LO震荡了好几个周期 后,VB-VS的电压才能超过高压侧的欠压钳位阈值VBSUV+ (9 Volts),这个时候高压侧才能有输出。在整个UVLO模 式期间,高压侧和低压侧的输出HO、LO都是低电平,VCO脚也是被拉到GND电平将启动频率设置成最大值。
—
2.7
—
—
45
80
µA
—
100
—
—
4.5
—
mA
—
2.0
—
14.4 15.4 —
V
—
80 150
—
20
40
µA
7.7
9.0 10.3
V
6.8
8.0
9.2
V
—
—
50
µA
30
36
45
70
90
110
kHz
—
50
—
%—Biblioteka 2.0—µS
—
2.0
—
µS
—
80
—
0.8
1.6
2.0
µA
—
1.1
—
—
6
—
V
— COM —
mV
频率扫描模式
当VCC超过阈值VCCUV+ ,3520D进入频率扫描模式。图2中所示的一个内部的电流源给VCO引脚的外部电容 CVCO充电,使得VCO引脚的电压开始线性上升。一个额外的快速启动电流IVCOQS也和VCO引脚相连,将VCO引 脚的电压从初始值充到0 .85V。当VCO的电压超过0.85V,这个快速启动电流在内部断开,VCO的电压随着正常 频率扫描电流源IVCOFS的充电而继续被抬升(图3)。这个快速启动将VCO电压快速的带到VCO内部的范围。
Nokia 3520 说明书

Nokia 3250用户手册版权所有 © 2006 诺基亚。
保留所有权利。
1声明在此,诺基亚公司郑重声明产品 RM-38 遵守 1999/5/EC 的主要要求以及其他与之相关的指令。
此声明的全文可经由/phones/declaration_of_conformity/ 找到。
版权所有© 2006 诺基亚。
保留所有权利。
在未经诺基亚事先书面许可的情况下,严禁以任何形式复制、传递、分发和存储本文档中的任何内容。
诺基亚、Nokia 、Visual Radio (可视收音机)、Nokia Connecting People 和 Pop-Port 是诺基亚公司的商标或注册商标。
在本文档中提及的其他产品或公司的名称可能是其各自所有者的商标或商名。
Nokia tune 和 Visual Radio 是诺基亚公司的声音标志。
产品所包含的部分软件已获得 Symbian Software Ltd. 的许可证授权 © 1998-2006。
Symbian 和 Symbian 操作系统是 Symbian Ltd. 的商标。
包括 RSA Security 提供的 RSA BSAFE 密码体系或安全协议软件。
Java™ 和所有基于 Java 的标志均为 Sun Microsystems, Inc. 的商标或注册商标。
美国专利 5818437 号以及其他待定专利。
T9 文字输入软件版权所有 © 1997-2006。
Tegic Communications ,Inc.。
保留所有权利。
本产品已取得 MPEG-4 Visual Patent Portfolio License 的许可证授权,因此 (i) 当涉及由从事个人及非商业活动的用户以符合 MPEG-4 视频标准的编码方式编码的信息时,可将本产品用于相关的个人及非商业用途,且 (ii) 当视频内容由已取得 MPEG-4 许可证授权的视频内容供应商提供时,可将本产品用于相关用途。
BCM3520中文资料

• Integrated NTSC demodulator • BTSC decoder on chip • Direct interface to CMOS and discrete DTV tuners • Reduces system costs through direct IF sampling • Single IF path for QAM/VSB/NTSC simplifies board design • Smart antenna support • Automatic NTSC co-channel interference and RFI rejection
OOB Tuner
EIA/CEA-909 Smart Antenna Interface
Composite Video Audio: I2S, L/R, multiplex baseband, IF audio Out-of-band Transport
OVERVIEW Functional Block Diagram
demodulator goes to an ATSC A/53 coding Forward Error Corrector (FEC), with integrated trellis and Reed Solomon decoder. The output of the QAM demodulator goes to an ITU-T J.83 Annex A/B/C coding FEC. The output of either QAM or VSB FEC is delivered in either parallel or serial MPEG-2 transport format. The NTSC demodulator filters and demodulates the analog NTSC and FM audio signals and delivers a composite output via an on-chip 10-bit DAC. An IF modulated audio output is also provided via a second on-chip 10-bit DAC. An on-chip BTSC decoder handles the decoding of the base-band multiplexed audio from the IF demod, providing an stereo left/right, mono, or SAP output via a pair of high precision HiFiDACs. All gain, clock, and carrier, acquisition, and tracking loops are integrated on-chip as are the necessary phase-locked loops, referenced to a single external crystal. Chip configuration, channel acquisition, and performance monitoring functions are conducted by the on-chip acquisition processor using Broadcom-provided software.
NCP1395资料

−
Fault
+ Vref Fault
+
Fast Fault
−
+ Vref Fault
VCC B A PGND
元器件交易网
NCP1395A/B
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage, Pin 12
VCC
HV
Fmin Fmax Deadtime Soft−start
Timer
BO
NCP1395
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC = 15 V
NCP5181
1
8
2
7
3
6
4
5
Slow Fault Power Ground Analog Ground
Vout +
NCP1395A/B
元器件交易网
元器件交易网
NCP1395A/B
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
1
Fmin
Timing Resistor
2
Fmax
Frequency Clamp
3
DT
Deadtime
4
Css
Soft−Start
5
FB
Feedback
Transient Current Injected into VCC when Internal Zener is Activated –
NCP1207中文规格

发NCP1207电流模式PWMController for Free Running 准谐振 NCP1207集成了电流型PWM 控制和退磁检测电路,在大范围的负载和输入电压变化情况下,确保谷电压开关(准谐振方式)和borderline/critical 传导模式。
器件内部的“跳过周期”功能会在轻载时提高效率和降低空载功耗,突发模式时电路中峰值电流已经很小,所以不会产生音频范围内的噪声。
器件内的8uS 计时器,限制了开关频率不高于100KHz (低于CISPR −22 EMI 中的150KHz 限制)。
器件的“动态自给(DSS )”功能简化电路设计,可以取消变压器的辅助绕组供电,这个特点特别适用于电源输出电压大范围变化的场合,如电池充电器。
由于采用了HV 设计,器件直接连接到高压直流母线。
退磁检测电路通过一个辅助绕组检测变压器磁芯是否复位,同时这个引脚还具备快速过压保护(OVP )功能,一旦退磁检测引脚检测到的电压达到OVP 门限,器件进入闭锁状态。
连续监测反馈信号和过流故障保护(OCP )功能,使最终设计出来的产品更可靠。
器件特性 z borderline/critical 准谐振模式 z 电流型自动跳过周期模式 z 可取消辅助绕组供电 z (折返型)自动电流限(OCP ) z 过压锁死(OVP ) z 外部锁存触发。
例如外加过热保护电路 z 500mA 源/沉输出驱动能力 z 内部1mS 软启动 z 内部最小8uS 导通时间 z 可调节进入突发模式功率水平 z 集成过热保护 z 光耦合器直接连接 z SPICE 仿真模型用于瞬态分析 z 可选无铅封装典型应用 z笔记本电脑等AC/DC 适配器z 离线电池充电器 z 消费类电子设备(DVD 、机顶盒、电视机等)图一典型应用引脚说明引脚号引脚名称功能描述退磁检测与OVP 检测反激电源中一个辅助绕组上的电压确定变压器是否1 Demag复位,过压保护门限7.2V。
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NCP3520/NCP3521LDO Regulator ControllerThe NCP3520 / NCP3521 parts are Low Drop Out (LDO) regulator controllers for applications requiring high −currents and ultra low dropout voltages. The use of an external NMOS driver allows the user to adapt the device to a multitude of applications depending on system requirements for current and dropout voltage.Features•Fixed V oltage Options ♦NCP3520 (1.2 V)♦NCP3521 (1.5 V)•Low Operating Current•Low Standby Current (sleep mode < 1 m A)•Non Rush Current on Startup •Short Circuit Protection•1% Output V oltage Tolerance•Drop −In Replacement for Rohm BD3520FVM and BD3521FVM •Functionally Equivalent to theRohm BD3501FVM and BD3502FVM •These are Pb −Free DevicesTypical Applications•Computer based gaming consolesFigure 1. Application DiagramFB utilize a Kelvin connection at the load.See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.ORDERING INFORMATIONNRCSVFBGNDVSGVD VCCENFigure 2. Block DiagramPACKAGE PIN DESCRIPTION Micro8Pin #Symbol Description1NRCS Non Rush current on Startup. Capacitor to ground controls output voltage slew rate and short circuitdelay time.2GND Ground.3EN Enable input control.4VCC Power Supply Voltage Input.5VFB Voltage Feedback pin into the error amplifier for maintaining the output voltage.6VS Source input. Provides pulldown capability (1.2 mA operating & 220 mA turnoff) for fast output voltage response time.7G Gate Drive for the external NFET.8VD NFET Drain input for voltage sensing.MAXIMUM RATINGSRating Value UnitAll Pins−0.3 to 7VIG (DC) IG (AC) IVS (DC)1010300mAElectrostatic Discharge, Human Body Model 1.5kV Electrostatic Discharge, Machine Model100V Package Thermal ResistanceMicro8238°C/W Operating Junction Temperature−10 to 150°C Storage Temperature Range−55 to 150°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.ELECTRICAL CHARACTERISTICS (T J = 25°C, V CC = 5 V, V D = 2.0 V, EN = 3 V, External FET = NTMS4107N (Note 3), unless otherwise specified)Characteristic Conditions Min Typ Max Unit REGULATOR OUTPUTFeedback Voltage (NCP3520)I O (NTMS4107N) = 50 mA4.5 V < V CC <5.5 V, 0°C < T J < 100°C(Note 1)1.1881.1761.2001.2001.2121.224VVFeedback Voltage (NCP3521)I O (NTMS4107N) = 50 mA4.5 V < V CC <5.5V, 0°C < T J < 100°C(Note 1)1.4851.4701.5001.5001.5151.530VVSupply CurrentSleep ModeRun ModeShort Circuit Latch Condition EN = 0 VEN = 3 VEN = 3 V−−−1.250.5101.71.7m AmAmALine Regulation (NCP3520) 4.5 V < V CC < 5.5 V, I OUT = 04.5 V < V CC <5.5 V, I OUT = 3 A (Note 1)− 1.21.26.06.0mVmVLine Regulation (NCP3521) 4.5 V < V CC < 5.5 V, I OUT = 04.5 V < V CC <5.5 V, I OUT = 3 A (Note 1)− 1.51.57.57.5mVmVLoad Regulation (Note 2)I O = 0 A to 3 A−0.5010mV1.Guaranteed by Design2.Load regulation may vary with the selection of an external FET other than the NTMS4107N.3.See “External Components” section on Page 8.ELECTRICAL CHARACTERISTICS (T J = 25°C, V CC = 5 V, V D = 2.0 V, EN = 3 V, External FET = NTMS4107N (Note 3), unless otherwise specified)Characteristic UnitMaxTypMinConditionsOUTPUT DRIVERSource Current V FB = V OUT− 0.1 V, V GATE = 2.5 V−4−3−2mA Sink Current V FB = V OUT + 0.1 V, V GATE = 2.5 V234mA GENERALV FB Input ImpedanceNCP3520 (1.2 V)NCP3521 (1.5 V)−−2126−−k WV S Input Bias Current− 1.2 2.4mA V S Standby Current V S = 1 V, EN = 0 V150220−mA V CC Undervoltage Lockout V CC Rising 4.20 4.35 4.50V V CC Undervoltage Lockout Hysteresis100160250mV V D Undervoltage Lockout (NCP3520)0.720.840.96V V D Undervoltage Lockout (NCP3521)0.90 1.05 1.20VV D Input ImpedanceNCP3520 (1.2 V)NCP3521 (1.5 V)−−228284−−k WThermal Shutdown (Note 1)150180210°C Thermal Hysteresis (Note 1)−15−°C NON RUSH CURRENT ON STARTUP (NRCS) SHORT CIRCUIT PROTECTION (SCP)NRCS Charge Current NRCS = 0.5 V142026m A SCP Charge Current NRCS = 0.5 V142026m A SCP Discharge Current NRCS = 0.5 V300400−m A SCP Threshold Voltage 1.15 1.3 1.4V Short Detect Voltage V FB Decreasing V FB * 0.30V FB * 0.35V FB * 0.40V Power On Reset V CC−50−m S EN to G Turn on Delay−50−m S Short Circuit Powerup Decision Timer−50−m S NRCS Standby Voltage−2550mV ENABLEInput ThresholdLowHigh−2.01.341.400.8−VVInput Hysteresis−60−mV Input Current EN = 3 V−710m A1.Guaranteed by Design2.Load regulation may vary with the selection of an external FET other than the NTMS4107N.3.See “External Components” section on Page 8.−10256085TEMPERATURE (°C)V OFigure 3. 1.2 V Output Voltage versusTemperature (NCP3520)−10256095TEMPERATURE (°C)V OFigure 4. 1.5 V Output Voltage versusTemperature (NCP3521)0.0000.2000.4000.6000.8001.0001.2001.4000.000.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00V IN , INPUT VOLTAGE (V)V O U T ,O U T P U T V O L T A G E (V )Figure 5. Output Voltage versus Input Voltage(NCP3520)1.051.061.071.081.091.11.11−10256095TEMPERATURE (°C)Figure 6. Run Mode Supply Current versusTemperaturem A0.0000.2000.4000.6000.8001.0001.2001.4000.000.501.00 1.502.00 2.50 3.003.50 4.00 4.50 5.00V IN , INPUT VOLTAGE (V)I C C , I N P U T C U R R E N T (m A )Figure 7. I CC versus Input Voltage (NCP3520)Figure 8. I CC versus I LOAD (05C, 255C, 1005C)01000200030I LOAD , (mA)I C C , I N P U T C U R R E N T (m A )Figure 9. Ripple Rejection versus Frequency (V CC = 5.0 V, I LOAD= 3.0 A)1002003004005006008.09.01011121314151617181920NRCS CAPACITOR (nF)RISETIME(∝s)Figure 10. NRCS Time versus NRCS Capacitor(NCP3520) Figure 11. Load Transient Response (10 mA to1.3 A) Channel 1 (V O), Channel 2 (Switch Control)Figure 12. Load Transient Response (1.3 A to10 mA) Channel 1 (V O), Channel 2 (Switch Control) MAG(dB)0.0010.0020.0030.0040.0050.0060.0070.0010100 1 k10 k100 kControlSignalV OControlSignalV ODETAILED OPERATING DESCRIPTIONGeneralThe NCP3520/NCP3521 are LDO Regulator Controllers. An external NFET device sets the current capability allowing for designer selection.Features include an undervoltage lockout for both the integrated circuit supply Pin VCC, and the supply pin for the external FET connection to the drain of the FET.The NRCS (Non Rush Current on Startup) feature prevents high currents through the external FET (drain−source). The external capacitor setting component used in NRCS is also used for short circuit protection (SCP). The device also has an enable feature allowing it to go into a low supply current sleep mode demanded by most modern day feature rich systems when not in use.Thermal shutdown functionality protects the IC from damage caused from excessively high temperatures appearing on the IC.Output DriverOutput current drive capability is determined by the designer’s choice of external MOSFET (NFET). Power dissipated in the driver can be controlled by the voltage applied to V D. V D should be kept low to minimize power dissipation and high enough to support regulated operation at the desired output current. It should also be noted the output capacitor (V O to GND) value supports regulation during high speed transient events until the system loop can respond to any voltage dips to drive the external FET. High Speed ControlUnlike most linear regulators whose reaction to overvoltage events is to turn off the upper driver and let the external load and resistor feedback network quench the incident, the NCP3520/21 include a 1.2 mA pulldown through the VS Pin. This keeps overshoot to a minimum during powerup. During turn−off and thermal overload, the pulldown current is increased from 1.2 mA to 220 mA to provide an even faster turn−off time.Power On ResetA 50 m s power on reset circuit is built into the IC acting as a digital filter and performing housekeeping activity during a short circuit event.The timer effects three areas of operation.1.EN turn on delay. Upon detection of an EN high,there is a 50 m s delay to when the internal circuitryturns on and the gate pin (G) goes high. A low onEN resets the timer.2.V CC startup delay. If V CC drops out below theundervoltage lockout voltage and restored aboveits hysteresis value, a 50 m s time is also observedfrom reinitiation of V CC and G going high. This isrecognized to be different from the EN turn ondelay by the active circuitry of the voltagereference, NRCS circuitry, and V S high currentpulldown.3.Device startup into a short circuit. Further detailsare available on this subject under the heading“Starting Up Into A Short Circuit”.Normal Powerup/DownThe NRCS (Non Rush Current on Startup) timer controls the output driver during powerup. The output driver voltage (V G) is controlled during powerup. The voltage on NRCS is mimicked to provide a duplicate voltage on VFB. When 1.2 V is reached normal operation of the error amplifier and feedback network take over. Regulation is maintained in the loop around 1.2 V. The NRCS pin rises up to 1 V. At 1 V, the NRCS capacitor is discharged fully at a 300 m A (min) rate. The IC enters a standby mode capable of short circuit detection.A 20 m A pullup current source is used to charge the external NRCS capacitor linearly and maintain a predictable powerup. A recommended 0.01 m F will provide a 325 m s powerup time. Alternative times can be programmed with this equation:T+C(NRCS)*V FBńINRCS(eq. 1) Rush current during startup can be calculated by I = C OUT * V O / T.The NRCS circuit is not active during powerdown. Normal circuit operation will be maintained unless VCC_UVLO or VD_UVLO cause the gate drive output to turn off.NRCS1.0 V1.2 VEN3 V0.65 VFigure 13. Powerup (NCP3520 (1.2 V) Version Shown)Short Circuit Protection (SCP)The IC enters normal mode after the NRCS has gone through powerup. The NRCS capacitor has reached a 1 V (typ) threshold and fully discharged (50 mV (max)).When a short circuit event occurs it is detected when the voltage on V FB goes below (35% of V OUT ). This triggers the NRCS current source to start charging the NRCS capacitor at the same 20 m A rate as during powerup. When the voltage on the capacitor reaches 1.3 V a short circuit event is confirmed, V G goes low turning off the external FET. V S Standby Current pulldown is enabled.Clearing a Short Circuit Latch ConditionA short circuit latch condition can be cleared by toggling the EN from its high condition to a low condition, and then back to a high condition.Figure 14. Short Circuit (NCP3520 (1.2 V)Version Shown)NRCS1.3 VVS / VFB1.2 V EN 3 V 0 V V O * 0.35Shirt Circuit is DetectedOutput Falls Out of RegulationOutput Turns OffStarting Up Into a Short CircuitIf the NCP3520/NCP3521 turns on and has not gone into a normal mode of operation, additional time has been added to the NRCS to ignore potential false short circuit confirmation during in −rush current events. This time is independent of the external capacitor value and is typically 50 m s. The voltage on NRCS operates as a normal condition until it reaches 1 V . The current source charging NRCS turns off for 50 m s disallowing the voltage to rise on NRCS. After 50 m s the current source turns back on and continues to charge the NRCS capacitor. Once 1.3 V is reached, the circuit operates as during a typical short circuit event.Shirt Circuit Decision TimerFigure 15. Starting Up Into a Short Circuit (NCP3520(1.2 V) Version Shown)Undervoltage LockoutV CC and V D detection is provided in conjunction with the EN input pin. When all three conditions are met (V CC is up,V D is up, and EN is high), the Non Rush Current on Startup (NRCS) circuitry is allowed to start. Any one of the three conditions failing will not allow the device to turn on.The V CC undervoltage threshold is 4.35 V and the V D threshold is V O * 0.7.EnableThe Enable function is controlled by the logic pin EN. The threshold of this pin is set to TTL logic levels. TTL logic levels are 0.8 V (low) and 2.0 V (high). A low on the EN pin puts the device is a low current sleep mode consuming less than 10 m A (I VCC ). A device going from normal operation to sleep will 1st go through a discharge mode maintaining a discharge current of 220 mA on V S (measured @ V S = 1 V).This pin has 60 mV (typ) of hysteresis to guarantee a clean switching threshold.External ComponentsA capacitor between V O and ground is required for stability. A 220 m F value capacitor such as the SANYO 2R5TPE220MF is recommended. The SANYO 2R5TPE220MF capacitor has a 15 m W maximum specification. Contact resistance and board trace resistance are the significant contributors to output capacitor ESR below 10 m W .As ON Semiconductor’s NCP352X family of LDO controllers may be considered as an alternative to Rohm’s family of LDO controllers, alternative FETs such as industry compatible parts like the Si4866DY may also be used in conjunction with ON Semiconductor’s controller.Thermal ShutdownWhen the die temperature exceeds the Thermal Shutdown threshold, a Thermal Shutdown (TSD) event is detected and V G is turned off. The IC will remain in this state until the die temperature moves below the shutdown threshold (180°C typical) minus the hysteresis factor (15°C typical). The output will then go through a soft startup using the NRCS circuitry.ORDERING INFORMATIONDevice Package Shipping†NCP3520DMR2G Micro8(Pb−Free)4000 / Tape & ReelNCP3521DMR2G Micro8(Pb−Free)4000 / Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.PACKAGE DIMENSIONSMicro8t CASE 846A −02ISSUE GNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.846A−01 OBSOLETE, NEW STANDARD 846A−02.STYLE 2:PIN 1.SOURCE 1 2.GATE 1 3.SOURCE 2 4.GATE 2 5.DRAIN 2 6.DRAIN 2 7.DRAIN 1 8.DRAIN 1*For additional information on our Pb −Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*8XDIM A MIN NOM MAX MIN MILLIMETERS−−−− 1.10−−INCHES A10.050.080.150.002b 0.250.330.400.010c 0.130.180.230.005D 2.90 3.00 3.100.114E 2.90 3.00 3.100.114e 0.65 BSCL 0.400.550.700.016−−0.0430.0030.0060.0130.0160.0070.0090.1180.1220.1180.1220.026 BSC0.0210.028NOM MAX 4.75 4.90 5.050.1870.1930.199H E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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