Design of Signal Windows in High Throughput Screening Assays for Drug Discovery

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AD9696超高速比较器

The AD9696 and AD9698 are both available as commercial temperature range devices operating from ambient temperatures of 0°C to +70°C, and as extended temperature range devices for ambient temperatures from –55°C to +125°C. Both versions are available qualified to MIL-STD-883 class B.
DIGITAL OUTPUTS Logic “1” Voltage (Source 4 mA) Logic “0” Voltage (Sink 10 mA)
SWITCHING PERFORMANCE Propagation Delay (tPD)5 Input to Output HIGH Input to Output LOW Latch Enable to Output HIGH Latch Enable to Output LOW Delta Delay Between Outputs Propagation Delay Dispersion 20 mV to 100 mV Overdrive 100 mV to 1.0 V Overdrive Rise Time10 Fall Time10 Latch Enable Pulse Width [tPW(E)] Setup Time (tS) Hold Time (tH)
Input Offset Current
Input Capacitance Input Voltage Range

电力中英文词汇对照

abrasion-Proof component of burner 燃烧器耐磨件arm-brace 撑脚ash conditoner 调灰器basket removal panel 元件盒检修护板BDV blow down valve 疏水阀，排污阀blind 堵板blind flange 法兰堵板/盲板法兰（盖calling 催交campell diagram 叶片埃贝尔曲线dado 墙裙daily service fuel tank level switch 日用油缸液位掣damage 损毁damper 挡板damper linkage 风闸联动装置damper motor 风闸马达damping mat 阻尼垫dangerous earth potential 危险性对地电势dashpot 减震器data transmission 数据传输DC/AC converter 直流电／交流电转换器dead 不带电dead weight 自重decanter 沉淀分取器declaration of conformity 符合标准声明decommissioning 解除运作；停止运作decompression chamber 减压室decorative lighting 装饰照明；灯饰deep bore well pump 深钻井泵defect liability period 故障修理责任期；保用期defectograph 钢缆探伤仪；故障检查仪defence in depth 纵深防御definite sequence 固定次序deflection 偏转；挠度deflector sheave 折向轮；导向轮defrost timer 防霜时间掣defrost unit 溶雪组合dehumidifier 抽湿机deleterious substance 有害物质delivery and return air temperature 送风及回风温度delivery connection 出油接头delivery pressure 输出压力demand side management 用电需求管理demand side management agreement 用电需求管理协议demand side management programme 用电需求管理计划dent 凹痕dental instrument 牙科仪器dental scaler 洗牙具Departmental Administration Division [Electrical and Mechanical Services Department] 行政部〔机电工程署〕Departmental Safety Unit [Electrical and Mechanical Services Department] 部门安全组〔机电工程署〕deposition 沉积物depth measuring facility 深度测量装置derating factor 额定值降低因子derust 除锈descale 清除氧化皮design current 设计电流design parameter 设计参数designated employee 指定雇员detachable grip 可拆除的夹扣Details of Branch Offices of Registered Electrical Contractors 注册电业承办商分行详情申报deterioration 变质；变坏Deutsche Industrie Normen [DIN] 德国工业标准device 器件；装置dewatering 脱水；排水diaphragm 膜片；隔板dielectric strength test 电介质强度测试diesel fuel tank 柴油燃料缸diesel oil 柴油differential gasket 差速器衬垫differential lock 差速器锁differential oil 差速器机油diffuser 透光罩；扩散器dilute 稀释dim sum trolley 点心手推车dim transformer 光暗变压器diminution of value 减值dimmer 调光器；光暗掣；光暗器dip tube 液位探测管Diploma in Electrical Engineering 电机工程学文凭dipstick 量油尺direct current [DC] 直流电direct current control 直流控制direct current electric drive 直流电电力驱动direct current reactor 直流电抗器direct drive 直接驱动direct purging 直接驱气direct-acting lift 直接驱动升降机direct-fired vaporizer 明火直热式汽化器direction arrow 方向箭头direction arrow plate 方向指示板direction indicator 方向指示器Director of Electrical and Mechanical Services 机电工程署署长Directory of Accredited Laboratories 认可实验所名册Directory of Quality System Registration Bodies 品质系统注册团体指南disassemble 拆散discharge 放电；卸载discharge lamp 放电灯；放电管discharge lighting 放电照明设施discharge of electricity 释电；放电discharge valve 排水阀disciplinary board 纪律审裁委员会disciplinary board panel 纪律审裁委员团disciplinary tribunal 纪律审裁小组disciplinary tribunal panel 纪律审裁委员团；纪律审裁委员会discolouring 变色disconnection 截断；截离steam hamerring analysis 汽锤分析steam packing unloading valve 汽封卸载阀steam purity 蒸汽纯度steam seal diverting valve 汽封分流阀steam seal feed valve 汽封给水阀steam water mixture 汽水混合物steel bar 扁钢steel supporting 钢支架steel wire brush 钢丝轮steel works 钢结构step load change 负荷阶跃still air 蒸馏气体stirrup 镫形夹stoikiometric ratio 化学当量比stopper 制动器、塞子storage vessell 贮水箱stppage alarm 停转报警stranded copper cable 铜绞线电缆strength 强度strong backs 支撑stud bolt 柱头螺栓、双头螺栓sub cooling line 欠热管submerged arc welding 埋弧焊substation 配电装置substation island 电气岛superficial corrosion 表面腐蚀superheat 过热度supersaturation 过饱和supervisory instrument 监测装置supply transformer 供电变压器support trunnion 支撑端轴surfactant 表面活性剂surge 喘振suspended diode 中断二极管suspended particles 悬浮颗粒switch board 开关柜switch gear 开关柜sychronization 并网sychroscope 同步指示器、同步示波器T square 丁字尺T/G transformer 发变组tackling system 起吊系统tamped/compacted backfill 夯实回填土tanks and accessories 箱罐和附件taper land thrust bearing 斜面式推力轴承tar epoxy paint 柏油环氧漆tarpaulin 防水布temperature digital display meter 温度数显表tensile test 拉伸试验tension test 拉伸试验，张力试验tensioning rod 拉杆terminal box 接线盒terminal poit 接口termination flange 接口法兰tertiary air 三次风test connection 试验接头test permition 试验合格the expansion coordinate system 热膨胀系统theodilite\transit instrument 经纬仪thermal insulatiion for tuebine casing 汽缸保温thermo resistor 热电阻thermostat 恒温器、恒温调节器thinner 稀释剂threaded flange 螺纹法兰throudh type 直通式、穿入式through bolt 贯穿螺栓、双头螺栓thrust plate 推力板tier tube 间隔管tilting pad 可倾瓦块tilting pad bearing 可倾瓦块轴承tip shroud 围带、环形叶栅外柱面tip speed 叶顶速度toe board/plate (kick plate) 踢脚板top crown plate seal 高冠板式密封装置top girder 顶板top penthouse 顶部雨棚top plan view 俯视图torquemeter 扭矩测量仪totalnumber of welding 焊口总数trajectory 轨道、轨迹transducer board 变送器屏transfer pipe 引出管transition piece 过渡连接件transtion piece 过渡段transverse strength 弯曲强度、抗挠强度transverse stress 横向应力、弯曲应力transverse test 抗弯试验trapezoid corrugated plate seperater 梯形波形板分离器、顶帽travelling crab 小车起重机travelling hoist 移动卷扬机tread width 踏步宽度trestle 组合支架trim and grind the welding 修磨焊点trisector air preheater 三分仓空预器trunk cable pair 主电缆对trunnion air seal assembly 端轴空气密封tube exchanger 管式热交换器tubing stress analysis 管系应力分析turbidity analyser 浊度分析仪turbine lube oil and conditioning system 汽机润滑油及净化系统turning oil 循环油twisted pair conveyer 双绞线传送器undercut 坡口underflow 地流、潜流、下溢union 活接头、管节unit control 单元控制unloadding spout vent fan 卸料口通风风机unloading valve 卸载阀urgent need equipment 急需设备urgtented need equipment 急需设备u-shape hanger chains u形曲链片吊挂装置UT ultrasonic testing 超声波探伤UTS ultimate tensible strength 极限抗拉强度vacuum belt filter 皮带真空吸滤器valve opening chart at load rejection 甩负荷阀门开启阀valve seat body seat 阀座valve spindle 阀轴、阀杆valve stem 阀杆vapor proof 防水灯variable inlet guide vane centrifugal fan 进口可调导叶离心式风机variable moning blade axial flow fan 动叶可调轴流式风机variable moving blade double stage axial fan 动叶可调双级轴流式风机variable speed driver 变速马达variables 变量vent capacity 排放量vent line 放气管ventilator valve 通风阀vernier caliper 游标卡尺vertical deflection 垂直挠度vertical movement 垂直位移vertical spindle coal pulveriser 立式磨煤机vibration isolation 隔振装置viewing lamp 观察指示灯viscosity 粘滞度、内摩擦viscous fluid 粘性液体visual examination of coating 外观质量vlve body 阀体void 无效volatily 挥发分voltage class 电压等级vortex gasket 涡流垫片wall type and retractable soot blower 墙式、伸缩式吹灰器warm air curtain 热风幕rwarming line 加热管water balance 水平衡water induction prevent control 防进水控制water level gauge 水位计water stop flange 止水法兰water supply facility island 水工岛wear hardness 可抗磨能力wear template 防磨板wearing bush 防磨套wearing plate 防磨板、护板weigh feeder 重量计量进料器weld bolt 焊接螺栓weld contamination 焊接杂质weld groove 焊缝坡口weld pass 焊道weld penetration 熔深weld preparation 焊缝坡口加工weld with shop beveled ends 工厂加工坡口焊接welder helment 面罩welding line 焊缝welding plate flange 焊接板式法兰welding rod 焊条welding rods dryer barrel 焊条保温筒welding run 焊道welding seam 对接焊缝welding technological properties 焊接工艺性能welding tool 电焊钳welding torch 焊枪welding wire 焊丝welds counting quantity 焊口统计数量wellington boot 防水长统靴whirl plate 折流板wide column 宽立柱winding resistance 绕组电阻wire feed speed 送丝速度wire netting/metal mesh 铁丝网wire wool 擦洗用的）钢丝绒，百洁丝withstand voltage test 耐压试验working medium 工质worm hole （焊缝）条虫状气孔yield strength 屈服强度yoke 磁轭、人孔压板、座架联板firproof paint 防火漆manifold valve 汇集阀saw trace 锯痕tapping point 取样点bushing current transformer 套管式电流互感器light gauge plate/sheet 薄钢板notch 槽口、凹口holding strip 压板straight edge 校正装置trailing edge 后缘lance 喷枪lighting off 点火gaseous fuel 气体燃料entrain 夹带、传输combustion air 助燃风hot stand by 热备用行波travelling wave模糊神经网络fuzzy-neural network神经网络neural network模糊控制fuzzy control研究方向 research direction副教授associate professor电力系统the electrical power system大容量发电机组large capacity generating set输电距离electricity transmission超高压输电线supervltage transmission power line投运commissioning行波保护Traveling wave protection自适应控制方法adaptive control process 动作速度speed of action行波信号travelling wave signal测量信号measurement signal暂态分量transient state component非线性系统nonlinear system高精度high accuracy自学习功能selflearning function抗干扰能力antijamming capability自适应系统adaptive system行波继电器travelling wave relay输电线路故障transmission line malfunction仿真simulation算法algorithm电位electric potential短路故障short trouble子系统subsystem大小相等，方向相反equal and opposite in direction电压源voltage source故障点trouble spot等效于equivalent暂态行波transient state travelling wave 偏移量side-play mount电压electric voltage附加系统add-ons system波形waveform工频power frequency延迟变换delayed transformation延迟时间delay time减法运算subtraction相减运算additive operation 求和器summator模糊规则fuzzy rule参数值parameter values可靠动作action message等值波阻抗equivalent value wave impedance附加网络additional network修改的modified反传算法backpropagation algorithm隶属函数membership function模糊规则fuzzy rule模糊推理fuzzy reasoning样本集合 sample set给定的given模糊推理矩阵fuzzy reasoning matrix采样周期sampling period三角形隶属度函数Triangle-shape grade of membership function负荷状态load conditions区内故障troubles inside the sample space 门槛值threshold level采样频率sampling frequency全面地all sidedly样本空间sample space误动作malfunction保护特性protection feature仿真数据simulation data灵敏性sensitivity小波变换wavelet transformation神经元neuron谐波电流harmonic current电力系统自动化power system automation 继电保护relaying protection中国电力 China Power学报 journal初探primary exploration标准的机组数据显示 (Standard Measurement And Display Data)负载电流百分比显示 Percentage of Current load(%)单相/三相电压 Voltage by One/Three Phase (Volt.)每相电流 Current by Phase (AMP)千伏安 Apparent Power (KVA)中线电流 Neutral Current (N Amp)功率因数 Power Factor (PF)频率 Frequency(HZ)千瓦 Active Power (KW)千阀 Reactive Power (KVAr)最高/低电压及电流 Max/Min. Current and Voltage输出千瓦/兆瓦小时 Output kWh/MWh运行转速 Running RPM机组运行正常 Normal Running超速故障停机 Overspeed Shutdowns低油压故障停机 Low Oil Pressure Shutdowns高水温故障停机 High Coolant Temperature Shutdowns起动失败停机 Fail to Start Shutdowns冷却水温度表 Coolant Temperature Gauge机油油压表 Oil Pressure Gauge电瓶电压表 Battery Voltage Meter机组运行小时表 Genset Running Hour Meter怠速-快速运行选择键 Idle Run – Normal Run Selector Switch 运行-停机-摇控启动选择键 LocalRun-Stop-Remote Starting Selector Switch其它故障显示及输入 Other Common Fault Alarm Display and。

Native Instruments MASCHINE MK3 用户手册说明书

The information in this document is subject to change without notice and does not represent a commitment on the part of Native Instruments GmbH. The software described by this docu-ment is subject to a License Agreement and may not be copied to other media. No part of this publication may be copied, reproduced or otherwise transmitted or recorded, for any purpose, without prior written permission by Native Instruments GmbH, hereinafter referred to as Native Instruments.“Native Instruments”, “NI” and associated logos are (registered) trademarks of Native Instru-ments GmbH.ASIO, VST, HALion and Cubase are registered trademarks of Steinberg Media Technologies GmbH.All other product and company names are trademarks™ or registered® trademarks of their re-spective holders. Use of them does not imply any affiliation with or endorsement by them.Document authored by: David Gover and Nico Sidi.Software version: 2.8 (02/2019)Hardware version: MASCHINE MK3Special thanks to the Beta Test Team, who were invaluable not just in tracking down bugs, but in making this a better product.NATIVE INSTRUMENTS GmbH Schlesische Str. 29-30D-10997 Berlin Germanywww.native-instruments.de NATIVE INSTRUMENTS North America, Inc. 6725 Sunset Boulevard5th FloorLos Angeles, CA 90028USANATIVE INSTRUMENTS K.K.YO Building 3FJingumae 6-7-15, Shibuya-ku, Tokyo 150-0001Japanwww.native-instruments.co.jp NATIVE INSTRUMENTS UK Limited 18 Phipp StreetLondon EC2A 4NUUKNATIVE INSTRUMENTS FRANCE SARL 113 Rue Saint-Maur75011 ParisFrance SHENZHEN NATIVE INSTRUMENTS COMPANY Limited 5F, Shenzhen Zimao Center111 Taizi Road, Nanshan District, Shenzhen, GuangdongChina© NATIVE INSTRUMENTS GmbH, 2019. All rights reserved.Table of Contents1Welcome to MASCHINE (25)1.1MASCHINE Documentation (26)1.2Document Conventions (27)1.3New Features in MASCHINE 2.8 (29)1.4New Features in MASCHINE 2.7.10 (31)1.5New Features in MASCHINE 2.7.8 (31)1.6New Features in MASCHINE 2.7.7 (32)1.7New Features in MASCHINE 2.7.4 (33)1.8New Features in MASCHINE 2.7.3 (36)2Quick Reference (38)2.1Using Your Controller (38)2.1.1Controller Modes and Mode Pinning (38)2.1.2Controlling the Software Views from Your Controller (40)2.2MASCHINE Project Overview (43)2.2.1Sound Content (44)2.2.2Arrangement (45)2.3MASCHINE Hardware Overview (48)2.3.1MASCHINE Hardware Overview (48)2.3.1.1Control Section (50)2.3.1.2Edit Section (53)2.3.1.3Performance Section (54)2.3.1.4Group Section (56)2.3.1.5Transport Section (56)2.3.1.6Pad Section (58)2.3.1.7Rear Panel (63)2.4MASCHINE Software Overview (65)2.4.1Header (66)2.4.2Browser (68)2.4.3Arranger (70)2.4.4Control Area (73)2.4.5Pattern Editor (74)3Basic Concepts (76)3.1Important Names and Concepts (76)3.2Adjusting the MASCHINE User Interface (79)3.2.1Adjusting the Size of the Interface (79)3.2.2Switching between Ideas View and Song View (80)3.2.3Showing/Hiding the Browser (81)3.2.4Showing/Hiding the Control Lane (81)3.3Common Operations (82)3.3.1Using the 4-Directional Push Encoder (82)3.3.2Pinning a Mode on the Controller (83)3.3.3Adjusting Volume, Swing, and Tempo (84)3.3.4Undo/Redo (87)3.3.5List Overlay for Selectors (89)3.3.6Zoom and Scroll Overlays (90)3.3.7Focusing on a Group or a Sound (91)3.3.8Switching Between the Master, Group, and Sound Level (96)3.3.9Navigating Channel Properties, Plug-ins, and Parameter Pages in the Control Area.973.3.9.1Extended Navigate Mode on Your Controller (102)3.3.10Navigating the Software Using the Controller (105)3.3.11Using Two or More Hardware Controllers (106)3.3.12Touch Auto-Write Option (108)3.4Native Kontrol Standard (110)3.5Stand-Alone and Plug-in Mode (111)3.5.1Differences between Stand-Alone and Plug-in Mode (112)3.5.2Switching Instances (113)3.5.3Controlling Various Instances with Different Controllers (114)3.6Host Integration (114)3.6.1Setting up Host Integration (115)3.6.1.1Setting up Ableton Live (macOS) (115)3.6.1.2Setting up Ableton Live (Windows) (116)3.6.1.3Setting up Apple Logic Pro X (116)3.6.2Integration with Ableton Live (117)3.6.3Integration with Apple Logic Pro X (119)3.7Preferences (120)3.7.1Preferences – General Page (121)3.7.2Preferences – Audio Page (126)3.7.3Preferences – MIDI Page (130)3.7.4Preferences – Default Page (133)3.7.5Preferences – Library Page (137)3.7.6Preferences – Plug-ins Page (145)3.7.7Preferences – Hardware Page (150)3.7.8Preferences – Colors Page (154)3.8Integrating MASCHINE into a MIDI Setup (156)3.8.1Connecting External MIDI Equipment (156)3.8.2Sync to External MIDI Clock (157)3.8.3Send MIDI Clock (158)3.9Syncing MASCHINE using Ableton Link (159)3.9.1Connecting to a Network (159)3.9.2Joining and Leaving a Link Session (159)3.10Using a Pedal with the MASCHINE Controller (160)3.11File Management on the MASCHINE Controller (161)4Browser (163)4.1Browser Basics (163)4.1.1The MASCHINE Library (163)4.1.2Browsing the Library vs. Browsing Your Hard Disks (164)4.2Searching and Loading Files from the Library (165)4.2.1Overview of the Library Pane (165)4.2.2Selecting or Loading a Product and Selecting a Bank from the Browser (170)4.2.2.1[MK3] Browsing by Product Category Using the Controller (174)4.2.2.2[MK3] Browsing by Product Vendor Using the Controller (174)4.2.3Selecting a Product Category, a Product, a Bank, and a Sub-Bank (175)4.2.3.1Selecting a Product Category, a Product, a Bank, and a Sub-Bank on theController (179)4.2.4Selecting a File Type (180)4.2.5Choosing Between Factory and User Content (181)4.2.6Selecting Type and Character Tags (182)4.2.7List and Tag Overlays in the Browser (186)4.2.8Performing a Text Search (188)4.2.9Loading a File from the Result List (188)4.3Additional Browsing Tools (193)4.3.1Loading the Selected Files Automatically (193)4.3.2Auditioning Instrument Presets (195)4.3.3Auditioning Samples (196)4.3.4Loading Groups with Patterns (197)4.3.5Loading Groups with Routing (198)4.3.6Displaying File Information (198)4.4Using Favorites in the Browser (199)4.5Editing the Files’ Tags and Properties (203)4.5.1Attribute Editor Basics (203)4.5.2The Bank Page (205)4.5.3The Types and Characters Pages (205)4.5.4The Properties Page (208)4.6Loading and Importing Files from Your File System (209)4.6.1Overview of the FILES Pane (209)4.6.2Using Favorites (211)4.6.3Using the Location Bar (212)4.6.4Navigating to Recent Locations (213)4.6.5Using the Result List (214)4.6.6Importing Files to the MASCHINE Library (217)4.7Locating Missing Samples (219)4.8Using Quick Browse (221)5Managing Sounds, Groups, and Your Project (225)5.1Overview of the Sounds, Groups, and Master (225)5.1.1The Sound, Group, and Master Channels (226)5.1.2Similarities and Differences in Handling Sounds and Groups (227)5.1.3Selecting Multiple Sounds or Groups (228)5.2Managing Sounds (233)5.2.1Loading Sounds (235)5.2.2Pre-listening to Sounds (236)5.2.3Renaming Sound Slots (237)5.2.4Changing the Sound’s Color (237)5.2.5Saving Sounds (239)5.2.6Copying and Pasting Sounds (241)5.2.7Moving Sounds (244)5.2.8Resetting Sound Slots (245)5.3Managing Groups (247)5.3.1Creating Groups (248)5.3.2Loading Groups (249)5.3.3Renaming Groups (251)5.3.4Changing the Group’s Color (251)5.3.5Saving Groups (253)5.3.6Copying and Pasting Groups (255)5.3.7Reordering Groups (258)5.3.8Deleting Groups (259)5.4Exporting MASCHINE Objects and Audio (260)5.4.1Saving a Group with its Samples (261)5.4.2Saving a Project with its Samples (262)5.4.3Exporting Audio (264)5.5Importing Third-Party File Formats (270)5.5.1Loading REX Files into Sound Slots (270)5.5.2Importing MPC Programs to Groups (271)6Playing on the Controller (275)6.1Adjusting the Pads (275)6.1.1The Pad View in the Software (275)6.1.2Choosing a Pad Input Mode (277)6.1.3Adjusting the Base Key (280)6.1.4Using Choke Groups (282)6.1.5Using Link Groups (284)6.2Adjusting the Key, Choke, and Link Parameters for Multiple Sounds (286)6.3Playing Tools (287)6.3.1Mute and Solo (288)6.3.2Choke All Notes (292)6.3.3Groove (293)6.3.4Level, Tempo, Tune, and Groove Shortcuts on Your Controller (295)6.3.5Tap Tempo (299)6.4Performance Features (300)6.4.1Overview of the Perform Features (300)6.4.2Selecting a Scale and Creating Chords (303)6.4.3Scale and Chord Parameters (303)6.4.4Creating Arpeggios and Repeated Notes (316)6.4.5Swing on Note Repeat / Arp Output (321)6.5Using Lock Snapshots (322)6.5.1Creating a Lock Snapshot (322)6.5.2Using Extended Lock (323)6.5.3Updating a Lock Snapshot (323)6.5.4Recalling a Lock Snapshot (324)6.5.5Morphing Between Lock Snapshots (324)6.5.6Deleting a Lock Snapshot (325)6.5.7Triggering Lock Snapshots via MIDI (326)6.6Using the Smart Strip (327)6.6.1Pitch Mode (328)6.6.2Modulation Mode (328)6.6.3Perform Mode (328)6.6.4Notes Mode (329)7Working with Plug-ins (330)7.1Plug-in Overview (330)7.1.1Plug-in Basics (330)7.1.2First Plug-in Slot of Sounds: Choosing the Sound’s Role (334)7.1.3Loading, Removing, and Replacing a Plug-in (335)7.1.3.1Browser Plug-in Slot Selection (341)7.1.4Adjusting the Plug-in Parameters (344)7.1.5Bypassing Plug-in Slots (344)7.1.6Using Side-Chain (346)7.1.7Moving Plug-ins (346)7.1.8Alternative: the Plug-in Strip (348)7.1.9Saving and Recalling Plug-in Presets (348)7.1.9.1Saving Plug-in Presets (349)7.1.9.2Recalling Plug-in Presets (350)7.1.9.3Removing a Default Plug-in Preset (351)7.2The Sampler Plug-in (352)7.2.1Page 1: Voice Settings / Engine (354)7.2.2Page 2: Pitch / Envelope (356)7.2.3Page 3: FX / Filter (359)7.2.4Page 4: Modulation (361)7.2.5Page 5: LFO (363)7.2.6Page 6: Velocity / Modwheel (365)7.3Using Native Instruments and External Plug-ins (367)7.3.1Opening/Closing Plug-in Windows (367)7.3.2Using the VST/AU Plug-in Parameters (370)7.3.3Setting Up Your Own Parameter Pages (371)7.3.4Using VST/AU Plug-in Presets (376)7.3.5Multiple-Output Plug-ins and Multitimbral Plug-ins (378)8Using the Audio Plug-in (380)8.1Loading a Loop into the Audio Plug-in (384)8.2Editing Audio in the Audio Plug-in (385)8.3Using Loop Mode (386)8.4Using Gate Mode (388)9Using the Drumsynths (390)9.1Drumsynths – General Handling (391)9.1.1Engines: Many Different Drums per Drumsynth (391)9.1.2Common Parameter Organization (391)9.1.3Shared Parameters (394)9.1.4Various Velocity Responses (394)9.1.5Pitch Range, Tuning, and MIDI Notes (394)9.2The Kicks (395)9.2.1Kick – Sub (397)9.2.2Kick – Tronic (399)9.2.3Kick – Dusty (402)9.2.4Kick – Grit (403)9.2.5Kick – Rasper (406)9.2.6Kick – Snappy (407)9.2.7Kick – Bold (409)9.2.8Kick – Maple (411)9.2.9Kick – Push (412)9.3The Snares (414)9.3.1Snare – Volt (416)9.3.2Snare – Bit (418)9.3.3Snare – Pow (420)9.3.4Snare – Sharp (421)9.3.5Snare – Airy (423)9.3.6Snare – Vintage (425)9.3.7Snare – Chrome (427)9.3.8Snare – Iron (429)9.3.9Snare – Clap (431)9.3.10Snare – Breaker (433)9.4The Hi-hats (435)9.4.1Hi-hat – Silver (436)9.4.2Hi-hat – Circuit (438)9.4.3Hi-hat – Memory (440)9.4.4Hi-hat – Hybrid (442)9.4.5Creating a Pattern with Closed and Open Hi-hats (444)9.5The Toms (445)9.5.1Tom – Tronic (447)9.5.2Tom – Fractal (449)9.5.3Tom – Floor (453)9.5.4Tom – High (455)9.6The Percussions (456)9.6.1Percussion – Fractal (458)9.6.2Percussion – Kettle (461)9.6.3Percussion – Shaker (463)9.7The Cymbals (467)9.7.1Cymbal – Crash (469)9.7.2Cymbal – Ride (471)10Using the Bass Synth (474)10.1Bass Synth – General Handling (475)10.1.1Parameter Organization (475)10.1.2Bass Synth Parameters (477)11Working with Patterns (479)11.1Pattern Basics (479)11.1.1Pattern Editor Overview (480)11.1.2Navigating the Event Area (486)11.1.3Following the Playback Position in the Pattern (488)11.1.4Jumping to Another Playback Position in the Pattern (489)11.1.5Group View and Keyboard View (491)11.1.6Adjusting the Arrange Grid and the Pattern Length (493)11.1.7Adjusting the Step Grid and the Nudge Grid (497)11.2Recording Patterns in Real Time (501)11.2.1Recording Your Patterns Live (501)11.2.2The Record Prepare Mode (504)11.2.3Using the Metronome (505)11.2.4Recording with Count-in (506)11.2.5Quantizing while Recording (508)11.3Recording Patterns with the Step Sequencer (508)11.3.1Step Mode Basics (508)11.3.2Editing Events in Step Mode (511)11.3.3Recording Modulation in Step Mode (513)11.4Editing Events (514)11.4.1Editing Events with the Mouse: an Overview (514)11.4.2Creating Events/Notes (517)11.4.3Selecting Events/Notes (518)11.4.4Editing Selected Events/Notes (526)11.4.5Deleting Events/Notes (532)11.4.6Cut, Copy, and Paste Events/Notes (535)11.4.7Quantizing Events/Notes (538)11.4.8Quantization While Playing (540)11.4.9Doubling a Pattern (541)11.4.10Adding Variation to Patterns (541)11.5Recording and Editing Modulation (546)11.5.1Which Parameters Are Modulatable? (547)11.5.2Recording Modulation (548)11.5.3Creating and Editing Modulation in the Control Lane (550)11.6Creating MIDI Tracks from Scratch in MASCHINE (555)11.7Managing Patterns (557)11.7.1The Pattern Manager and Pattern Mode (558)11.7.2Selecting Patterns and Pattern Banks (560)11.7.3Creating Patterns (563)11.7.4Deleting Patterns (565)11.7.5Creating and Deleting Pattern Banks (566)11.7.6Naming Patterns (568)11.7.7Changing the Pattern’s Color (570)11.7.8Duplicating, Copying, and Pasting Patterns (571)11.7.9Moving Patterns (574)11.7.10Adjusting Pattern Length in Fine Increments (575)11.8Importing/Exporting Audio and MIDI to/from Patterns (576)11.8.1Exporting Audio from Patterns (576)11.8.2Exporting MIDI from Patterns (577)11.8.3Importing MIDI to Patterns (580)12Audio Routing, Remote Control, and Macro Controls (589)12.1Audio Routing in MASCHINE (590)12.1.1Sending External Audio to Sounds (591)12.1.2Configuring the Main Output of Sounds and Groups (596)12.1.3Setting Up Auxiliary Outputs for Sounds and Groups (601)12.1.4Configuring the Master and Cue Outputs of MASCHINE (605)12.1.5Mono Audio Inputs (610)12.1.5.1Configuring External Inputs for Sounds in Mix View (611)12.2Using MIDI Control and Host Automation (614)12.2.1Triggering Sounds via MIDI Notes (615)12.2.2Triggering Scenes via MIDI (622)12.2.3Controlling Parameters via MIDI and Host Automation (623)12.2.4Selecting VST/AU Plug-in Presets via MIDI Program Change (631)12.2.5Sending MIDI from Sounds (632)12.3Creating Custom Sets of Parameters with the Macro Controls (636)12.3.1Macro Control Overview (637)12.3.2Assigning Macro Controls Using the Software (638)12.3.3Assigning Macro Controls Using the Controller (644)13Controlling Your Mix (646)13.1Mix View Basics (646)13.1.1Switching between Arrange View and Mix View (646)13.1.2Mix View Elements (647)13.2The Mixer (649)13.2.1Displaying Groups vs. Displaying Sounds (650)13.2.2Adjusting the Mixer Layout (652)13.2.3Selecting Channel Strips (653)13.2.4Managing Your Channels in the Mixer (654)13.2.5Adjusting Settings in the Channel Strips (656)13.2.6Using the Cue Bus (660)13.3The Plug-in Chain (662)13.4The Plug-in Strip (663)13.4.1The Plug-in Header (665)13.4.2Panels for Drumsynths and Internal Effects (667)13.4.3Panel for the Sampler (668)13.4.4Custom Panels for Native Instruments Plug-ins (671)13.4.5Undocking a Plug-in Panel (Native Instruments and External Plug-ins Only) (675)13.5Controlling Your Mix from the Controller (677)13.5.1Navigating Your Channels in Mix Mode (678)13.5.2Adjusting the Level and Pan in Mix Mode (679)13.5.3Mute and Solo in Mix Mode (680)13.5.4Plug-in Icons in Mix Mode (680)14Using Effects (681)14.1Applying Effects to a Sound, a Group or the Master (681)14.1.1Adding an Effect (681)14.1.2Other Operations on Effects (690)14.1.3Using the Side-Chain Input (692)14.2Applying Effects to External Audio (695)14.2.1Step 1: Configure MASCHINE Audio Inputs (695)14.2.2Step 2: Set up a Sound to Receive the External Input (698)14.2.3Step 3: Load an Effect to Process an Input (700)14.3Creating a Send Effect (701)14.3.1Step 1: Set Up a Sound or Group as Send Effect (702)14.3.2Step 2: Route Audio to the Send Effect (706)14.3.3 A Few Notes on Send Effects (708)14.4Creating Multi-Effects (709)15Effect Reference (712)15.1Dynamics (713)15.1.1Compressor (713)15.1.2Gate (717)15.1.3Transient Master (721)15.1.4Limiter (723)15.1.5Maximizer (727)15.2Filtering Effects (730)15.2.1EQ (730)15.2.2Filter (733)15.2.3Cabinet (737)15.3Modulation Effects (738)15.3.1Chorus (738)15.3.2Flanger (740)15.3.3FM (742)15.3.4Freq Shifter (743)15.3.5Phaser (745)15.4Spatial and Reverb Effects (747)15.4.1Ice (747)15.4.2Metaverb (749)15.4.3Reflex (750)15.4.4Reverb (Legacy) (752)15.4.5Reverb (754)15.4.5.1Reverb Room (754)15.4.5.2Reverb Hall (757)15.4.5.3Plate Reverb (760)15.5Delays (762)15.5.1Beat Delay (762)15.5.2Grain Delay (765)15.5.3Grain Stretch (767)15.5.4Resochord (769)15.6Distortion Effects (771)15.6.1Distortion (771)15.6.2Lofi (774)15.6.3Saturator (775)15.7Perform FX (779)15.7.1Filter (780)15.7.2Flanger (782)15.7.3Burst Echo (785)15.7.4Reso Echo (787)15.7.5Ring (790)15.7.6Stutter (792)15.7.7Tremolo (795)15.7.8Scratcher (798)16Working with the Arranger (801)16.1Arranger Basics (801)16.1.1Navigating Song View (804)16.1.2Following the Playback Position in Your Project (806)16.1.3Performing with Scenes and Sections using the Pads (807)16.2Using Ideas View (811)16.2.1Scene Overview (811)16.2.2Creating Scenes (813)16.2.3Assigning and Removing Patterns (813)16.2.4Selecting Scenes (817)16.2.5Deleting Scenes (818)16.2.6Creating and Deleting Scene Banks (820)16.2.7Clearing Scenes (820)16.2.8Duplicating Scenes (821)16.2.9Reordering Scenes (822)16.2.10Making Scenes Unique (824)16.2.11Appending Scenes to Arrangement (825)16.2.12Naming Scenes (826)16.2.13Changing the Color of a Scene (827)16.3Using Song View (828)16.3.1Section Management Overview (828)16.3.2Creating Sections (833)16.3.3Assigning a Scene to a Section (834)16.3.4Selecting Sections and Section Banks (835)16.3.5Reorganizing Sections (839)16.3.6Adjusting the Length of a Section (840)16.3.6.1Adjusting the Length of a Section Using the Software (841)16.3.6.2Adjusting the Length of a Section Using the Controller (843)16.3.7Clearing a Pattern in Song View (843)16.3.8Duplicating Sections (844)16.3.8.1Making Sections Unique (845)16.3.9Removing Sections (846)16.3.10Renaming Scenes (848)16.3.11Clearing Sections (849)16.3.12Creating and Deleting Section Banks (850)16.3.13Working with Patterns in Song view (850)16.3.13.1Creating a Pattern in Song View (850)16.3.13.2Selecting a Pattern in Song View (850)16.3.13.3Clearing a Pattern in Song View (851)16.3.13.4Renaming a Pattern in Song View (851)16.3.13.5Coloring a Pattern in Song View (851)16.3.13.6Removing a Pattern in Song View (852)16.3.13.7Duplicating a Pattern in Song View (852)16.3.14Enabling Auto Length (852)16.3.15Looping (853)16.3.15.1Setting the Loop Range in the Software (854)16.4Playing with Sections (855)16.4.1Jumping to another Playback Position in Your Project (855)16.5Triggering Sections or Scenes via MIDI (856)16.6The Arrange Grid (858)16.7Quick Grid (860)17Sampling and Sample Mapping (862)17.1Opening the Sample Editor (862)17.2Recording Audio (863)17.2.1Opening the Record Page (863)17.2.2Selecting the Source and the Recording Mode (865)17.2.3Arming, Starting, and Stopping the Recording (868)17.2.5Using the Footswitch for Recording Audio (871)17.2.6Checking Your Recordings (872)17.2.7Location and Name of Your Recorded Samples (876)17.3Editing a Sample (876)17.3.1Using the Edit Page (877)17.3.2Audio Editing Functions (882)17.4Slicing a Sample (890)17.4.1Opening the Slice Page (891)17.4.2Adjusting the Slicing Settings (893)17.4.3Live Slicing (898)17.4.3.1Live Slicing Using the Controller (898)17.4.3.2Delete All Slices (899)17.4.4Manually Adjusting Your Slices (899)17.4.5Applying the Slicing (906)17.5Mapping Samples to Zones (912)17.5.1Opening the Zone Page (912)17.5.2Zone Page Overview (913)17.5.3Selecting and Managing Zones in the Zone List (915)17.5.4Selecting and Editing Zones in the Map View (920)17.5.5Editing Zones in the Sample View (924)17.5.6Adjusting the Zone Settings (927)17.5.7Adding Samples to the Sample Map (934)18Appendix: Tips for Playing Live (937)18.1Preparations (937)18.1.1Focus on the Hardware (937)18.1.2Customize the Pads of the Hardware (937)18.1.3Check Your CPU Power Before Playing (937)18.1.4Name and Color Your Groups, Patterns, Sounds and Scenes (938)18.1.5Consider Using a Limiter on Your Master (938)18.1.6Hook Up Your Other Gear and Sync It with MIDI Clock (938)18.1.7Improvise (938)18.2Basic Techniques (938)18.2.1Use Mute and Solo (938)18.2.2Use Scene Mode and Tweak the Loop Range (939)18.2.3Create Variations of Your Drum Patterns in the Step Sequencer (939)18.2.4Use Note Repeat (939)18.2.5Set Up Your Own Multi-effect Groups and Automate Them (939)18.3Special Tricks (940)18.3.1Changing Pattern Length for Variation (940)18.3.2Using Loops to Cycle Through Samples (940)18.3.3Using Loops to Cycle Through Samples (940)18.3.4Load Long Audio Files and Play with the Start Point (940)19Troubleshooting (941)19.1Knowledge Base (941)19.2Technical Support (941)19.3Registration Support (942)19.4User Forum (942)20Glossary (943)Index (951)1Welcome to MASCHINEThank you for buying MASCHINE!MASCHINE is a groove production studio that implements the familiar working style of classi-cal groove boxes along with the advantages of a computer based system. MASCHINE is ideal for making music live, as well as in the studio. It’s the hands-on aspect of a dedicated instru-ment, the MASCHINE hardware controller, united with the advanced editing features of the MASCHINE software.Creating beats is often not very intuitive with a computer, but using the MASCHINE hardware controller to do it makes it easy and fun. You can tap in freely with the pads or use Note Re-peat to jam along. Alternatively, build your beats using the step sequencer just as in classic drum machines.Patterns can be intuitively combined and rearranged on the fly to form larger ideas. You can try out several different versions of a song without ever having to stop the music.Since you can integrate it into any sequencer that supports VST, AU, or AAX plug-ins, you can reap the benefits in almost any software setup, or use it as a stand-alone application. You can sample your own material, slice loops and rearrange them easily.However, MASCHINE is a lot more than an ordinary groovebox or sampler: it comes with an inspiring 7-gigabyte library, and a sophisticated, yet easy to use tag-based Browser to give you instant access to the sounds you are looking for.What’s more, MASCHINE provides lots of options for manipulating your sounds via internal ef-fects and other sound-shaping possibilities. You can also control external MIDI hardware and 3rd-party software with the MASCHINE hardware controller, while customizing the functions of the pads, knobs and buttons according to your needs utilizing the included Controller Editor application. We hope you enjoy this fantastic instrument as much as we do. Now let’s get go-ing!—The MASCHINE team at Native Instruments.MASCHINE Documentation1.1MASCHINE DocumentationNative Instruments provide many information sources regarding MASCHINE. The main docu-ments should be read in the following sequence:1.MASCHINE Getting Started: This document provides a practical approach to MASCHINE viaa set of tutorials covering easy and more advanced tasks in order to help you familiarizeyourself with MASCHINE.2.MASCHINE Manual (this document): The MASCHINE Manual provides you with a compre-hensive description of all MASCHINE software and hardware features.Additional documentation sources provide you with details on more specific topics:▪Controller Editor Manual: Besides using your MASCHINE hardware controller together withits dedicated MASCHINE software, you can also use it as a powerful and highly versatileMIDI controller to pilot any other MIDI-capable application or device. This is made possibleby the Controller Editor software, an application that allows you to precisely define all MIDIassignments for your MASCHINE controller. The Controller Editor was installed during theMASCHINE installation procedure. For more information on this, please refer to the Con-troller Editor Manual available as a PDF file via the Help menu of Controller Editor.▪Online Support Videos: You can find a number of support videos on The Official Native In-struments Support Channel under the following URL: https:///NIsupport-EN. We recommend that you follow along with these instructions while the respective ap-plication is running on your computer.Other Online Resources:If you are experiencing problems related to your Native Instruments product that the supplied documentation does not cover, there are several ways of getting help:▪Knowledge Base▪User Forum▪Technical Support▪Registration SupportYou will find more information on these subjects in the chapter Troubleshooting.1.2Document ConventionsThis section introduces you to the signage and text highlighting used in this manual. This man-ual uses particular formatting to point out special facts and to warn you of potential issues. The icons introducing these notes let you see what kind of information is to be expected:This document uses particular formatting to point out special facts and to warn you of poten-tial issues. The icons introducing the following notes let you see what kind of information can be expected:Furthermore, the following formatting is used:▪Text appearing in (drop-down) menus (such as Open…, Save as… etc.) in the software and paths to locations on your hard disk or other storage devices is printed in italics.▪Text appearing elsewhere (labels of buttons, controls, text next to checkboxes etc.) in the software is printed in blue. Whenever you see this formatting applied, you will find the same text appearing somewhere on the screen.▪Text appearing on the displays of the controller is printed in light grey. Whenever you see this formatting applied, you will find the same text on a controller display.▪Text appearing on labels of the hardware controller is printed in orange. Whenever you see this formatting applied, you will find the same text on the controller.▪Important names and concepts are printed in bold.▪References to keys on your computer’s keyboard you’ll find put in square brackets (e.g.,“Press [Shift] + [Enter]”).►Single instructions are introduced by this play button type arrow.→Results of actions are introduced by this smaller arrow.Naming ConventionThroughout the documentation we will refer to MASCHINE controller (or just controller) as the hardware controller and MASCHINE software as the software installed on your computer.The term “effect” will sometimes be abbreviated as “FX” when referring to elements in the MA-SCHINE software and hardware. These terms have the same meaning.Button Combinations and Shortcuts on Your ControllerMost instructions will use the “+” sign to indicate buttons (or buttons and pads) that must be pressed simultaneously, starting with the button indicated first. E.g., an instruction such as:“Press SHIFT + PLAY”means:1.Press and hold SHIFT.2.While holding SHIFT, press PLAY and release it.3.Release SHIFT.Unlabeled Buttons on the ControllerThe buttons and knobs above and below the displays on your MASCHINE controller do not have labels.。

SRAM 设计介绍2007

Static Read Access Memory (SRAM) DesignAbhinandan Majumdar MS. Computer Engineering am2993@Srinivas Satish MS. Computer Engineering ssn2111@December 10, 2007Final ProjectEE 4321VLSI Circuits Prof. Azeez BhavnagarwalaI DEX1.I TRODUCTIO (1)1.1 Design (1)1.2 SRAM Operation (2)1.3 Applications and Uses (3)2.DESIG (5)2.1 Block Diagram (5)2.2 Decoder (6)2.2.1 2 Input And Gate Design (7)2.2.2 3 Input And Gate Design (11)2.2.3 3x8 Decoder (13)2.2.4 6x64 Decoder (14)2.2.5 Decoder Resizing (15)2.3 SRAM Cell and Array Design (17)2.3.1 Precharge Circuitry (17)2.3.2 SRAM Cell (18)2.3.3 Read Sensing Circuit (19)2.3.4 Write Driver (19)2.3.5 SRAM Array (20)2.3.6 SRAM Cell with Decoder (20)2.3.7 Read Stability (21)2.4 DC Simulation (22)2.4.1 Static Noise Margin (SNM) (21)2.4.2 Cell Read Current (23)2.4.3 Effect of Threshold Voltage (V t) (24)YOUT (27)3.1 Decoder (27)3.1.1 AND2 Gate (27)3.1.2 AND3 Gate (28)3.1.3 3x8 Decoder (29)3.1.4 6x64 Decoder (29)3.2 SRAM (30)3.2.1 Precharge (30)3.2.2 Read Sensing Circuit (31)3.2.3 SRAM 64x64 Array (32)4.RESULTS (35)4.1 Simulation Results (35)4.1.1 Simulation of One SRAM Cell (35)4.1.2 Simulation of 64x64 SRAM Array (36)4.2 DRC & LVS Results (37)5.CO CLUSIO (38)6.REFERE CES (39)1.I TRODUCTIOStatic random access memory (SRAM) is a type of semiconductor memory. The word "static" indicates that the memory retains its contents as long as power remains applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed.DesignFig 1.1 A six-transistor CMOS SRAM cell.Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. It thus typically takes six MOSFETs to store one memory bit.Access to the cell is enabled by the word line (WL in figure) which controls the two access transistors M5 and M6 which, in turn, control whether the cell should be connected to the bit lines: BL and BL’. They are used to transfer data for both read and write operations. While it's not strictly necessary to have two bit lines, both the signal and its inverse are typically provided since it improves noise margins.During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell. This improves SRAM speed compared to DRAMs—in a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwardsor downwards. The symmetric structure of SRAMs also allows for differential signaling, which makes small voltage swings more easily detectable. Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time. By comparison, commodity DRAMs have the address multiplexed in two halves, i.e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.The size of an SRAM with m address lines and n data lines is 2m words, or 2m × n bits.1.2. SRAM operationA SRAM cell has three different states it can be in: standby where the circuit is idle, reading when the data has been requested and writing when updating the contents. The three different states work as follows:a) StandbyIf the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines. The two cross coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are disconnected from the outside world.b) ReadingAssume that the content of the memory is a 1, stored at Q. The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors. The second step occurs when the values stored in Q and Q are transferred to the bit lines by leaving BL at its precharged value and discharging BL through M1 and M5 to a logical 0. On the BL side, the transistors M4 and M6 pull the bit line toward VDD, a logical 1. If the content of the memory was a 0, the opposite would happen and BL would be pulled toward 1 and BL toward 0.c) WritingThe start of a write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to a SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. Note that the reason this works is that the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself, so that they can easily override the previous state of the cross-coupledinverters. Careful sizing of the transistors in a SRAM cell is needed to ensure proper operation.1.3. Applications and Usesa) CharacteristicsSRAM is a little more expensive, but faster and significantly less power hungry (especially idle) than DRAM. It is therefore used where either speed or low power, or both, are of prime interest. SRAM is also easier to control (interface to) and generally more truly random access than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main memory in personal computers.b) Clock speed and powerThe power consumption of SRAM varies widely depending on how frequently it is accessed; it can be as power-hungry as dynamic RAM, when used at high frequencies, and some ICs can consume many watts at full speed. On the other hand, static RAM used at a somewhat slower pace, such as in applications with moderately clocked microprocessors, draw very little power and can have a nearly negligible power consumption when sitting idle — in the region of a few microwatts.Static RAM exists primarily as:(i) General purpose products•with asynchronous interface, such as the 28 pin 32Kx8 chips (usually named XXC256), and similar products up to 16 Mb per chip•with synchronous interface, usually used for caches and other applications requiring burst transfers, up to 18 Mb (256Kx72) per chip(ii) Integrated on chip•as RAM or cache memory in microcontrollers (usually from around 32 bytes up to 128 kilobytes)•as the primary caches in powerful microprocessors, such as the x86 family, and many others (from 8 KB, up to several megabytes)•on application specific ICs, or ASICs (usually in the order of kilobytes)•in FPGAs and CPLDs (usually in the order of a few kilobytes or less)c) Uses(i) Embedded UseMany categories of industrial and scientific subsystems, automotive electronics, and similar, contains static RAM. Some amounts (kilobytes or less) is also embedded in practically all modern appliances, toys, etc that implements an electronic user interface. Several megabytes may be used in complex products such as digital cameras, cell phones, synthesizers, etc. SRAM in its dual-ported form is sometimes used for realtime digital signal processing circuits.(ii)In computersSRAM is also used in personal computers, workstations, routers and peripheral equipment: internal CPU caches and external burst mode SRAM caches, hard disk buffers, router buffers, etc. LCD screens and printers also normally employ static RAM to hold the image displayed (or to be printed). Small SRAM buffers are also found in CDROM and CDRW drives; usually 256 KB or more are used to buffer track data, which is transferred in blocks instead of as single values. The same applies to cable modems and similar equipment connected to computers. The so called "CMOS RAM" on PC motherboards was originally a battery-powered SRAM chip, but is today more often implemented using EEPROM or Flash.2.DESIG2.1 Block DiagramThere are two major blocks to be designed:•Address decoder: The address decoder takes in the 6 address lines a4:0 coming from the latch, and decodes them to generate 64 wordlines WL0-63 for the SRAM array.•SRAM array: Consists of an array of 64 x 64 bit SRAM cells. In addition to these blocks, the array also contains circuitry that allows data to be written intothe array, and for precharging the bitlines to V DD before the read operation; these circuits are not shown in figure.2.2 DECODERTo construct a 64x64 bit SRAM, we need 6x64 Address Decoder to select one of the word lines of 64 rows, each containing 64 1b SRAM cells. Hence we need to make the decoder logic fastest so as it doesn’t become the bottleneck of our whole design. Hence considering speed and layout issues, we are taking up Domino Logic for all the intermediate nodes being used.For designing a 6x64 Decoder, we can either have three 2x4 decoders in 1st stage and perform ANDING of the corresponding outputs to have a 6x64 decoder logic, or we can have two 3x8. But for the former case, we need 64 three input AND gate and 12 two input AND gate and which is designed through domino logic, while the later design has 64 two input AND gates and 16 three input AND gate, hence considering the space limitations as three input AND gate takes much more area and offer higher gate capacitance, we choose the later design for 6x64 decoder.Fig 2.2: 6x64 Decoder using 2x4 decodersFig 2.2: 6x64 Decoder design using two 3x8 decoders2.2.1 2 Input A D Gate Design – We designed 2 Input AND gate using DominoLogic. Here is the schematic of the designFig 2.3: Schematic Design of AND2 Gatei)Frequency Calculation. We kept input A & B at 1.2V, and saw how fast canit be operated at higher frequency, and we found that it atleast needs 0.4ns or2.5Ghz.Fig 2.4: Frequency Variation for AND2 Gateii)PFET size calculation. We tried to simulate for varying Pfet size and found that we need to keep pfet minimal as well as optimum to charge the bitline faster at a given frequency of 2.5Ghz. We decided upon pfet size to be 715nm so as precharges at a faster rate.Fig 2.5: Pfet width variation for AND2 Gateiii)Sizing of nfets – We try to scale the nfet array so as the propagation delay could be minimized. Increasing the scaling decreases the propagation delay, hence decided upon a = 1.3Fig 2.6: NFET Size variation for NFETiv)Keeper PFET sizing – Keeper PFET is the one whose gate is driven by the output of the inverter, and prevents the voltage drop across the intermediate capacitance to drop below the V M of the inverter during evaluation stage. First graph is that of clock. Second graph shows that if we don’t have any pfet, the output voltage rises by mV. If we connect it to a pfet and increase its size by b*(sum of the width of nfet array), we see the outout to be stable at 0 and randomness decreases by increase in b. Hence we find b = 0.15.Fig 2.7: Keeper PFET sizing for AND2 gatev)Inverter Sizing. Though we should make the nfet stronger than pfet so as the voltage drop across intermediate capacitance is greater than VM of inveter.But making nfet stronger adds delay, so by adding a Keeper Pfet so as to keep the intermediate capacitance charged, we can increase our pfet to have same rise and fall time. Hence we find the beta ratio to be 2.45.Fig 2.8: Inverter size variation for AND2 Gate2.2.2 3 I PUT A D GATE. The ratios which we got for 2 INPUT AND Gate arekept same for 3 INPUT too, but the confusion should we use 2 cascadedAND2 gate for a 3 Input AND or single 3 INPUT AND. Hence we computedthe propagation delay, and found following things. AND2_1 and AND2_2 iscascade 2 AND with changing line in 1st and 2nd AND respectively.Gate High to Low Low to High PropagationDelayAND2 0 1.15ns 0.575nsAND2_1 (cascaded) 0 1.18ns 0.59nsAND2_2 (cascaded) 0 1.19ns 0.595nsAND3 0 1.46ns 0.73nsHence cascaded AND2 would make our design faster but could make it asymmetrical, hence we chose AND3.AND2 (Only one 2 Input AND) AND2_1 (Cascaded 2 Input AND)AND2_2 (Cascaded 2 Input AND) AND3 (3 Input AND)2.2.33x8 DECODER – Here is the schematic for the Decoder.Fig 2.9: 3x8 Decoder SchematicAnd, here is the simulation graph,Fig 2.10: Simulation of 3x8 Decoder2.2.46x64 Decoder – We used two 3x8 decoders and used 2 AND for having the64x6 decoder logic. Here is the schematicFig 2.11: Schematic of 6x64 DecoderWe kept all inputs A1-A5 at 0 and sweeped A0 from 0 to 1.2V, and saw that Y0 dropping out and Y1 rising to 1.2V.Fig 2.12: Propagation Delay at the Critical Path for 6x64 Decoder2.2.5Decoder Resizing.The delay what we got after designing was 5.177ns – 5.025ns = 0.152ns when running at 1Ghz and driving a capacitance of 39.931fF. We computed the end capacitance having the value of gate capacitance as 1fF/um and width capacitance as0.2fF/um. In this case the AND3 nfets have W1 = 1u and rest being size by the ratio1.3, inveter nfet has W2 = 1um, AND2 nfets have W3 = 1u and sized accordingly with ratio 1.3 and inverter has W4 = 1um.To have minimal delay so as to have equal rise time and fall time, we optimized the sizes as follows,For AND3,NFET Array: 2u, 2.6u, 3.38u, 4.395uPFET: 3uKeeper PFET: 800nmInverter: NFET – 3uPFET – 2.9uFor AND2,NFET Array: 5.8u, 7.54u, 9.8uPFET: 3.2uKeeper PFET: 2.2uInverter: NFET – 3uPFET – 2.9uHere’s the critical pathFig 2.13: Schematic of Critical Path in 6x64 DecoderWe obtained a fall and rise time for the four stages as follows 33.94ps, 34,94ps, 33.23ps, 34.99ps. By this, our propagation delay got reduced from 152ps to 89ps (1.594ns – 1.505ns = 89ps). Hence we stick to this sizes.Fig 2.14: Propagation of Critical Path in 6x64 Decoder after Optimization2.3 SRAM cell and array design2.3.1 Precharge circuitryThe schematic of the precharge circuit is shown below. The pfet are of 1um width. This large width of the pfet is required to be able to charge the bitline quickly during the pre-charge phase. The huge width ensures that the bit-line BIT and BIT_B are charged to VDD in half the clock cycle.Fig 2.15: Schematic of Precharge Circuit2.3.2SRAM Cell.Schematic of the cell is shown below. The sizes of the access transistors, inverternfet, pfet widths are as per the ones given in the layout.Fig 2.16: Schematic of SRAM Cell2.3.3 Read Sense CircuitSchematic of the read large sense circuit is shown below. The basic NAND gate is sized with nfet=280nm and pfet width of 560nm a ratio of 4.8:1. This is the required ratio in the 90nm process with channel length=80nm for achieving ideal rise and fall times.Fig 2.17: Schematic of Read Sense Circuit2.3.4 Write driverThe write driver is enabled by a Write_enable line. The schematic is shown below.Fig 2.18: Schematic of Write Circuit2.3.5 The complete SRAM ArrayFollowing is the schematic of 64x64 bit SRAM cellFig 2.19: Schematic of SRAM Array2.3.6 SRAM Array with DecoderHere is the schematic of the complete SRAM with DECODER,Fig 2.20: Schematic of SRAM Array with 6X64 Decoder2.3.7 Read StabilityThis is an important characteristic of the SRAM Cell. During a read-operation one of the bitlines either BIT or BIT_B is discharged though the access transistor and an nfet of the inverter. During this discharge process, a large amount of current flows through node A ( shown below). Read stability is a measure of the potential at node A, this potential should not exceed the switching threshold of the other inverter. If it does then the state of the SRAM has changed. An analogous analysis was done in identifying tradeoffs in Read Current and Static Noise Margin.Following is the READ STABILITY Graph.Fig 2.21: Simulation of Read Stability2.4DC SIMULATIO2.4.1STATIC OISE MARGIHere is the schematic of the SRAM for Static Noise Margin Measurement. We sweep the left voltage and measure the right voltage and do vice versa and find the min edge of the max box that can fit into the butterfly curve.Fig 2.22: Schematic of SRAM Array with 6X64 Decoder(i)HOLD operation. We keep the gate of the pass transistors at GND and getthe following curve. The SNM for this is 0.4604.Fig 2.23: Hold operation(ii)READ - The SNM we got was 0.1616V. The graph is as follows.Fig 2.24: Static Noise Margin estimation of SRAM Cell2.4.2Cell Read CurrentCell read current equals the current that flows through the pass gate nfet connected to the BL draining charge on the BL into the cell ground terminal. The larger the current the faster BL gets discharged and develops a signal for the sensing circuit to detect. Having a very large Read Current flowing through the discharge path from bit line to the ground could result in the exceeding the read stability threshold. This can be avoided by optimally choosing the sizing of the access nfet and the discharge nfet of the respective inverted during a read operation cycle.Fig 2.25: Cell Read Current Simulation2.4.3 Effect of Threshold Voltage (V t )We change Vt by 25mV, 50mV, 100mV and 200mV by adding a –ve voltage to the gate and got following values. Vt Pass nfet Pull down nfet Pfet 25mV 0.1638 0.1626 0.1518 50mV 0.1725 0.1655 0.1483 100mV 0.1900 0.1732 0.1422 200mV 0.2246 0.1778 0.1252Fig 2.26 - Effect of SNM by increasing V t at pass nfetFig 2.27- Effect of SNM on increasing V t at pull down nfetFig 2.28- Effect of increasing V t at one end of pfet and measuring other side.YOUT3.1 DECODER3.1.1 A D2 Gate.Here is the layout of AND2 gate which passes both DRC and LVSFig 3.1- DRC and LVS results for AND2 Gate along with layout.3.1.2 A D3 Gate.Here is the layout of AND3 gate which passes both DRC and LVSFig 3.2- DRC and LVS results for AND3 Gate along with layout.3.1.3 3x8 DECODERHere is the layout of 3x8 Decoder which passes both DRC and LVSFig 3.3- DRC and LVS results for 3x8 Decoder along with layout.3.1.4 6x64 DECODERHere is the layout of 3x8 Decoder which passes both DRC and LVSFig 3.4- DRC and LVS results for 6x64 Decoder along with layout.3.2 SRAM3.2.1 Precharge circuit layoutThe width of the entire precharge circuit layout should be equal to the width between the two bit lines BIT and BIT_B. Below is an image of our layout of this circuit with its DRC and LVS results.Fig 3.5- DRC and LVS results for Precharge Circuit along with layout3.2.2Read Sense Amp CircuitIn the layout of the read circuit, care has to be taken to ensure that it fits exactly in between the two bitlines. The symmetric lateral reflection layout of the SRAM cells adds some degree of complexity, this being due to the fact that now we would have a series of BIT, BIT_B, BIT_B, BIT followed by the same pattern. For a read it is sufficient to sense one of the bit lines, either BIT or BIT_B. Two read sense amps would have to be fit between the two BIT lines. The LVS results and the layout of the Read Sense amp can be found in the image below.Fig 3.6 DRC and LVS results for Read Sense Amplifier along with layout3.2.3SRAM 64 X 64 arrayUsing the SRAM Cell provided from the standard library, we created a symmetrical and laterally inverted 2 X 2 network of SRAM cells. This was done to achieve a good sharing of the power rails and to reduce the bit line noise reduction. Though not done in our layout cross coupling bit lines would reduce the bit line noise to a very good extent.Using an instance of 2 X 2 SRAM cells the entire array of 64 X 32 top half and 64 X 32 bottom halves as shown in the schematic of phase two was laid out. Following this is the insertion of the Read Sense Amplifiers in between the top half and bottom halves of theentire SRAM array layout. To the left of the image below is the layout of the 2 X 2 network of SRAM cells and to the right the 64 X 64 layout of SRAM cells.Fig 3.7- Array of SRAM Cells, 2 X 2 and 64 X 64 arrays.Image below shows the DRC test results:Fig 3.8: DRC results for the 64 X 64 SRAM arrayHere’s the complete layout of SRAM cell with decoder.Fig 3.9: 64 X 64 SRAM array along with 6x64 Decoder4.RESULTS4.1 Simulation Results4.1.1 Simulation for One Cell SRAMWe simulated a single cell SRAM with following schematicFig 4.1 – One Cell SRAM SchematicBelow is a graph showing the Write – 1 Read – 1 Write – 0 simulation on a single SRAM cell.Fig 4.2 – One Cell SRAM Simulation4.1.2Simulation for 64x64 bit SRAM ArrayHere is the schematic used for 64x64 bit SRAM ArrayFig 4.3 –64x64 SRAM Arrayand here are the simulation results, when din<0> = 1, din<1> = 0, and din<2> = 1 with address line as 000000, and clock running at 1 Ghz.Fig 4.4 – Simulation for complete 64x64 SRAM cell Array4.2 DRC and LVS ResultsThe DRC and LVS were checked for each component individually. The following is a summary of the results:Functional Component DRC LVS6 X 64 Decoder Passed PassedPrecharge Passed PassedRead Sense Amp Passed Passed64 X 64 SRAM array Errors ErrorsPlease find all reports to these tests at the following location on/home/user5/fall07/ssn2111/LVS_FinalReports/home/user5/fall07/ssn2111/DRC_FinalReports5.CO CLUSIOAs a SRAM project for EE 4321 VLSI course, we designed 64x64 bit SRAM cell both at the schematic and layout level. We attempted to design the 6x64 decoder using 3x8 decoder using two and three input AND gates using Domino Logic. We could successfully simulate and verify the functionality of the components which we targeted to design. Though we couldn’t successfully pass the DRC and LVS of entire unit because of the primary reason that the unit cell being provided to us failed at DRC and LVS level, but we could successfully pass the DRC and LVS of other individual components including Pre-Charge, Read Sensing Circuit and 6x64 Decoder.The experience on working for such a design oriented project gave us a thorough insight what all critical issues we need to consider while designing a simple unit. This also made us familiar with the different approaches to implement the same design and decide what the tradeoffs between different alternatives are. Also, it made us aware of the critical physical implementation issues which we not only have to consider during actual layout but also during schematic level design. It also gave a hand-on experience upon CAD tools like Cadence, Virtuoso, Spice and Spectre widely used both at industrial and academic level for circuit designing. Overall, it was a nice experience both at learning, practicing and designing a most critical part of processor unit widely used in any Computer Architecture.6.REFERE CES1./wiki/Static_random_access_memory2.Cmos Logic – Uyemura3.CMOS VLSI Design – Weste & Harris4.Static-Noise Margin Analysis of CMOS SRAM Cells EVERT SEEVINCK,SENIOR MEMBER, IEEE, FRANS J. LIST, AND JAN LOHSTROH, MEMBER, IEEE.5.Analyzing Static Noise Margin for Subthreshold SRAM in 65nm CMOS BentonH. Calhoun and Anantha Chandrakasan6.Transistor Sizing for Reliable Domino Logic Design in Dual Threshold VoltageTechnologies by Seong-Ook Jung, Ki-Wook Kim, Sung-Mo (Steve) Kang。

Quartus_II_Simulation

Introduction to Simulationof Verilog DesignsII14.11IntroductionAn effective way of determining the correctness of a logic circuit is to simulate its behavior.This tutorial provides an introduction to such simulation using Altera’s Quartus II CAD system.The simulation method used in this tutorial is based on drawing waveforms,similar to timing diagrams,that are inputs for a simulator tool.The outputs of the simulator are also in the form of waveforms.This tutorial is intended for students who are taking a course in logic circuit design.We show how to use the Simulation Waveform Editor tool provided in the Quartus II software to perform a simulation of a circuit speciﬁed in Verilog HDL.Only a very basic understanding of Verilog is needed for this purpose.Contents:•Design Project•Creating Waveforms for Simulation•Simulation•Making Changes and Resimulating•Concluding Remarks1 Altera Corporation-University ProgramDecember2014The Simulation Waveform Editor tool is available for use with Altera’s Quartus II software version13.0or later.It allows the user to apply inputs to the designed circuit,usually referred to as test vectors,in the form of waveforms and to observe the outputs generated in response.In this tutorial,the reader will learn about:•Test vectors needed to test the designed circuit•Using the Simulation Waveform Editor tool to draw test vector waveforms•Functional simulation,which is used to verify the functional correctness of a synthesized circuit•Timing simulation,which is used to verify the timing of signals in a synthesized circuitThis tutorial is aimed at the reader who wishes to simulate circuits deﬁned by using the Verilog hardware description language.An equivalent tutorial is available for the user who prefers the VHDL language.2Design ProjectTo illustrate the simulation process,we will use a very simple logic circuit that implements the majority function of three inputs,x1,x2and x3.The circuit is deﬁned by the expressionf(x1,x2,x3)=x1x2+x1x3+x2x3In Verilog,this circuit can be speciﬁed as follows:module majority3(x1,x2,x3,f);input x1,x2,x3;output f;assign f=(x1&x2)|(x1&x3)|(x2&x3);endmoduleThe desired circuit has to be implemented in a Quartus II project.To do so,create a new directory(folder)for the Quartus II project;in this tutorial we call the folder simulation_intro.Enter the Verilog code for the majority3module into aﬁle called majority3.v in the project directory.Then,create a Quartus II project and call it majority3.For the project choose as the target device any FPGA chip of your choosing;for example,select the EP4CE115F29C7, which is the device on the Altera DE2-115board,or the5CSEMA5F31C6,which is the device on the DE1-SoC board.2Altera Corporation-University ProgramDecember20143Creating Waveforms for SimulationTo create test vectors for your design,select File>New...>Veriﬁcation/Debugging Files>University Program VWF in the Quartus II window where the design project is open.This opens the Simulation Waveform Editor tool, shown in Figure1,which allows you to specify the desired input waveforms.Figure1.The Waveform Editor window.For our simple circuit,we can do a complete simulation by applying all eight possible valuations of the input signals x1,x2and x3.The output f should then display the logic values deﬁned by the truth table for the majority function.We will run the simulation for800ns;so,select Edit>Set End Time...in the Waveform Editor and in the pop-up window that will appear specify the time of800ns,and click OK.This will adjust the time scale in the window of Figure1.Before drawing the input waveforms,it is necessary to locate the desired signals in the implemented circuit.In FPGA jargon,the term“node”is used to refer to a signal in a circuit.This could be an input signal(input node), output signal(output node),or an internal signal.For our task,we need toﬁnd the input and output nodes.This is done by using a utility program called the Node Finder.In the Waveform Editor window,select Edit>Insert>Insert Node or Bus....In the pop-up window that appears, which is shown in Figure2,click on Node Finder.3 Altera Corporation-University ProgramDecember2014Figure2.The Insert Node or Bus dialog.The Node Finder window is presented in Figure3.Aﬁlter is used to identify the nodes of interest.In our circuit, we are only interested in the nodes that appear on the pins(i.e.external connections)of the FPGA chip.Hence,the ﬁlter setting should be Pins:all.Click on List,which will display the nodes as indicated in theﬁgure.In a large circuit there could be many nodes displayed.We need to select the nodes that we wish to observe in the simulation. This is done by highlighting the desired nodes and clicking on the>button.Select the nodes labeled x1,x2,x3,and f,which will lead to the image in Figure4.Click OK in this window and also upon return to the window in Figure2. This returns to the Waveform Editor window,with the selected signals included as presented in Figure5.Figure3.The Node Finder dialog.4Altera Corporation-University ProgramDecember2014Figure4.The selected signals.Observe that in Figure5all input signals are at logic level0.The output,f is shown as undeﬁned.Next,we have to draw the input waveforms.Then,we will simulate the circuit,which will produce the output waveform.To make it easier to draw the input waveforms,the Waveform Editor displays dashed grid lines.The spacing of the grid lines can be adjusted by selecting Edit>Grid Size...,and in the pop-up box in Figure6specifying the desired size.The spacing of grid lines in Figure5is20ns.Another convenience in drawing is to have transitions of a waveform snap on grid lines.This feature is activated by clicking on the Snap to Grid icon,or by selecting the command Edit>Snap to Grid.Figure5.Signals in the Waveform Editor window.Altera Corporation-University Program5 December2014Figure6.Specifying the grid spacing.Input waveforms can be drawn in different ways.The most straightforward way is to indicate a speciﬁc time range and specify the value of a signal.To illustrate this approach,click the mouse on the x1waveform near the400-ns point and then drag the mouse to the800-ns point.The selected time interval will be highlighted in blue,as depicted in Figure7.Change the value of the waveform to1by clicking on the Forcing High(1)icon,as illustrated in Figure8.Figure7.Selection of a time interval.6Altera Corporation-University ProgramDecember2014Figure8.Drawing the waveform for x1In creating the waveform for x1,we used the icon to implement the logic value1.Another possibility is to invert the value of the signal in a selected time interval by using the Invert icon.We will use this approach to create the waveform for x2,which should change from0to1at200ns,then back to0at400ns,and again to1at600ns. Select the interval from200to400ns and click on the icon.Then do the same for the interval from600to800ns, as illustrated in Figure9.Figure9.Drawing the waveform for x2.We will use a third approach to draw the waveform for x3.This signal should alternate between logic values0and 1at each100-ns interval.Such a regular pattern is indicative of a clock signal that is used in many logic circuits. Even though there is no clock signal in our example circuit,it is convenient to specify x3in this manner.Click on the x3input,which selects the entire800-ns interval.Then,click on the Overwrite Clock icon,as indicated in Figure10.This leads to the pop-up window in Figure11.Specify the clock period of200ns and the duty cycle of7 Altera Corporation-University ProgramDecember201450%,and click OK.The result is depicted in Figure12.Figure10.Drawing the waveform for x3.Figure11.Deﬁning the clock characteristics8Altera Corporation-University ProgramDecember2014Figure12.The completed input waveforms.Save the waveformﬁle using a suitable name;we chose the name majority3.vwf.Note that the sufﬁx vwf stands for vector waveformﬁle.VWFﬁles that are added to the Quartus II project can be accessed at any time in the Project Navigator Widget’s Files tab.4SimulationThe Simulation Waveform Editor performs the simulation by using the simulation tool known as ModelSim.ModelSim-Altera Edition is strongly recommended for use with the Simulation Waveform Editor,as it contains the Altera de-vice libraries necessary for simulations.To use a standard version of ModelSim,the path to its executables must be speciﬁed in the Quartus II software under Tools>Options...>EDA T ool Options.If both ModelSim and ModelSim-Altera are available,the simulator will preferentially use ModelSim-Altera.4.1Functional SimulationNow that we have created the input vector waveform,we can simulate the circuit.In the Simulation WaveformEditor,select Simulation>Run Functional Simulation,or click on the icon.A pop-up window will show the progress of the simulation,then automatically close when it is complete.A second Simulation Waveform Ed-itor window then opens the output waveform,as depicted in Figure13.The output waveform is read-only,so any changes in simulation have to be done by modifying the majority3.vwfﬁle and resimulating the circuit.Observe that the output f is equal to1whenever two or three inputs have the value1,which veriﬁes the correctness of our design.9 Altera Corporation-University ProgramDecember2014Figure13.Result of the functional simulation.4.2Timing SimulationTo observe the actual propogation delays in our circuit,we have to perform a timing simulation.(Note that for FPGA devices with preliminary timing models that the timing simulation results may be the same as functional simulation results.)In the Simulation Waveform Editor,select Simulation>Run Timing Simulation,or click on the icon.A pop-up window will show the progress of the simulation,then automatically close when it is complete.A second Simulation Waveform Editor window then opens the output waveform.The output waveform is read-only,so any changes in simulation have to be done by modifying the majority3.vwfﬁle and resimulating the circuit.The timing simulation shows that there are delays when signals change from one value to another.Figure14shows the waveform,zoomed in at300ns to show the propogation delay between x3and f.The waveform indicates that the maximum delay is approximately6ns.10Altera Corporation-University ProgramDecember2014Figure14.Result of the timing simulation,zoomed in at300ns.5Making Changes and ResimulatingChanges in the input waveforms can be made using the approaches explained above.The circuit can then be resimu-lated using the altered waveforms.For example,change the waveform for x1to have the logic value1in the interval from100to240ns,as indicated in Figure15.Now,simulate the circuit again.The result is given in Figure16.If errors in the circuit are discovered,then these errors can beﬁxed by changing the Verilog code and recompiling the design using the Quartus II software.Figure15.Modiﬁed input waveforms.Figure16.Result of the new simulation.6Concluding RemarksThe purpose of this tutorial is to provide a quick introduction to the Simulation Waveform Editor,explaining only the rudimentary aspects of functional and timing simulations.Details about additional features of the Simulation Waveform Editor can be found in the appendix of this document.To learn about more about simulating circuits using ModelSim,please refer to the tutorials Introduction to Model-Sim’s Graphical Waveform Editor,and Using ModelSim to Simulate Logic Circuits,which are available on Altera’s University Program website.12Altera Corporation-University ProgramA Simulation Waveform EditorIn section3we introduced the Waveform Editor tool,which is used to view and edit waveforms that are used in simulation.Additional features of the Waveform Editor are described in this appendix.A.1Waveform Editor ToolbarThe Waveform Editor window is illustrated in Figure1.The tool includes several commands which can be accessed by using the mouse,including File,Edit,View,Simulation,and Help.Below these commands,as shown in the ﬁgure,there is a toolbar that contains a number of icons which are useful when manipulating waveforms.This toolbar should be visible by default,but if it is not visible,then right-click near the top of the window(below the title bar)and select Waveform Editor in the menu that appears.The toolbar icons are described below.Selection T oolThis tool is used to select waveform intervals and apply changes.To make a selection,click on any part of a waveform and drag the blue box across the desired interval.It’s possible to select multiple waveforms at the same time,as shown in Figure1,or select entire waveform(s)by clicking on its name(s).ing the Selection Tool to select a portion of multiple waveforms.Double clicking the selection tool anywhere on a waveform will select the largest interval with the same value from where the cursor points.Double clicking on a selected interval brings up the window to set arbitrary values for that interval.Zoom T oolThis tool is used to zoom in or zoom out in the waveform display,as indicated in Figure2.Left-clicking zooms into the display and right-clicking zooms out.ing the Zoom Tool.Forcing Unknown(X)This tool allows the selected part of a waveform to be set to the value Unknown(x).An example is given in Figure3,using the majority3function circuit that was described in section2.The value of the signal x3has been set to unknown for theﬁrst half of the simulation.Running the simulation with these input values results in the output waveform f that is shown in theﬁgure.Note that the value of f is unknown between200to400 ns.Figure3.Setting the value of an input to Unknown(X).Forcing Low(0)and Forcing High(1)These tools are used to force the selected part of a waveform to the value low(0)or high(1),as shown in Figures4and5,respectively.14Altera Corporation-University ProgramFigure4.Forcing x1to be low from0to400ns.Figure5.Forcing x1to be high from400to800ns.High Impedance(Z)This tool forces the selected waveform to the value High Impedance(Z),as shown in Figure6.The high impedance value represents a signal that has not been set to any speciﬁc value—that is,an input pin that is not connected.Forcing output waveforms to have high impedance does not affect the output simulation waveforms.Figure6.Setting a signal to high impedance.Weak Low(L)and Weak High(H)These tools are used to set a signal to the values Weak Low(L)or Weak High(H),which represents a circuit in which a bidirectional signal is pulled down or up by using a resistor.Examples are shown in Figures7and 8.Figure7.Changing the x1signal to be weak low from200to400ns.16Altera Corporation-University ProgramFigure8.Changing the x1signal to be weak high from400to600ns.InvertThis tool inverts the value of a selected waveform,as shown in Figure9.Low signals become high,weak low signals become weak high,and vice versa for both cases.The Invert tool has no effect on a signal that is set to high impedance or unknown.Figure9.Inverting the x1signal from100to260ns.Count ValueThis tool allows a waveform to be partitioned into sections,in which the value is incremented by a speciﬁed amount.The Count Value tool can only be applied to a single waveform or a grouped waveform(see sectionB.1).The options that are available when using the Count T ool are illustrated in Figure10.Figure10.Options available for for the Count Value tool.As an example,Figure11shows the3-bit input signal called count set to increment by one every100ns.Figure11.An example of using the Count Value tool.Overwrite ClockThis tool is used to generate a periodic waveform,which is often used as a clock signal.The options available when using the Overwrite Clock tool are shown in Figure12.18Altera Corporation-University ProgramFigure12.Options available for the Overwrite Clock tool.In the example of Figure13,the x3signal has been generated with a period of200ns,an offset of0ns,and a duty cycle of50%.Figure13.An exmaple of using the Overwrite Clock tool.Arbitrary ValueThis tool allows a signal to be set to an arbitrary value,which is particularly useful for specifying the value ofa multibit waveform.The options available when using the Arbitrary Value tool are shown in Figure14.Figure14.Options available for for the Arbitrary Value tool.As an example,in Figure15the count signal is set to three different arbitrary binary values as speciﬁed by theuser.Figure15.The Arbitrary Value tool is used to set values for the count signal.Random ValuesThis tool assigns random values to the selected waveform(s),with several options as shown in Figure16.Figure16.Various options available for the Random Value tool.For example,in Figure17,the signal x1has been given random values.20Altera Corporation-University ProgramFigure17.An example of the Random Value tool being used.Snap to GridThis option allows selections made with the Selection T ool to snap to the light grey grid lines running verti-cally down the waveform display.This option can be toggled on and off by pressing the Snap to Grid button.It is set to on by default.Figure18shows an example of the Selection Tool being used with the Snap to Grid option turned off.Figure18.An example of the Snap to Grid option turned off.Snap to T ransitionThis option allows the Selection Tool to automatically extend a selection to theﬁrst transition encountered on both sides of the selection of one or more waveforms.For example,with the Snap to T ransition option turned on,the Selection Tool rectangle shown in Figure19would be expanded to create the selections illustrated in Figure20.This option can be toggled on and off by pressing the Snap to T ransition button,and is set to off by default.Figure19.Making a selection with the Snap to T ransition option enabled.Figure20.The expanded selection resulting from Figure19.B Using Multibit SignalsThis section describes features of the Simulation Waveform Editor that are useful for dealing with multibit signals.B.1Grouping and Ungrouping SignalsIndividual signals can be grouped together to create a multibit waveform.This is done byﬁrst selecting the desired waveforms by clicking on their names in the leftside of the Waveform Editor with the key Ctrl pressed as indicated in Figure21.Then,as shown in theﬁgure,the grouping of signals is done by right-clicking on the selection and choosing Grouping>Group....22Altera Corporation-University ProgramFigure21.An example of grouping signals.In the options dialogue that opens,illustrated in Figure22,a name must be assigned to the group,as well as a radix.In the example shown,the name count has been chosen with a binary radix.The resulting group of signals is shown in Figure23.The multibit waveform can be expanded in the waveformeditor to display its individual signals.Figure23.An example of expanding a multibit signal.A multibit signal can be ungrouped by right-clicking on the group of signals and selecting Grouping>Ungroup.... It is also possible to create hierarchical groupings of signals as illustrated in Figure24.In this example,the two bit signal called level2is combined with the signal called x3to create the three bit signal called level1.It is only possible to group and ungroup top-level signals.Figure24.An example of hierarchical groups.It is also possible to group input and output signals,as shown in Figure25.24Altera Corporation-University ProgramFigure25.An example of grouping input and output signals.B.2Reverse Group or Bus Bit OrderIn Figure23,the three bit signal count is displayed as the3-tuple x1x2x3.It is possible to reverse the order in which the bits are displayed as illustrated in Figure26.This is done by right-clicking on the name of the multibit signal and selecting Reverse Group or Bus Bit Order,as seen in theﬁgure.Figure26.Reversing the bit order on a group of signals.The effects of the bit reversal can be seen in Figure27.The count waveform is now displayed as the3-tuple x3x2x1.Figure27.The result of reversing the bit order in Figure26.Copyright©2014Altera Corporation.26Altera Corporation-University Program。

PSpice仿真软件使用指南说明书

April 2016© 2013Cadence Design Systems, Inc. All rights reserved.Portions © Apache Software Foundation, Sun Microsystems, Free Software Foundation, Inc., Regents of the University of California, Massachusetts Institute of T echnology, University of Florida. Used by permission. Printed in the United States of America.Cadence Design Systems, Inc. (Cadence), 2655 Seely Ave., San Jose, CA 95134, USA.Product PSpice contains technology licensed from, and copyrighted by: Apache Software Foundation, 1901 Munsey Drive Forest Hill, MD 21050, USA © 2000-2005,Apache Software Foundation. Sun Microsystems, 4150 Network Circle, Santa Clara, CA 95054 USA © 1994-2007, Sun Microsystems, Inc. Free Software Foundation, 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA © 1989, 1991, Free Software Foundation, Inc. Regents of the University of California, Sun Microsystems, Inc., Scriptics Corporation, © 2001, Regents of the University of California. Daniel Stenberg, © 1996 - 2006, Daniel Stenberg. UMFPACK ©2005,TimothyA.Davis,UniversityofFlorida,(**************.edu).KenMartin,WillSchroeder,Bill Lorensen © 1993-2002, Ken Martin, Will Schroeder, Bill Lorensen. Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, Massachusetts, USA © 2003, the Board of Trustees of Massachusetts Institute of Technology. All rights reserved.Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522.Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission.All other trademarks are the property of their respective holders.Restricted Permission: This publication is protected by copyright law and international treaties and contains trade secrets and proprietary information owned by Cadence. Unauthorized reproduction or distribution of this publication, or any portion of it, may result in civil and criminal penalties. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. Unless otherwise agreed to by Cadence in writing, this statement grants Cadence customers permission to print one (1) hard copy of this publication subject to the following conditions:1.The publication may be used only in accordance with a written agreement between Cadence and itscustomer.2.The publication may not be modified in any way.3.Any authorized copy of the publication or portion thereof must include all original copyright,trademark, and other proprietary notices and this permission statement.4.The information contained in this document cannot be used in the development of like products orsoftware, whether for internal or external use, and shall not be used for the benefit of any other party, whether or not for consideration.Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information.Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.ContentsBefore you begin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Welcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 How to use this guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Symbols and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 What this user’s guide covers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PSpice overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Add-on options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PSpice Smoke Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PSpice Advanced Optimizer Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PSpice Advanced Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SLPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 If you don’t have the standard PSpice A/D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Comparison of the different versions of PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 If you have PSpice Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Minimum hardware requirements for running PSpice: . . . . . . . . . . . . . . . . . . . . . . . . 32 PSpice Samples and T utorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Part one: Simulation primer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1Things you need to know . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 What is PSpice? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Analyses you can run with PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Basic analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Advanced multi-run analyses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Analyzing waveforms with PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 What is waveform analysis? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Using PSpice with other programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Using design entry tools to prepare for simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 47What is the PSpice Stimulus Editor? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 What is the PSpice Model Editor? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Files needed for simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Files that design entry tool generates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Other files that you can configure for simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Files that PSpice generates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Directory structure for analog projects in Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 How are files configured at the design level maintained in the directory structure for analog projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 How are files configured at the profile level maintained in the new directory structure for analog projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 What happens when I convert an analog project that uses a design from another project or from another location? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 What should I do if the schematic for a converted analog project uses FILESTIM n parts from the SOURCE library? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Design Entry HDL libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Reference Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Local libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PSpice model libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 The cds.lib file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Encrypting PSpice Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Using PSpiceEnc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Using Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722Simulation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Chapter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Example circuit creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Using Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Using Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Using Design T emplates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Finding out more about setting up your design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Running PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Performing a bias point analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Using the simulation output file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Finding out more about bias point calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99DC sweep analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Setting up and running a DC sweep analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Displaying DC analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Finding out more about DC sweep analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 T ransient analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Finding out more about transient analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 AC sweep analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Setting up and running an AC sweep analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 AC sweep analysis results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Finding out more about AC sweep and noise analysis . . . . . . . . . . . . . . . . . . . . . . . 122 Parametric analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Setting up and running the parametric analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Analyzing waveform families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Finding out more about parametric analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Performance analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Finding out more about performance analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Part two: Design entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383Preparing a design for simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Chapter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Checklist for simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 T ypical simulation setup steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Advanced design entry and simulation setup steps . . . . . . . . . . . . . . . . . . . . . . . . . 141 When netlisting fails or the simulation does not start . . . . . . . . . . . . . . . . . . . . . . . . 142 Using parts that you can simulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Vendor-supplied parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Passive parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Breakout parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Behavioral parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Simulating asymmetric parts in PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Simulating homogenous parts in PSpice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Specifying values for part properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Using global parameters and expressions for values . . . . . . . . . . . . . . . . . . . . . . . . . . 158Global parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Defining power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 For the analog portion of your circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 For A/D interfaces in mixed-signal circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Defining stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Analog stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Digital stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Things to watch for . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Unmodeled parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Unconfigured model, stimulus, or include files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Unmodeled pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Missing ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Missing DC path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854Creating and editing models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Chapter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 What are models? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 How are models organized? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Model libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Model library configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Global vs. design vs. profile models and libraries . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Nested model libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 PSpice-provided models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Model library data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Device characteristic curves-based models vs. Template-based models . . . . . . . . 195 T ools to create and edit models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Ways to create and edit models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Using the Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Ways to use the Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Running the Model Editor alone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Starting the Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Creating models using the Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Creating models based on device characteristic curves . . . . . . . . . . . . . . . . . . . . . 203Creating models based on PSpice templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Importing an existing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Enabling and disabling automatic part creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Running the Model Editor from the schematic editor . . . . . . . . . . . . . . . . . . . . . . . . 215 Model creation examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Example: Creating a PSpice model based on device characteristic curves . . . . . . . 219 Example: Creating template-based PSpice model . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Editing model text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Example: editing a Q2N2222 instance model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Using the Create Subcircuit Format Netlist command (Capture only) . . . . . . . . . . . . . . 237 Changing the model reference to an existing model definition . . . . . . . . . . . . . . . . . . . 239 Reusing instance models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Reusing instance models in the same schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Making instance models available to all designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Configuring model libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 The Configuration Files tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 How PSpice uses model libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Adding model libraries to the configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Changing the model library scope from profile to design, profile to global, design to global and vice versa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Changing model library search order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Changing the library search path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Handling smoke information using the Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Adding smoke information to PSpice models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Creating template-based PSpice models with smoke information . . . . . . . . . . . . . . 256 Using the Model Editor to edit smoke information . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Examples: Smoke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Adding smoke information to the D1 diode model . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Adding smoke information to the OPA_LOCAL operational amplifier model . . . . . . 259 Smoke parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Bipolar Junction Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Magnetic Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Ins Gate Bipolar T ransistor (IGBT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Junction FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Darlington T ransistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2735Creating parts for models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Chapter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 What’s different about parts used for simulation? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Ways to create parts for models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Preparing your models for part creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Starting the Model Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Using the Model Editor to create parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Batch mode of part creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Interactive mode of part creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Creating Design Entry T ool parts for all models in a library . . . . . . . . . . . . . . . . . . . . . . 282 Using batch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Using interactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Setting up automatic part creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Creating parts in the batch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Creating parts using interactive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Basing new parts on a custom set of parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Editing part graphics (Capture only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 How Capture places parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 Defining grid spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Attaching models to parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Defining part properties needed for simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 PSPICETEMPLATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 IO_LEVEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 MNTYMXDL Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 PSPICEDEFAULTNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216Analog behavioral modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Chapter overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Overview of analog behavioral modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 The ABM part library file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Placing and specifying ABM parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Net names and device names in ABM expressions . . . . . . . . . . . . . . . . . . . . . . . . . 326 Forcing the use of a global definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 ABM part templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Control system parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Basic components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Chebyshev filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Integrator and differentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 T able look-up parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Laplace transform part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Math functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 ABM expression parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 An instantaneous device example: modeling a triode . . . . . . . . . . . . . . . . . . . . . . . 353 PSpice-equivalent parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Implementation of PSpice-equivalent parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Modeling mathematical or instantaneous relationships . . . . . . . . . . . . . . . . . . . . . . 358 Lookup tables (ET ABLE and GT ABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Frequency-domain device models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Laplace transforms (LAPLACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Frequency response tables (EFREQ and GFREQ) . . . . . . . . . . . . . . . . . . . . . . . . . 366 Cautions and recommendations for simulation and analysis . . . . . . . . . . . . . . . . . . . . . 369 Instantaneous device modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Frequency-domain parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Laplace transforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 T rading off computer resources for accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Basic controlled sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Creating custom ABM parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375。

工程常用英语词汇

目录1、电力设计基本术语2、给水排水设计基本术语3、水泵专业英语词汇4、阀门种类英汉术语对照5、阀门专用英语词汇6、照明术语7、工程结构设计基本术语电力设计基本术语abrasion-Proof component of burner 燃烧器耐磨件arm-brace 撑脚ash conditoner 调灰器basket removal panel 元件盒检修护板BDV blow down valve 疏水阀，排污阀blind 堵板blind flange 法兰堵板/盲板法兰（盖calling 催交campell diagram 叶片埃贝尔曲线dado 墙裙daily service fuel tank level switch 日用油缸液位掣damage 损毁damper 挡板damper linkage 风闸联动装置damper motor 风闸马达damping mat 阻尼垫dangerous earth potential 危险性对地电势dashpot 减震器data transmission 数据传输DC/AC converter 直流电／交流电转换器dead 不带电dead weight 自重decanter 沉淀分取器declaration of conformity 符合标准声明decommissioning 解除运作；停止运作decompression chamber 减压室decorative lighting 装饰照明；灯饰deep bore well pump 深钻井泵defect liability period 故障修理责任期；保用期defectograph 钢缆探伤仪；故障检查仪defence in depth 纵深防御definite sequence 固定次序deflection 偏转；挠度deflector sheave 折向轮；导向轮defrost timer 防霜时间掣defrost unit 溶雪组合dehumidifier 抽湿机deleterious substance 有害物质delivery and return air temperature 送风及回风温度delivery connection 出油接头delivery pressure 输出压力demand side management 用电需求管理demand side management agreement 用电需求管理协议demand side management programme 用电需求管理计划dent 凹痕dental instrument 牙科仪器dental scaler 洗牙具Departmental Administration Division [Electrical and Mechanical Services Department] 行政部〔机电工程署〕Departmental Safety Unit [Electrical and Mechanical Services Department] 部门安全组〔机电工程署〕deposition 沉积物depth measuring facility 深度测量装置derating factor 额定值降低因子derust 除锈descale 清除氧化皮design current 设计电流design parameter 设计参数designated employee 指定雇员detachable grip 可拆除的夹扣Details of Branch Offices of Registered Electrical Contractors 注册电业承办商分行详情申报deterioration 变质；变坏Deutsche Industrie Normen [DIN] 德国工业标准device 器件；装置dewatering 脱水；排水diaphragm 膜片；隔板dielectric strength test 电介质强度测试diesel fuel tank 柴油燃料缸diesel oil 柴油differential gasket 差速器衬垫differential lock 差速器锁differential oil 差速器机油diffuser 透光罩；扩散器dilute 稀释dim sum trolley 点心手推车dim transformer 光暗变压器diminution of value 减值dimmer 调光器；光暗掣；光暗器dip tube 液位探测管Diploma in Electrical Engineering 电机工程学文凭dipstick 量油尺direct current [DC] 直流电direct current control 直流控制direct current electric drive 直流电电力驱动direct current reactor 直流电抗器direct drive 直接驱动direct purging 直接驱气direct-acting lift 直接驱动升降机direct-fired vaporizer 明火直热式汽化器direction arrow 方向箭头direction arrow plate 方向指示板direction indicator 方向指示器Director of Electrical and Mechanical Services 机电工程署署长Directory of Accredited Laboratories 认可实验所名册Directory of Quality System Registration Bodies 品质系统注册团体指南disassemble 拆散discharge 放电；卸载discharge lamp 放电灯；放电管discharge lighting 放电照明设施discharge of electricity 释电；放电discharge valve 排水阀disciplinary board 纪律审裁委员会disciplinary board panel 纪律审裁委员团disciplinary tribunal 纪律审裁小组disciplinary tribunal panel 纪律审裁委员团；纪律审裁委员会discolouring 变色disconnection 截断；截离steam hamerring analysis 汽锤分析steam packing unloading valve 汽封卸载阀steam purity 蒸汽纯度steam seal diverting valve 汽封分流阀steam seal feed valve 汽封给水阀steam water mixture 汽水混合物steel bar 扁钢steel supporting 钢支架steel wire brush 钢丝轮steel works 钢结构step load change 负荷阶跃still air 蒸馏气体stirrup 镫形夹stoikiometric ratio 化学当量比stopper 制动器、塞子storage vessell 贮水箱stppage alarm 停转报警stranded copper cable 铜绞线电缆strength 强度strong backs 支撑stud bolt 柱头螺栓、双头螺栓sub cooling line 欠热管submerged arc welding 埋弧焊substation 配电装置substation island 电气岛superficial corrosion 表面腐蚀superheat 过热度supersaturation 过饱和supervisory instrument 监测装置supply transformer 供电变压器support trunnion 支撑端轴surfactant 表面活性剂surge 喘振suspended diode 中断二极管suspended particles 悬浮颗粒switch board 开关柜switch gear 开关柜sychronization 并网sychroscope 同步指示器、同步示波器T square 丁字尺T/G transformer 发变组tackling system 起吊系统tamped/compacted backfill 夯实回填土tanks and accessories 箱罐和附件taper land thrust bearing 斜面式推力轴承tar epoxy paint 柏油环氧漆tarpaulin 防水布temperature digital display meter 温度数显表tensile test 拉伸试验tension test 拉伸试验，张力试验tensioning rod 拉杆terminal box 接线盒terminal poit 接口termination flange 接口法兰tertiary air 三次风test connection 试验接头test permition 试验合格the expansion coordinate system 热膨胀系统theodilite\transit instrument 经纬仪thermal insulatiion for tuebine casing 汽缸保温thermo resistor 热电阻thermostat 恒温器、恒温调节器thinner 稀释剂threaded flange 螺纹法兰throudh type 直通式、穿入式through bolt 贯穿螺栓、双头螺栓thrust plate 推力板tier tube 间隔管tilting pad 可倾瓦块tilting pad bearing 可倾瓦块轴承tip shroud 围带、环形叶栅外柱面tip speed 叶顶速度toe board/plate (kick plate) 踢脚板top crown plate seal 高冠板式密封装置top girder 顶板top penthouse 顶部雨棚top plan view 俯视图torquemeter 扭矩测量仪totalnumber of welding 焊口总数trajectory 轨道、轨迹transducer board 变送器屏transfer pipe 引出管transition piece 过渡连接件transtion piece 过渡段transverse strength 弯曲强度、抗挠强度transverse stress 横向应力、弯曲应力transverse test 抗弯试验trapezoid corrugated plate seperater 梯形波形板分离器、顶帽travelling crab 小车起重机travelling hoist 移动卷扬机tread width 踏步宽度trestle 组合支架trim and grind the welding 修磨焊点trisector air preheater 三分仓空预器trunk cable pair 主电缆对trunnion air seal assembly 端轴空气密封tube exchanger 管式热交换器tubing stress analysis 管系应力分析turbidity analyser 浊度分析仪turbine lube oil and conditioning system 汽机润滑油及净化系统turning oil 循环油twisted pair conveyer 双绞线传送器undercut 坡口underflow 地流、潜流、下溢union 活接头、管节unit control 单元控制unloadding spout vent fan 卸料口通风风机unloading valve 卸载阀urgent need equipment 急需设备urgtented need equipment 急需设备u-shape hanger chains u形曲链片吊挂装置UT ultrasonic testing 超声波探伤UTS ultimate tensible strength 极限抗拉强度vacuum belt filter 皮带真空吸滤器valve opening chart at load rejection 甩负荷阀门开启阀valve seat body seat 阀座valve spindle 阀轴、阀杆valve stem 阀杆vapor proof 防水灯variable inlet guide vane centrifugal fan 进口可调导叶离心式风机variable moning blade axial flow fan 动叶可调轴流式风机variable moving blade double stage axial fan 动叶可调双级轴流式风机variable speed driver 变速马达variables 变量vent capacity 排放量vent line 放气管ventilator valve 通风阀vernier caliper 游标卡尺vertical deflection 垂直挠度vertical movement 垂直位移vertical spindle coal pulveriser 立式磨煤机vibration isolation 隔振装置viewing lamp 观察指示灯viscosity 粘滞度、内摩擦viscous fluid 粘性液体visual examination of coating 外观质量vlve body 阀体void 无效volatily 挥发分voltage class 电压等级vortex gasket 涡流垫片wall type and retractable soot blower 墙式、伸缩式吹灰器warm air curtain 热风幕rwarming line 加热管water balance 水平衡water induction prevent control 防进水控制water level gauge 水位计water stop flange 止水法兰water supply facility island 水工岛wear hardness 可抗磨能力wear template 防磨板wearing bush 防磨套wearing plate 防磨板、护板weigh feeder 重量计量进料器weld bolt 焊接螺栓weld contamination 焊接杂质weld groove 焊缝坡口weld pass 焊道weld penetration 熔深weld preparation 焊缝坡口加工weld with shop beveled ends 工厂加工坡口焊接welder helment 面罩welding line 焊缝welding plate flange 焊接板式法兰welding rod 焊条welding rods dryer barrel 焊条保温筒welding run 焊道welding seam 对接焊缝welding technological properties 焊接工艺性能welding tool 电焊钳welding torch 焊枪welding wire 焊丝welds counting quantity 焊口统计数量wellington boot 防水长统靴whirl plate 折流板wide column 宽立柱winding resistance 绕组电阻wire feed speed 送丝速度wire netting/metal mesh 铁丝网wire wool 擦洗用的）钢丝绒，百洁丝withstand voltage test 耐压试验working medium 工质worm hole （焊缝）条虫状气孔yield strength 屈服强度yoke 磁轭、人孔压板、座架联板firproof paint 防火漆manifold valve 汇集阀saw trace 锯痕tapping point 取样点bushing current transformer 套管式电流互感器light gauge plate/sheet 薄钢板notch 槽口、凹口holding strip 压板straight edge 校正装置trailing edge 后缘lance 喷枪lighting off 点火gaseous fuel 气体燃料entrain 夹带、传输combustion air 助燃风hot stand by 热备用行波travelling wave模糊神经网络fuzzy-neural network神经网络neural network模糊控制fuzzy control研究方向 research direction副教授associate professor电力系统the electrical power system大容量发电机组large capacity generating set输电距离electricity transmission超高压输电线supervltage transmission power line 投运commissioning行波保护Traveling wave protection自适应控制方法adaptive control process动作速度speed of action行波信号travelling wave signal测量信号measurement signal暂态分量transient state component非线性系统nonlinear system高精度high accuracy自学习功能selflearning function抗干扰能力antijamming capability自适应系统adaptive system行波继电器travelling wave relay输电线路故障transmission line malfunction仿真simulation算法algorithm电位electric potential短路故障short trouble子系统subsystem大小相等，方向相反equal and opposite in direction 电压源voltage source故障点trouble spot等效于equivalent暂态行波transient state travelling wave偏移量side-play mount电压electric voltage附加系统add-ons system波形waveform工频power frequency延迟变换delayed transformation延迟时间delay time减法运算subtraction相减运算additive operation求和器summator模糊规则fuzzy rule参数值parameter values可靠动作action message等值波阻抗equivalent value wave impedance附加网络additional network修改的modified反传算法backpropagation algorithm隶属函数membership function模糊规则fuzzy rule模糊推理fuzzy reasoning样本集合 sample set给定的given模糊推理矩阵fuzzy reasoning matrix采样周期sampling period三角形隶属度函数Triangle-shape grade of membership function 负荷状态load conditions区内故障troubles inside the sample space门槛值threshold level采样频率sampling frequency全面地all sidedly样本空间sample space误动作malfunction保护特性protection feature仿真数据simulation data灵敏性sensitivity小波变换wavelet transformation神经元neuron谐波电流harmonic current电力系统自动化power system automation继电保护relaying protection中国电力 China Power学报 journal初探primary exploration标准的机组数据显示 (Standard Measurement And Display Data)负载电流百分比显示 Percentage of Current load(%)单相/三相电压 Voltage by One/Three Phase (Volt.)每相电流 Current by Phase (AMP)千伏安 Apparent Power (KVA)中线电流 Neutral Current (N Amp)功率因数 Power Factor (PF)频率 Frequency(HZ)千瓦 Active Power (KW)千阀 Reactive Power (KVAr)最高/低电压及电流 Max/Min. Current and Voltage输出千瓦/兆瓦小时 Output kWh/MWh运行转速 Running RPM机组运行正常 Normal Running超速故障停机 Overspeed Shutdowns低油压故障停机 Low Oil Pressure Shutdowns高水温故障停机 High Coolant Temperature Shutdowns起动失败停机 Fail to Start Shutdowns冷却水温度表 Coolant Temperature Gauge机油油压表 Oil Pressure Gauge电瓶电压表 Battery Voltage Meter机组运行小时表 Genset Running Hour Meter怠速-快速运行选择键 Idle Run – Normal Run Selector Switch运行-停机-摇控启动选择键 Local Run-Stop-Remote Starting Selector Switch其它故障显示及输入 Other Common Fault Alarm Display and input给水排水设计基本术语一、通用术语给水排水工程的通用术语及其涵义应符合下列规定：1、给水工程water supply engineering 原水的取集和处理以及成品水输配的工程。

top258pn

TOP252-262TOPSwitch-HX Family January 2009Enhanced EcoSmart ®, Integrated Off-Line Switcher with Advanced Feature Set and Extended Power Range®Product HighlightsLower System Cost, Higher Design FlexibilityMulti-mode operation maximizes efﬁciency at all loads New eSIP-7F and eSIP-7C packagesLow thermal impedance junction-to-case (2 °C per watt)Low height is ideal for adapters where space is limitedSimple mounting using a clip to aid low cost manufacturing Horizontal eSIP-7F package ideal for ultra low height adapter and monitor applicationsExtended package creepage distance from DRAIN pin to adjacent pin and to heat sinkNo heatsink required up to 35 W using P , G and M packages with universal input voltage and up to 48 W at 230 VACOutput overvoltage protection (OVP) is user programmable for latching/non-latching shutdown with fast AC reset Allows both primary and secondary sensingLine undervoltage (UV) detection prevents turn-off glitches Line overvoltage (OV) shutdown extends line surge limit Accurate programmable current limitOptimized line feed-forward for line ripple rejection132 kHz frequency (254Y-258Y and all E/L packages) reduces transformer and power supply sizeHalf frequency option for video applications Frequency jittering reduces EMI ﬁ lter cost •••••••••••••••••Figure 1. Typical Flyback Application.Heatsink is connected to SOURCE for low EMIImproved auto-restart delivers <3% of maximum power in short circuit and open loop fault conditionsAccurate hysteretic thermal shutdown function automatically recovers without requiring a resetFully integrated soft-start for minimum start-up stress Extended creepage between DRAIN and all other pins improves ﬁ eld reliability•••••Table 1.Output Power Table. (for notes see page 2).Rev. F 01/09EcoSmart ®– Energy Efﬁ cientEnergy efﬁcient over entire load range No-load consumptionLess than 200 mW at 230 VAC Standby power for 1 W input>600 mW output at 110 VAC input >500 mW output at 265 VAC inputDescriptionTOPSwitch-HX cost effectively incorporates a 700 V power MOSFET, high voltage switched current source, PWM control, oscillator, thermal shutdown circuit, fault protection and other control circuitry onto a monolithic device.••••••Figure 2. Typical Flyback Application TOP259YN, TOP260YN and TOP261YN.Y Package Option for TOP259-261In order to improve noise-immunity on large TOPSwitch-HX Y package parts, the F pin has been removed (TOP259-261YN are ﬁ xed at 66 kHz switching frequency) and replaced with a SIGNAL GROUND (G) pin. This pin acts as a low noise path for the C pin capacitor and the X pin resistor. It is only required for the TOP259-261YN package parts.Notes for Table 1:1. Minimum continuous power in a typical non-ventilatedenclosed adapter measured at +50 °C ambient. Use of an external heat sink will increase power capability. 2. Minimum continuous power in an open frame design at+50 °C ambient.3. Peak power capability in any design at +50 °C ambient.4. 230 VAC or 110/115 VAC with doubler.5. Packages: P: DIP-8C, G: SMD-8C, M: SDIP-10C,Y: TO-220-7C, E: eSIP-7C, L: eSIP-7F .See part ordering information.6. TOP261 and TOP262 have the same current limit set point. Insome applications TOP262 may run cooler than TOP261 due to a lower R DS(ON) for the larger device.7. TOP256E package parts are available with Green (HalogenFree) mold compound. See Part Ordering Information on page 47. Parametrically green material encapsulated E package parts are identical to non-green parts. Section ListFunctional Block Diagram (4)Pin Functional Description (6)TOPSwitch-HX Family Functional Description (7)CONTROL (C) Pin Operation (8)Oscillator and Switching Frequency (8)Pulse Width Modulator (9)Maximum Load Cycle (9)ErrorAmpliﬁer (9)On-Chip Current Limit with External Programmability (9)Line Under-Voltage Detection (UV) (10)Line Overvoltage Shutdown (OV) (11)Hysteretic or Latching Output Overvoltage Protection (OVP) (11)Line Feed-Forward with DCMAX Reduction (13)Remote ON/OFF and Synchronization (13)Soft-Start (13)Shutdown/Auto-Restart (13)Hysteretic Over-Temperature Protection (13)BandgapReference (13)High-Voltage Bias Current Source (13)Typical Uses of FREQUENCY (F) Pin (15)Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins (16)Typical Uses of MULTI-FUNCTION (M) Pin (18)Application Examples (21)A High Efﬁ ciency, 35 W, Dual Output – Universal Input Power Supply (21)A High Efﬁ ciency, 1500 W, 250-380 VDC Input Power Supply (22)A High Efﬁ ciency, 20 W Continuous – 80 W Peak, Universal Input Power Supply (23)A High Efﬁ ciency, 65 W, Universal Input Power Supply (24)Key Application Considerations (25)TOPSwitch-HX vs.TOPSwitch-GX (25)TOPSwitch-HX Design Considerations (26)TOPSwitch-HX Layout Considerations (27)Quick Design Checklist (31)DesignTools (31)Product Speciﬁ cations and Test Conditions (32)Typical Performance Characteristics (39)Package Outlines (43)Part Ordering Information (47)Rev. F 01/09Rev. F 01/09Figure 3a. Functional Block Diagram (P and G Packages).Figure 3b. Functional Block Diagram (M Package).Rev. F 01/09Figure 3c. Functional Block Diagram (TOP254-258 YN Package and all eSIP Packages).Figure 3d. Functional Block Diagram TOP259YN, TOP260YN, TOP261YN.Rev. F 01/09Pin Functional DescriptionDRAIN (D) Pin:High-voltage power MOSFET DRAIN pin. The internal start-up bias current is drawn from this pin through a switched high-voltage current source. Internal current limit sense point for drain current.CONTROL (C) Pin:Error ampliﬁ er and feedback current input pin for duty cycle control. Internal shunt regulator connection to provide internal bias current during normal operation. It is also used as the connection point for the supply bypass and auto-restart/compensation capacitor.EXTERNAL CURRENT LIMIT (X) Pin (Y, M, E and L package):Input pin for external current limit adjustment and remote ON/OFF. A connection to SOURCE pin disables all functions on this pin.Figure 4. Pin Conﬁ guration (Top View).P I -4711-021308Figure 5. TOP254-258 Y and All M/E/L Package Line Sense and Externally Set Current Limit.Figure 7. P/G Package Line Sense.P I -4983-021308Figure 6. TOP259-261 Y Package Line Sense and External Current Limit.VOLTAGE MONITOR (V) Pin (Y & M package only):Input for OV, UV, line feed forward with DC MAX reduction, output overvoltage protection (OVP), remote ON/OFF and device reset. A connection to the SOURCE pin disables all functions on this pin.MULTI-FUNCTION (M) Pin (P & G packages only):This pin combines the functions of the VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) pins of the Y package into one pin. Input pin for OV, UV, line feed forward with DC MAXRev. F 01/09Figure 8. P/G Package Externally Set Current Limit.reduction, output overvoltage protection (OVP), external current limit adjustment, remote ON/OFF and device reset. Aconnection to SOURCE pin disables all functions on this pin and makes TOPSwitch-HX operate in simple three terminal mode (like TOPSwitch-II).FREQUENCY (F) Pin (TOP254-258Y, and all E and L packages):Input pin for selecting switching frequency 132 kHz if connected to SOURCE pin and 66 kHz if connected to CONTROL pin. The switching frequency is internally set for ﬁ xed 66 kHzoperation in the P , G, M package and TOP259YN, TOP260YN and TOP261YN.SIGNAL GROUND (G) Pin (TOP259YN, TOP260YN & TOP261YN only):Return for C pin capacitor and X pin resistor.SOURCE (S) Pin:Output MOSFET source connection for high voltage power return. Primary side control circuit common and reference point.TOPSwitch-HX Family Functional DescriptionLike TOPSwitch-GX, TOPSwitch-HX is an integrated switched mode power supply chip that converts a current at the control input to a duty cycle at the open drain output of a high voltage power MOSFET. During normal operation the duty cycle of the power MOSFET decreases linearly with increasing CONTROL pin current as shown in Figure 9.In addition to the three terminal TOPSwitch features, such as the high voltage start-up, the cycle-by-cycle current limiting, loop compensation circuitry, auto-restart and thermalshutdown, the TOPSwitch-HX incorporates many additional functions that reduce system cost, increase power supply performance and design ﬂ exibility. A patented high voltageCMOS technology allows both the high-voltage power MOSFET and all the low voltage control circuitry to be cost effectively integrated onto a single monolithic chip.Three terminals, FREQUENCY, VOLTAGE-MONITOR, andEXTERNAL CURRENT LIMIT (available in Y and E/L packages),two terminals, VOLTAGE-MONITOR and EXTERNAL CURRENT LIMIT (available in M package) or one terminal MULTI-FUNCTION (available in P and G package) have been used to implement some of the new functions. These terminals can be connected to the SOURCE pin to operate the TOPSwitch-HX in aTOPSwitch-like three terminal mode. However, even in this three terminal mode, the TOPSwitch-HX offers many transparent features that do not require any external components:A fully integrated 17 ms soft-start signiﬁcantly reduces or eliminates output overshoot in most applications by sweeping both current limit and frequency from low to high to limit the peak currents and voltages during start-up.A maximum duty cycle (DC MAX ) of 78% allows smaller inputstorage capacitor, lower input voltage requirement and/or higher power capability.Multi-mode operation optimizes and improves the powersupply efﬁ ciency over the entire load range while maintaining good cross regulation in multi-output supplies.1.2.3.Figure 9. Control Pin Characteristics (Multi-Mode Operation).Rev. F 01/09Switching frequency of 132 kHz reduces the transformer sizewith no noticeable impact on EMI.Frequency jittering reduces EMI in the full frequency mode athigh load condition.Hysteretic over-temperature shutdown ensures automaticrecovery from thermal fault. Large hysteresis prevents circuit board overheating.Packages with omitted pins and lead forming provide largedrain creepage distance.Reduction of the auto-restart duty cycle and frequency toimprove the protection of the power supply and load during open loop fault, short circuit, or loss of regulation.Tighter tolerances on I 2f power coefﬁ cient, current limitreduction, PWM gain and thermal shutdown threshold.The VOLTAGE-MONITOR (V) pin is usually used for line sensing by connecting a 4 M Ω resistor from this pin to the rectiﬁ ed DC high voltage bus to implement line overvoltage (OV), under-voltage (UV) and dual-slope line feed-forward with DC MAXreduction. In this mode, the value of the resistor determines the OV/UV thresholds and the DC MAX is reduced linearly with a dual slope to improve line ripple rejection. In addition, it also provides another threshold to implement the latched and hysteretic output overvoltage protection (OVP). The pin can also be used as a remote ON/OFF using the I UV threshold.The EXTERNAL CURRENT LIMIT (X) pin can be used to reduce the current limit externally to a value close to the operating peak current, by connecting the pin to SOURCE through a resistor. This pin can also be used as a remote ON/OFF input.For the P and G package the VOLTAGE-MONITOR andEXTERNAL CURRENT LIMIT pin functions are combined on one MULTI-FUNCTION (M) pin. However, some of the functions become mutually exclusive.The FREQUENCY (F) pin in the TOP254-258 Y and E/L packages set the switching frequency in the full frequency PWM mode to the default value of 132 kHz when connected to SOURCE pin. A half frequency option of 66 kHz can be chosen by connecting this pin to the CONTROL pin instead. Leaving this pin open is not recommended. In the P , G and M packages and the TOP259-261 Y packages, the frequency is set internally at 66 kHz in the full frequency PWM mode.CONTROL (C) Pin OperationThe CONTROL pin is a low impedance node that is capable of receiving a combined supply and feedback current. During normal operation, a shunt regulator is used to separate thefeedback signal from the supply current. CONTROL pin voltage V C is the supply voltage for the control circuitry including the MOSFET gate driver. An external bypass capacitor closely connected between the CONTROL and SOURCE pins is required to supply the instantaneous gate drive current. The total amount of capacitance connected to this pin also sets the auto-restart timing as well as control loop compensation.When rectiﬁ ed DC high voltage is applied to the DRAIN pin during start-up, the MOSFET is initially off, and the CONTROL pin capacitor is charged through a switched high voltage4.5.6.7.8.9.current source connected internally between the DRAIN and CONTROL pins. When the CONTROL pin voltage V C reaches approximately 5.8 V, the control circuitry is activated and the soft-start begins. The soft-start circuit gradually increases the drain peak current and switching frequency from a low starting value to the maximum drain peak current at the full frequency over approximately 17 ms. If no external feedback/supplycurrent is fed into the CONTROL pin by the end of the soft-start, the high voltage current source is turned off and the CONTROL pin will start discharging in response to the supply current drawn by the control circuitry. If the power supply is designed properly, and no fault condition such as open loop or shorted output exists, the feedback loop will close, providing external CONTROL pin current, before the CONTROL pin voltage has had a chance to discharge to the lower threshold voltage of approximately 4.8 V (internal supply undervoltage lockout threshold). When the externally fed current charges theCONTROL pin to the shunt regulator voltage of 5.8 V, current in excess of the consumption of the chip is shunted to SOURCE through an NMOS current mirror as shown in Figure 3. The output current of that NMOS current mirror controls the duty cycle of the power MOSFET to provide closed loop regulation. The shunt regulator has a ﬁ nite low output impedance Z C that sets the gain of the error ampliﬁ er when used in a primary feedback conﬁ guration. The dynamic impedance Z C of the CONTROL pin together with the external CONTROL pin capacitance sets the dominant pole for the control loop.When a fault condition such as an open loop or shorted output prevents the ﬂ ow of an external current into the CONTROL pin, the capacitor on the CONTROL pin discharges towards 4.8 V. At 4.8 V, auto-restart is activated, which turns the output MOSFET off and puts the control circuitry in a low current standby mode. The high-voltage current source turns on and charges the external capacitance again. A hysteretic internal supply undervoltage comparator keeps V C within a window of typically 4.8 V to 5.8 V by turning the high-voltage current source on and off as shown in Figure 11. The auto-restart circuit has a divide-by-sixteen counter, which prevents the output MOSFET from turning on again until sixteen discharge/charge cycles have elapsed. This is accomplished by enabling the output MOSFET only when the divide-by-sixteen counter reaches the full count (S15). The counter effectively limitsTOPSwitch-HX power dissipation by reducing the auto-restart duty cycle to typically 2%. Auto-restart mode continues until output voltage regulation is again achieved through closure of the feedback loop.Oscillator and Switching FrequencyThe internal oscillator linearly charges and discharges an internal capacitance between two voltage levels to create atriangular waveform for the timing of the pulse width modulator. This oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle.The nominal full switching frequency of 132 kHz was chosen to minimize transformer size while keeping the fundamental EMI frequency below 150 kHz. The FREQUENCY pin (available only in TOP254-258 Y and E, L packages), when shorted to the CONTROL pin, lowers the full switching frequency to 66 kHzRev. F 01/09Figure 10. Switching Frequency Jitter (Idealized V DRAIN Waveforms).(half frequency), which may be preferable in some cases such as noise sensitive video applications or a high efﬁ ciency standby mode. Otherwise, the FREQUENCY pin should be connected to the SOURCE pin for the default 132 kHz. In the M, P and G packages and the TOP259-261 Y package option, the full frequency PWM mode is set at 66 kHz, for higher efﬁ ciency and increased output power in all applications.To further reduce the EMI level, the switching frequency in the full frequency PWM mode is jittered (frequency modulated) by approximately ±2.5 kHz for 66 kHz operation or ±5 kHz for 132 kHz operation at a 250 Hz (typical) rate as shown in Figure 10. The jitter is turned off gradually as the system is entering the variable frequency mode with a ﬁ xed peak drain current.Pulse Width ModulatorThe pulse width modulator implements multi-mode control by driving the output MOSFET with a duty cycle inversely proportional to the current into the CONTROL pin that is in excess of the internal supply current of the chip (see Figure 9). The feedback error signal, in the form of the excess current, is ﬁ ltered by an RC network with a typical corner frequency of 7 kHz to reduce the effect of switching noise in the chip supply current generated by the MOSFET gate driver.To optimize power supply efﬁ ciency, four different control modes are implemented. At maximum load, the modulator operates in full frequency PWM mode; as load decreases, the modulator automatically transitions, ﬁ rst to variable frequency PWM mode, then to low frequency PWM mode. At light load, the control operation switches from PWM control to multi-cycle-modulation control, and the modulator operates in multi-cycle-modulation mode. Although different modes operate differently to make transitions between modes smooth, the simple relationship between duty cycle and excess CONTROL pin current shown in Figure 9 is maintained through all three PWM modes. Please see the following sections for the details of the operation of each mode and the transitions between modes.Full Frequency PWM mode: The PWM modulator enters full frequency PWM mode when the CONTROL pin current (I C ) reaches I B . In this mode, the average switching frequency is kept constant at f OSC (66 kHz for P , G and M packages and TOP259-261 Y, pin selectable 132 kHz or 66 kHz for Y and E/Lpackages). Duty cycle is reduced from DC MAX through the reduction of the on-time when I C is increased beyond I B . This operation is identical to the PWM control of all other TOPSwitch families. TOPSwitch-HX only operates in this mode if the cycle-by-cycle peak drain current stays above k PS(UPPER)*I LIMIT (set), where k PS(UPPER) is 55% (typical) and I LIMIT (set) is the current limit externally set via the X or M pin.Variable Frequency PWM mode: When peak drain current is lowered to k PS(UPPER)* I LIMIT (set) as a result of power supply load reduction, the PWM modulator initiates the transition to variable frequency PWM mode, and gradually turns off frequency jitter. In this mode, peak drain current is held constant at k PS(UPPER)* I LIMIT (set) while switching frequency drops from the initial full frequency of f OSC (132 kHz or 66 kHz) towards the minimum frequency of f MCM(MIN) (30 kHz typical). Duty cycle reduction is accomplished by extending the off-time.Low Frequency PWM mode: When switching frequencyreaches f MCM(MIN) (30 kHz typical), the PWM modulator starts to transition to low frequency mode. In this mode, switchingfrequency is held constant at f MCM(MIN) and duty cycle is reduced, similar to the full frequency PWM mode, through the reduction of the on-time. Peak drain current decreases from the initial value of k PS(UPPER)* I LIMIT (set) towards the minimum value ofk PS(LOWER)*I LIMIT (set), where k PS(LOWER) is 25% (typical) and I LIMIT (set) is the current limit externally set via the X or M pin.Multi-Cycle-Modulation mode: When peak drain current is lowered to k PS(LOWER)*I LIMIT (set), the modulator transitions to multi-cycle-modulation mode. In this mode, at each turn-on, the modulator enables output switching for a period of T MCM(MIN) at the switching frequency of f MCM(MIN) (4 or 5 consecutive pulses at 30 kHz) with the peak drain current of k PS(LOWER)*I LIMIT (set), and stays off until the CONTROL pin current falls below I C(OFF). This mode of operation not only keeps peak drain current low but also minimizes harmonic frequencies between 6 kHz and30 kHz. By avoiding transformer resonant frequency this way, all potential transformer audible noises are greatly supressed.Maximum Duty CycleThe maximum duty cycle, DC MAX , is set at a default maximum value of 78% (typical). However, by connecting the VOLTAGE-MONITOR or MULTI-FUNCTION pin (depending on the package) to the rectiﬁ ed DC high voltage bus through a resistor with appropriate value (4 M Ω typical), the maximum duty cycle can be made to decrease from 78% to 40% (typical) when input line voltage increases from 88 V to 380 V, with dual gain slopes.Error Ampliﬁ erThe shunt regulator can also perform the function of an error ampliﬁ er in primary side feedback applications. The shunt regulator voltage is accurately derived from a temperature-compensated bandgap reference. The CONTROL pin dynamic impedance Z C sets the gain of the error ampliﬁ er. TheCONTROL pin clamps external circuit signals to the V C voltage level. The CONTROL pin current in excess of the supply current is separated by the shunt regulator and becomes the feedback current I fb for the pulse width modulator.Rev. F 01/09On-Chip Current Limit with External ProgrammabilityThe cycle-by-cycle peak drain current limit circuit uses the output MOSFET ON-resistance as a sense resistor. A current limit comparator compares the output MOSFET on-state drain to source voltage V DS(ON) with a threshold voltage. High drain current causes V DS(ON) to exceed the threshold voltage and turns the output MOSFET off until the start of the next clock cycle. The current limit comparator threshold voltage is temperature compensated to minimize the variation of the current limit due to temperature related changes in R DS(ON) of the output MOSFET. The default current limit of TOPSwitch-HX is preset internally. However, with a resistor connected between EXTERNAL CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTI-FUNCTION (M) pin (P and G package) and SOURCE pin (for TOP259-261 Y, the X pin is connected to the SIGNAL GROUND (G) pin), current limit can be programmed externally to a lower level between 30% and 100% of the default current limit. By setting current limit low, a larger TOPSwitch-HX than necessary for the power required can be used to take advantage of the lower R DS(ON) for higher efﬁ ciency/smaller heat sinkingrequirements. TOPSwitch-HX current limit reduction initial tolerance through the X pin (or M pin) has been improved signiﬁ cantly compare with previous TOPSwitch-GX. With a second resistor connected between the EXTERNAL CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTI-FUNCTION (M) pin (P and G package) and the rectiﬁ ed DC high voltage bus, the current limit is reduced with increasing line voltage, allowing a true power limiting operation against line variation to be implemented. When using an RCD clamp, this power limiting technique reduces maximum clamp voltage at high line. This allows for higher reﬂ ected voltage designs as well as reducing clamp dissipation.The leading edge blanking circuit inhibits the current limitcomparator for a short time after the output MOSFET is turned on. The leading edge blanking time has been set so that, if a power supply is designed properly, current spikes caused by primary-side capacitances and secondary-side rectiﬁ er reverse recovery time should not cause premature termination of the switching pulse.The current limit is lower for a short period after the leading edge blanking time. This is due to dynamic characteristics of the MOSFET. During startup and fault conditions the controller prevents excessive drain currents by reducing the switching frequency.Line Undervoltage Detection (UV)At power up, UV keeps TOPSwitch-HX off until the input line voltage reaches the undervoltage threshold. At power down, UV prevents auto-restart attempts after the output goes out of regulation. This eliminates power down glitches caused by slow discharge of the large input storage capacitor present in applications such as standby supplies. A single resistor connected from the VOLTAGE-MONITOR pin (Y, E/L and M packages) or MULTI-FUNCTION pin (P and G packages) to the rectiﬁ ed DC high voltage bus sets UV threshold during power up. Once the power supply is successfully turned on, the UV threshold is lowered to 44% of the initial UV threshold to allow extended input voltage operating range (UV low threshold). If the UV low threshold is reached during operation without the power supply losing regulation, the device will turn off and stay off until UV (high threshold) has been reached again. If the power supply loses regulation before reaching the UV lowthreshold, the device will enter auto-restart. At the end of each auto-restart cycle (S15), the UV comparator is enabled. If the UV high threshold is not exceeded, the MOSFET will bedisabled during the next cycle (see Figure 11). The UV feature can be disabled independent of the OV feature.Figure 11. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.Line Overvoltage Shutdown (OV)The same resistor used for UV also sets an overvoltage threshold, which, once exceeded, will force TOPSwitch-HX to stop switching instantaneously (after completion of the current switching cycle). If this condition lasts for at least 100 μs, the TOPSwitch-HX output will be forced into off state. Unlike with TOPSwitch-GX, however, when the line voltage is back to normal with a small amount of hysteresis provided on the OV threshold to prevent noise triggering, the state machine sets to S13 and forces TOPSwitch-HX to go through the entire auto-restart sequence before attempting to switch again. The ratio of OV and UV thresholds is preset at 4.5, as can be seen in Figure 12. When the MOSFET is off, the rectiﬁ ed DC high voltage surge capability is increased to the voltage rating of the MOSFET (700 V), due to the absence of the reﬂ ected voltage and leakage spikes on the drain. The OV feature can be disabled independent of the UV feature.In order to reduce the no-load input power of TOPSwitch-HX designs, the V-pin (or M-pin for P Package) operates at very low currents. This requires careful layout considerations when designing the PCB to avoid noise coupling. Traces and components connected to the V-pin should not be adjacent to any traces carrying switching currents. These include the drain, clamp network, bias winding return or power traces from otherconverters. If the line sensing features are used, then the senseresistors must be placed within 10 mm of the V-pin to minimizethe V-pin node area. The DC bus should then be routed to theline sense resistors. Note that external capacitance must notbe connected to the V-pin as this may cause misoperaton of theV pin related functions.Hysteretic or Latching Output Overvoltage Protection (OVP) The detection of the hysteretic or latching output overvoltageprotection (OVP) is through the trigger of the line overvoltagethreshold. The V-pin or M-pin voltage will drop by 0.5 V, andthe controller measures the external attached impedanceimmediately after this voltage drops. If IVor IMexceeds IOV(LS) (336 μA typical) longer than 100 μs, TOPSwitch-HX will latchinto a permanent off state for the latching OVP. It only can bereset if VVor VMgoes below 1 V or VCgoes below the power-up-reset threshold (VC(RESET)) and then back to normal.If IVor IMdoes not exceed IOV(LS)or exceeds no longer than100 μs, TOPSwitch-HX will initiate the line overvoltage and thehysteretic OVP. Their behavior will be identical to the line overvoltage shutdown (OV) that has been described in detail in the previous section.Voltage Monitor and External Current Limit Pin Table**This table is only a partial list of many VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT Pin Conﬁ gurations that are possible. Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Conﬁ guration Options.Multi-Function Pin Table**This table is only a partial list of many MULTI-FUNCTIONAL Pin Conﬁ gurations that are possible.Table 3. MULTI-FUNCTION (M) Pin Conﬁ guration Options.。

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Journal of Biomolecular gnal Windows in High Throughput Screening Assays for Drug Discovery
G. Sitta Sittampalam, Philip W. Iversen, Joyce A. Boadt, Steven D. Kahl, Stuart Bright, Joseph M. Zock, William P. Janzen and Mark D. Lister J Biomol Screen 1997 2: 159 DOI: 10.1177/108705719700200306 The online version of this article can be found at: /content/2/3/159
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