How_to_select_I2C_Bus_Buffer

COMPANY CONFIDENTIAL
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What is I² C?
A communication bus for slow to medium speed digital data (<1MHz)
I² = Inter Integrated Circuit (Philips invented in the 1980s) C Commonly described as “Two-wire bus”
PCA9515A/16A/17A/18 A, PCA9507/08/09, PCA9519, P82B96… PCA9510A – PCA9514A PCA9521, PCA9522
PCA9525 PCA9605 P82B715
Amplifier
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I2C Bus Buffer types – STATIC OFFSET
I² bus hot swap C
Long cable transmission
BUS BUFFER
M
I²C Bus A
S
B
S
S
I²C Bus B SLAVES
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How Does an I² Bus Buffer Work? C
Any Bus Buffer must allow signals to pass in either direction
S slave address R A data A data
data A P
transmitter
SCL
Master
A P
SDA
Hale Waihona Puke Slave transmitter
receiver
SCL
< n data bytes > last data byte
S = Start condition A = Acknowledge P = Stop condition
One wire for data - SDA, one wire for clock - SCL
Master-Slave hierarchy for simplicity I2C = Inter Integrated Circuit
V
CC
Saves PCB space Easily expandable Better results, no hassle
A SIDE
X
B SIDE
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How to fix the “Bus Latch Up” problem?
Using general logic, with just two logic levels (Hi and Lo), it‟s not possible to build a bi-directional I2C buffer so there has to be some compromise. By accepting some small compromises in performance we can build I2C-bus buffers that achieve, for practical purposes, the bi-directional characteristic we need. So far, there are 4 solutions to make 4 different buffer types:
Open drain drivers can only pull the bus LOW or release it.
So it is pulled HIGH only by the pull-up resistor.
SCL or SDA
Open Drain FET Open Collector BJT GND
Buffer using special input and output logic LOW levels to avoid latching of the buffer. The logic LOW output level VOL is placed at a level slightly above its corresponding logic LOW input level requirement The special levels are offset by a fixed amount above 0V Example Part Numbers: PCA9509 (Side A), PCA9517A (Side B),
A Low on the A side will create a low on the B side The new low on the B side creates a low on the A side Release of the A side causes the buffer to remain low on both sides This is Called “Bus Latch Up” – It is fatal. Conclusion: There must be special bus buffer for I² Bus! C
Advantages
• • •
Disadvantages
Restricts low bus voltage requirement on the static offset side Offset stops interface with other buffers
Strong drive down to VOL (~0.6 V) Over-voltage tolerance Work with any slave when bus low voltage is acceptable
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GND
Why to use an I² Bus Buffer? C
If I² bus is greater than > 400 pF capacitance specification (to drive C longer distance or more devices) Bus level translation is required
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Triangle Wave method to test Bus Buffers
A Triangular “Test Waveform” is used to explain how different Bus Buffer types react to input signals We can identify the input voltage levels at which the output changes, and the output levels produced This signal swings from GND to VDD (typically 0 to 3.3V)
How to Select I² Bus Buffer? C
2Q 2011 Bruce Xu – Technical Marketing
Agenda
I² Bus Overview C
I² Bus Buffers C
I² Bus Buffer Types C
I² Noise Margins C
I² Bus buffer Applications C
1. 2. 3. 4. Static Offset Incremental Offset Amplifier No Offset
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Bus Buffer Types – different Offset design
Type Function Example PNs
The direction is automatic, without disrupting the I² Traffic C
SDA or SCL
A SIDE
B SIDE
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I² Bus Buffer Problem – Using General C Logic
Open Drain FET (or Open Collector BJT) control SDA and SCL Pull Up Resistor (only ONE on each of the two I² bus lines) C
Only open drain or open collector drivers are allowed to be connected to an I² bus. C VDD
Master OR Slave send data (one byte) Slave sends Master the ACK or NACK (1bit)
…
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How are the I² signals connected? C
Each wire is Bi-directional (Sends / Receives, but not at the same time)
R = read (active high) A = Not Acknowledge W = Write (active low)
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COMPANY CONFIDENTIAL
What is the Payload?
Payload is always less than the stated bus speeds:
Static Offset