移位寄存器--DE2开发板(西邮)
EDA技术实训_DE2使用教程
Altera DE2 使用教程电子信息科学与技术系目录DE2开发板资源: (3)FPGA简要介绍 (5)Quaturs使用基础 (7)用HDL写代码 (22)管脚的输入方式 (25)NIOSII 实验 (25)FAQ (36)DE2开发板资源:Table. DE2 Board InformationFPGA•Cyclone II EP2C35F672C6 with EPCS16 16-Mbit serial configuration deviceI/O Devices•Built-in USB-Blaster TM cable for FPGA configuration•10/100 Ethernet•RS232•Video out (VGA 10-bit DAC)•Video in (NTSC/PAL/multi-format)•USB 2.0 (type A and type B)•PS/2 mouse or keyboard port•Line in/out, microphone in (24-bit Audio CODEC)•Expansion headers (76 signal pins)•Infrared portMemory•8-MBytes SDRAM, 512K SRAM, 4-MBytes flash•SD memory card slotDisplays•16 x 2 LCD display•Eight 7-segment displaysSwitches and LEDs•18 toggle switches•18 red LEDs•9 green LEDs•Four debounced push-button switchesClocks•50-MHz crystal for FPGA clock input•27-MHz crystal for video applications•External SMA clock input可以在目前开发板上做的实验包括基本的VHDL以及Verilog HDL实验接口实验高级实验NIOS II CPU 实验开发套件清单1DE2开发板一个2ByteBlasterII 下载电缆1根35v电源一个4光盘一张FPGA简要介绍FPGA是英文Field Programmable Gate Array的缩写，即现场可编程门阵列，它是在PAL、GAL、EPLD等可编程器件的基础上进一步发展的产物。
EDA实验装置DE2开发板介绍
信息与通信工程学院
电子设计自动化
AS下载方式操作方法：
AS下载方案示意图
信息与通信工程学院
电子设计自动化
具体下载步骤： ① 确定DE2开发板电源正常； ② 正确连接USB接口； ③ 设置RUN/PROG开关在PROG状态； ④ 从Quartus II 软件下载后缀名为.pof的可下载文件; ⑤ 下载完成后，将RUN/PROG开关拨向RUN并重启开 发板，实现新的系统功能。
信息与通信工程学院
电子设计自动化
DE2开发板的加电过程
将开发板上USB-BLASTER接口和电脑USB口 相连。(注意：要先安装ALTERA USB BLASTER 驱动) 将9V电源连入开发板电源接口。 将需要连接的图像显示终端、音频输入输出装 置连接开发板的对应接口。 将开发板上RUN/PROG开关拨向RUN端。 打开电源开关接通电源。
信息与通信工程学院
电子设计自动化
7段数码管 与FPGA 芯片管脚 连接情况
信息与通信工程学院
电子设计自动化
EDA实验装置DE2开发板介绍
DE2实验教学开发板基本情况 DE2开发板控制软件
DE2开发板使用方法
DE2开发板使用示例
信息与通信工程学院
电子设计自动化
例1：使用DE2开发板上的示例程序设置下载环境
信息与通信工程学院
电子设计自动化
参考程序：
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY part1 IS PORT(SW :IN STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR :OUT STD_LOGIC_VECTOR(17 DOWNTO 0)); END part1; ARCHITECTURE Behavior OF part1 IS BEGIN
附录DE2-115引脚表
SW[11]PIN_AB24Slide Switch[11]Depending on JP7 SW[12]PIN_AB23Slide Switch[12]Depending on JP7 SW[13]PIN_AA24Slide Switch[13]Depending on JP7 SW[14]PIN_AA23Slide Switch[14]Depending on JP7 SW[15]PIN_AA22Slide Switch[15]Depending on JP7 SW[16]PIN_Y24Slide Switch[16]Depending on JP7 SW[17]PIN_Y23Slide Switch[17]Depending on JP7表 2 按钮开关引脚配置Signal Name FPGA Pin No.Description I/O Standard KEY[0]PIN_M23Push-button[0]Depending on JP7KEY[1]PIN_M21Push-button[1]Depending on JP7KEY[2]PIN_N21Push-button[2]Depending on JP7KEY[3]PIN_R24Push-button[3]Depending on JP7表 3 LED引脚配置Signal Name FPGA Pin No.Description I/OS tandard LEDR[0]PIN_G19LED Red[0] 2.5VLEDR[1]PIN_F19LED Red[1] 2.5VLEDR[2]PIN_E19LED Red[2] 2.5VLEDR[3]PIN_F21LED Red[3] 2.5VLEDR[4]PIN_F18LED Red[4] 2.5VLEDR[5]PIN_E18LED Red[5] 2.5VLEDR[6]PIN_J19LED Red[6] 2.5VLEDR[7]PIN_H19LED Red[7] 2.5V LEDR[8]PIN_J17LED Red[8] 2.5V LEDR[9]PIN_G17LED Red[9] 2.5V LEDR[10]PIN_J15LED Red[10] 2.5V LEDR[11]PIN_H16LED Red[11] 2.5V LEDR[12]PIN_J16LED Red[12] 2.5V LEDR[13]PIN_H17LED Red[13] 2.5V LEDR[14]PIN_F15LED Red[14] 2.5V LEDR[15]PIN_G15LED Red[15] 2.5V LEDR[16]PIN_G16LED Red[16] 2.5V LEDR[17]PIN_H15LED Red[17] 2.5V LEDG[0]PIN_E21LED Green[0] 2.5V LEDG[1]PIN_E22LED Green[1] 2.5V LEDG[2]PIN_E25LED Green[2] 2.5V LEDG[3]PIN_E24LED Green[3] 2.5V LEDG[4]PIN_H21LED Green[4] 2.5V LEDG[5]PIN_G20LED Green[5] 2.5V LEDG[6]PIN_G22LED Green[6] 2.5V LEDG[7]PIN_G21LED Green[7] 2.5V LEDG[8]PIN_F17LED Green[8] 2.5V 表 4 七段数码管引脚配置Signal Na me FPGA Pin No.Description I/O StandardHEX0[0]PIN_G18Seven Segment Digit 0[0]2.5VHEX0[1]PIN_F22Seven Segment Digit 0[1] 2.5VHEX0[2]PIN_E17Seven Segment Digit 0[2] 2.5VHEX0[3]PIN_L26Seven Segment Digit 0[3]Depending onJP7HEX0[4]PIN_L25Seven Segment Digit 0[4]Depending on JP7HEX0[5]PIN_J22Seven Segment Digit 0[5]Depending on JP7HEX0[6]PIN_H22Seven Segment Digit 0[6]Depending on JP7HEX1[0]PIN_M24Seven Segment Digit 1[0]Depending on JP7HEX1[1]PIN_Y22Seven Segment Digit 1[1]Depending on JP7HEX1[2]PIN_W21Seven Segment Digit 1[2]Depending on JP7HEX1[3]PIN_W22Seven Segment Digit 1[3]Depending onJP7HEX1[4]PIN_W25Seven Segment Digit 1[4]Depending onJP7HEX1[5]PIN_U23Seven Segment Digit 1[5]Depending onJP7HEX1[6]PIN_U24Seven Segment Digit 1[6]Depending onJP7HEX2[0]PIN_AA25Seven Segment Digit 2[0]Depending onJP7HEX2[1]PIN_AA26Seven Segment Digit 2[1]Depending onJP7HEX2[2]PIN_Y25Seven Segment Digit 2[2]Depending on JP7HEX2[3]PIN_W26Seven Segment Digit 2[3]Depending on JP7HEX2[4]PIN_Y26Seven Segment Digit 2[4]Depending on JP7HEX2[5]PIN_W27Seven Segment Digit 2[5]Depending on JP7HEX2[6]PIN_W28Seven Segment Digit 2[6]Depending on JP7HEX3[0]PIN_V21Seven Segment Digit 3[0]Depending on JP7HEX3[1]PIN_U21Seven Segment Digit 3[1]Depending on JP7HEX3[2]PIN_AB20Seven Segment Digit 3[2]Depending onJP6HEX3[3]PIN_AA21Seven Segment Digit 3[3]Depending onJP6HEX3[4]PIN_AD24Seven Segment Digit 3[4]Depending onJP6HEX3[5]PIN_AF23Seven Segment Digit 3[5]Depending onJP6HEX3[6]PIN_Y19Seven Segment Digit 3[6]Depending onJP6HEX4[0]PIN_AB19Seven Segment Digit 4[0]Depending onJP6HEX4[1]PIN_AA19Seven Segment Digit 4[1]Depending on JP6HEX4[2]PIN_AG21Seven Segment Digit 4[2]Depending on JP6HEX4[3]PIN_AH21Seven Segment Digit 4[3]Depending on JP6HEX4[4]PIN_AE19Seven Segment Digit 4[4]Depending on JP6HEX4[5]PIN_AF19Seven Segment Digit 4[5]Depending on JP6HEX4[6]PIN_AE18Seven Segment Digit 4[6]Depending on JP6HEX5[0]PIN_AD18Seven Segment Digit 5[0]Depending on JP6HEX5[1]PIN_AC18Seven Segment Digit 5[1]Depending onJP6HEX5[2]PIN_AB18Seven Segment Digit 5[2]Depending onJP6HEX5[3]PIN_AH19Seven Segment Digit 5[3]Depending onJP6HEX5[4]PIN_AG19Seven Segment Digit 5[4]Depending onJP6HEX5[5]PIN_AF18Seven Segment Digit 5[5]Depending onJP6HEX5[6]PIN_AH18Seven Segment Digit 5[6]Depending onJP6HEX6[0]PIN_AA17Seven Segment Digit 6[0]Depending on JP6HEX6[1]PIN_AB16Seven Segment Digit 6[1]Depending on JP6HEX6[2]PIN_AA16Seven Segment Digit 6[2]Depending on JP6HEX6[3]PIN_AB17Seven Segment Digit 6[3]Depending on JP6HEX6[4]PIN_AB15Seven Segment Digit 6[4]Depending on JP6HEX6[5]PIN_AA15Seven Segment Digit 6[5]Depending on JP6HEX6[6]PIN_AC17Seven Segment Digit 6[6]Depending on JP6HEX7[0]PIN_AD17Seven Segment Digit 7[0]Depending onJP6HEX7[1]PIN_AE17Seven Segment Digit 7[1]Depending onJP6HEX7[2]PIN_AG17Seven Segment Digit 7[2]Depending onJP6HEX7[3]PIN_AH17Seven Segment Digit 7[3]Depending onJP6HEX7[4]PIN_AF17Seven Segment Digit 7[4]Depending on JP6HEX7[5]PIN_AG18Seven Segment Digit 7[5]Depending on JP6HEX7[6]PIN_AA14Seven Segment Digit 7[6] 3.3V表 5 时钟信号引脚配置信息Signal NameFPGA Pin N o.DescriptionI/O StandardCLOCK_50PIN_Y250 MHz clock input3.3V CLOCK2_50PIN_AG1450 MHz clock input 3.3V CLOCK3_50PIN_AG1550 MHz clock input Depending onJP6SMA_CLKOUT PIN_AE23External (SMA) clock o utputDepending onJP6SMA_CLKINPIN_AH14External (SMA) clock in put3.3V表 6 LCD 模块引脚配置Signal NameFPGAPinNo.DescriptionI/OLCD_DATA[7]PIN_M5LCD Data[7]StandardLCD_DATA[6]PIN_M3LCD Data[6]3.3VLCD_DATA[5]PIN_K2LCD Data[5]3.3VLCD_DATA[4]PIN_K1LCD Data[4]3.3VLCD_DATA[3]PIN_K7LCD Data[3]3.3VLCD_DATA[2]PIN_L2LCD Data[2]3.3VLCD_DATA[1]PIN_L1LCD Data[1]3.3VLCD_DATA[0]PIN_L3LCD Data[0]3.3VLCD_ENPIN_L4LCD Enable3.3VLCD_RWPIN_M1LCD Read/Write Select, 0 = Write, 1 = Read3.3VLCD_RSPIN_M2LCD Command/Data S elect, 0 = Command, 1= Data3.3VLCD_ONPIN_L5LCD Power ON/OFF3.3V LCD_BLONPIN_L6LCD Back Light ON/OF F 3.3V表 7 HSMC 接口引脚配置Signal NameFPGA Pin No.DescriptionI/O StandardHSMC_CLKIN0PIN_AH15Dedicated clock inputDepending on JP6HSMC_CLKIN_N1PIN_J28LVDS RX or C MOS I/O or diff erential clock inputDepending on JP7HSMC_CLKIN_N2PIN_Y28LVDS RX or C MOS I/O or diff erential clock inDepending on JP7putHSMC_CLKIN_P1PIN_J27LVDS RX or C MOS I/O or diff erential clock inputDepending on JP7HSMC_CLKIN_P2PIN_Y27LVDS RX or C MOS I/O or diff erential clock in put Depending on JP7HSMC_CLKOUT0PIN_AD28Dedicated clock output Depending on JP7HSMC_CLKOUT_N1PIN_G24LVDS TX or C MOS I/O or diff erential clock in put/output Depending on J P7HSMC_CLKOUT_N2PIN_V24LVDS TX or C MOS I/O or diff erential clock in put/output Depending on J P7HSMC_CLKOUT_P1PIN_G23LVDS TX or C MOS I/O or diff erential clock input/outputDepending on J P7HSMC_CLKOUT_P2PIN_V23LVDS TX or C MOS I/O or diff erential clock input/outputDepending on JP7HSMC_D[0]PIN_AE26LVDS TX or CDepending on JMOS I/O P7HSMC_D[1]PIN_AE28LVDS TX or CMOS I/O Depending on J P7HSMC_D[2]PIN_AE27LVDS TX or CMOS I/O Depending on J P7HSMC_D[3]PIN_AF27LVDS TX or CMOS I/O Depending on J P7HSMC_RX_D_N[0]PIN_F25LVDS RX bit 0n or CMOS I/O Depending on J P7HSMC_RX_D_N[1]PIN_C27LVDS RX bit 1n or CMOS I/O Depending on J P7HSMC_RX_D_N[2]PIN_E26LVDS RX bit 2n or CMOS I/O Depending on J P7HSMC_RX_D_N[3]PIN_G26LVDS RX bit 3n or CMOS I/O Depending on J P7HSMC_RX_D_N[4]PIN_H26LVDS RX bit 4n or CMOS I/O Depending on J P7HSMC_RX_D_N[5]PIN_K26LVDS RX bit 5n or CMOS I/O Depending on J P7HSMC_RX_D_N[6]PIN_L24LVDS RX bit 6n or CMOS I/O Depending on J P7HSMC_RX_D_N[7]PIN_M26LVDS RX bit 7n or CMOS I/O Depending on J P7HSMC_RX_D_N[8]PIN_R26LVDS RX bit 8n or CMOS I/O Depending on J P7HSMC_RX_D_N[9]PIN_T26LVDS RX bit 9n or CMOS I/O Depending on J P7HSMC_RX_D_N[10]PIN_U26LVDS RX bit 10n or CMOS I/O Depending on J P7HSMC_RX_D_N[11]PIN_L22LVDS RX bit 11n or CMOS I/O Depending on J P7HSMC_RX_D_N[12]PIN_N26LVDS RX bit 12n or CMOS I/O Depending on J P7HSMC_RX_D_N[13]PIN_P26LVDS RX bit 13n or CMOS I/O Depending on J P7HSMC_RX_D_N[14]PIN_R21LVDS RX bit 14n or CMOS I/O Depending on J P7HSMC_RX_D_N[15]PIN_R23LVDS RX bit 15n or CMOS I/O Depending on J P7HSMC_RX_D_N[16]PIN_T22LVDS RX bit 16n or CMOS I/O Depending on J P7HSMC_RX_D_P[0]PIN_F24LVDS RX bit 0or CMOS I/O Depending on J P7HSMC_RX_D_P[1]PIN_D26LVDS RX bit 1or CMOS I/O Depending on J P7HSMC_RX_D_P[2]PIN_F26LVDS RX bit 2or CMOS I/O Depending on J P7HSMC_RX_D_P[3]PIN_G25LVDS RX bit 3or CMOS I/O Depending on J P7HSMC_RX_D_P[4]PIN_H25LVDS RX bit 4or CMOS I/O Depending on J P7HSMC_RX_D_P[5]PIN_K25LVDS RX bit 5or CMOS I/O Depending on J P7HSMC_RX_D_P[6]PIN_L23LVDS RX bit 6or CMOS I/O Depending on J P7HSMC_RX_D_P[7]PIN_M25LVDS RX bit 7or CMOS I/O Depending on J P7HSMC_RX_D_P[8]PIN_R25LVDS RX bit 8or CMOS I/O Depending on J P7HSMC_RX_D_P[9]PIN_T25LVDS RX bit 9or CMOS I/O Depending on J P7HSMC_RX_D_P[10]PIN_U25LVDS RX bit 10 or CMOS I/O Depending on J P7HSMC_RX_D_P[11]PIN_L21LVDS RX bit 11 or CMOS I/O Depending on J P7HSMC_RX_D_P[12]PIN_N25LVDS RX bit 12 or CMOS I/O Depending on J P7HSMC_RX_D_P[13]PIN_P25LVDS RX bit 13 or CMOS I/O Depending on J P7HSMC_RX_D_P[14]PIN_P21LVDS RX bit 14 or CMOS I/O Depending on J P7HSMC_RX_D_P[15]PIN_R22LVDS RX bit 15 or CMOS I/O Depending on J P7HSMC_RX_D_P[16]PIN_T21LVDS RX bit 16 or CMOS I/O Depending on J P7HSMC_TX_D_N[0]PIN_D28LVDS TX bit 0n or CMOS I/O Depending on J P7HSMC_TX_D_N[1]PIN_E28LVDS TX bit 1n or CMOS I/O Depending on J P7HSMC_TX_D_N[2]PIN_F28LVDS TX bit 2n or CMOS I/O Depending on J P7HSMC_TX_D_N[3]PIN_G28LVDS TX bit 3n or CMOS I/O Depending on J P7HSMC_TX_D_N[4]PIN_K28LVDS TX bit 4n or CMOS I/O Depending on J P7HSMC_TX_D_N[5]PIN_M28LVDS TX bit 5n or CMOS I/O Depending on J P7HSMC_TX_D_N[6]PIN_K22LVDS TX bit 6n or CMOS I/O Depending on J P7HSMC_TX_D_N[7]PIN_H24LVDS TX bit 7n or CMOS I/O Depending on J P7HSMC_TX_D_N[8]PIN_J24LVDS TX bit 8n or CMOS I/O Depending on J P7HSMC_TX_D_N[9]PIN_P28LVDS TX bit 9n or CMOS I/O Depending on J P7HSMC_TX_D_N[10]PIN_J26LVDS TX bit 10n or CMOS I/O Depending on J P7HSMC_TX_D_N[11]PIN_L28LVDS TX bit 11n or CMOS I/Depending on J P7OHSMC_TX_D_N[12]PIN_V26LVDS TX bit 12n or CMOS I/O Depending on J P7HSMC_TX_D_N[13]PIN_R28LVDS TX bit 13n or CMOS I/O Depending on J P7HSMC_TX_D_N[14]PIN_U28LVDS TX bit 14n or CMOS I/O Depending on J P7HSMC_TX_D_N[15]PIN_V28LVDS TX bit 15n or CMOS I/O Depending on J P7HSMC_TX_D_N[16]PIN_V22LVDS TX bit 16n or CMOS I/O Depending on J P7HSMC_TX_D_P[0]PIN_D27LVDS TX bit 0or CMOS I/O Depending on J P7HSMC_TX_D_P[1]PIN_E27LVDS TX bit 1or CMOS I/O Depending on J P7HSMC_TX_D_P[2]PIN_F27LVDS TX bit 2or CMOS I/O Depending on J P7HSMC_TX_D_P[3]PIN_G27LVDS TX bit 3or CMOS I/O Depending on J P7HSMC_TX_D_P[4]PIN_K27LVDS TX bit 4or CMOS I/O Depending on J P7HSMC_TX_D_P[5]PIN_M27LVDS TX bit 5 Depending on Jor CMOS I/O P7HSMC_TX_D_P[6]PIN_K21LVDS TX bit 6or CMOS I/O Depending on J P7HSMC_TX_D_P[7]PIN_H23LVDS TX bit 7or CMOS I/O Depending on J P7HSMC_TX_D_P[8]PIN_J23LVDS TX bit 8or CMOS I/O Depending on J P7HSMC_TX_D_P[9]PIN_P27LVDS TX bit 9or CMOS I/O Depending on J P7HSMC_TX_D_P[10]PIN_J25LVDS TX bit 10 or CMOS I/O Depending on J P7HSMC_TX_D_P[11]PIN_L27LVDS TX bit 11 or CMOS I/O Depending on J P7HSMC_TX_D_P[12]PIN_V25LVDS TX bit 12 or CMOS I/O Depending on J P7HSMC_TX_D_P[13]PIN_R27LVDS TX bit 13 or CMOS I/O Depending on J P7HSMC_TX_D_P[14]PIN_U27LVDS TX bit 14 or CMOS I/O Depending on J P7HSMC_TX_D_P[15]PIN_V27LVDS TX bit 15 or CMOS I/O Depending on J P7HSMC_TX_D_P[16]PIN_U22LVDS TX bit 16 or CMOS I/O Depending on J P7表8 GPIO 引脚配置信息Signal Nam e FPGA Pin No.Description I/O StandardGPIO[0]PIN_AB22GPIO Connection DATA[0]Depending on JP 6GPIO[1]PIN_AC15GPIO Connection DATA[1]Depending on JP 6GPIO[2]PIN_AB21GPIO Connection DATA[2]Depending on JP 6GPIO[3]PIN_Y17GPIO Connection DATA[3]Depending on JP 6GPIO[4]PIN_AC21GPIO Connection DATA[4]Depending on JP 6GPIO[5]PIN_Y16GPIO Connection DATA[5]Depending on JP 6GPIO[6]PIN_AD21GPIO Connection DATA[6]Depending on JP 6GPIO[7]PIN_AE16GPIO Connection DATA[7]Depending on JP 6GPIO[8]PIN_AD15GPIO Connection DATA[8]Depending on JP 6GPIO[9]PIN_AE15GPIO Connection DATA[9]Depending on JP 6GPIO[10]PIN_AC19GPIO Connection DATA[10]Depending on JP 6GPIO[11]PIN_AF16GPIO Connection DATA[11]Depending on JP 6GPIO[12]PIN_AD19GPIO Connection DATA[12]Depending on JP 6GPIO[13]PIN_AF15GPIO Connection DATA[13]Depending on JP 6GPIO[14]PIN_AF24GPIO Connection DATA[14]Depending on JP 6GPIO[15]PIN_AE21GPIO Connection DATA[15]Depending on JP 6GPIO[16]PIN_AF25GPIO Connection DATA[16]Depending on JP 6GPIO[17]PIN_AC22GPIO Connection DATA[17]Depending on JP 6GPIO[18]PIN_AE22GPIO Connection DATA[18]Depending on JP 6GPIO[19]PIN_AF21GPIO Connection DATA[19]Depending on JP 6GPIO[20]PIN_AF22GPIO Connection DATA[20]Depending on JP 6GPIO[21]PIN_AD22GPIO Connection DATA[21]Depending on JP 6GPIO[22]PIN_AG25GPIO Connection DATA[22]Depending on JP 6GPIO[23]PIN_AD25GPIO Connection DATA[23]Depending on JP 6GPIO[24]PIN_AH25GPIO Connection DATA[24]Depending on JP 6GPIO[25]PIN_AE25GPIO Connection DATA[25]Depending on JP 6GPIO[26]PIN_AG22GPIO Connection DATA[26]Depending on JP 6GPIO[27]PIN_AE24GPIO Connection DATA[27]Depending on JP 6GPIO[28]PIN_AH22GPIO Connection DATA[28]Depending on JP 6GPIO[29]PIN_AF26GPIO Connection DATA[29]Depending on JP 6GPIO[30]PIN_AE20GPIO Connection DATA[30]Depending on JP 6GPIO[31]PIN_AG23GPIO Connection DATA[31]Depending on JP 6GPIO[32]PIN_AF20GPIO Connection DATA[32]Depending on JP 6GPIO[33]PIN_AH26GPIO Connection DATA[33]Depending on JP 6GPIO[34]PIN_AH23GPIO Connection DATA[34]Depending on JP 6GPIO[35]PIN_AG26GPIO Connection DATA[35]Depending on JP 6表9 扩展接口引脚配置信息Signal Name FPGA Pin No.Description I/O Standard EX_IO[0]PIN_J10Extended IO[0] 3.3VEX_IO[1]PIN_J14Extended IO[1] 3.3VEX_IO[2]PIN_H13Extended IO[2] 3.3VEX_IO[3]PIN_H14Extended IO[3] 3.3VEX_IO[4]PIN_F14Extended IO[4] 3.3VEX_IO[5]PIN_E10Extended IO[5] 3.3VEX_IO[6]PIN_D9Extended IO[6] 3.3V表10 ADV7123 引脚配置Signal Name FPGA Pin No.Description I/O Standard VGA_R[0]PIN_E12VGA Red[0] 3.3VVGA_R[1]PIN_E11VGA Red[1] 3.3VVGA_R[2]PIN_D10VGA Red[2] 3.3VVGA_R[3]PIN_F12VGA Red[3] 3.3VVGA_R[4]PIN_G10VGA Red[4] 3.3VVGA_R[5]PIN_J12VGA Red[5] 3.3VVGA_R[6]PIN_H8VGA Red[6] 3.3VVGA_R[7]PIN_H10VGA Red[7] 3.3VVGA_G[0]PIN_G8VGA Green[0] 3.3VVGA_G[1]PIN_G11VGA Green[1] 3.3VVGA_G[2]PIN_F8VGA Green[2] 3.3VVGA_G[3]PIN_H12VGA Green[3] 3.3VVGA_G[4]PIN_C8VGA Green[4] 3.3VVGA_G[5]PIN_B8VGA Green[5] 3.3VVGA_G[6]PIN_F10VGA Green[6] 3.3VVGA_G[7]PIN_C9VGA Green[7] 3.3VVGA_B[0]PIN_B10VGA Blue[0] 3.3VVGA_B[1]PIN_A10VGA Blue[1] 3.3VVGA_B[2]PIN_C11VGA Blue[2] 3.3VVGA_B[3]PIN_B11VGA Blue[3] 3.3VVGA_B[4]PIN_A11VGA Blue[4] 3.3VVGA_B[5]PIN_C12VGA Blue[5] 3.3VVGA_B[6]PIN_D11VGA Blue[6] 3.3VVGA_B[7]PIN_D12VGA Blue[7] 3.3VVGA_CLK PIN_A12VGA Clock 3.3VVGA_BLANK_N PIN_F11VGA BLANK 3.3VVGA_HS PIN_G13VGA H_SYNC 3.3VVGA_VS PIN_C13VGA V_SYNC 3.3VVGA_SYNC_N PIN_C10VGA SYNC 3.3V表11 音频编解码芯片引脚配置Signal Name FPGA Pin No.Description I/O Standard3.3VAUD_ADCLRCK PIN_C2Audio CODEC ADC LR ClockAUD_ADCDAT PIN_D2Audio CODEC ADC Data 3.3V3.3VAUD_DACLRCK PIN_E3Audio CODEC DAC LR ClockAUD_DACDAT PIN_D1Audio CODEC DAC Data 3.3VAUD_XCK PIN_E1Audio CODEC Chip Clock 3.3V3.3VAUD_BCLK PIN_F2Audio CODEC Bit-StreamClockI2C_SCLK PIN_B7I2C Clock 3.3VI2C_SDAT PIN_A8I2C Data 3.3V表12 RS-232 引脚配置Signal Name FPGA Pin No.Description I/O Standard UART_RXD PIN_G12UART Receiver 3.3VUART_TXD PIN_G9UART Transmitter 3.3VUART_CTS PIN_G14UART Clear to Send 3.3VUART_RTS PIN_J13UART Request to Send3.3V表13 PS/2 引脚配置Signal Name FPGA Pin No.Description I/O StandardPS2_CLK PIN_G6PS/2 Clock 3.3VPS2_DAT PIN_H5PS/2 Data 3.3VPS2_CLK2PIN_G5PS/2 Clock (reserved for second PS/2 device)3.3VPS2_DAT2PIN_F5PS/2 Data (reserved for second PS/2 device)3.3V表14 千兆以太网芯片引脚配置Signal Name FPGA Pin No.Description I/O StandardE NET0_GTX_CLK PIN_A17GMII Transmit Clock 12.5VENET0_INT_N PIN_A21Interrupt open drain2.5Voutput 13.3V ENET0_LINK100PIN_C14Parallel LED outputof 100BASE-TX link12.5V ENET0_MDC PIN_C20Management data clock reference 1ENET0_MDIO PIN_B21Management data 12.5V2.5V ENET0_RST_N PIN_C19Hardware reset signal 1ENET0_RX_CLK PIN_A15GMII and MII receiv2.5Ve clock 12.5V ENET0_RX_COL PIN_E15GMII and MII collision 1ENET0_RX_CRS PIN_D15GMII and MII carrie2.5Vr sense 12.5V ENET0_RX_DATA[0]PIN_C16GMII and MII receive data[0] 12.5V ENET0_RX_DATA[1]PIN_D16GMII and MII receive data[1] 12.5V ENET0_RX_DATA[2]PIN_D17GMII and MII receive data[2] 12.5V ENET0_RX_DATA[3]PIN_C15GMII and MII receive data[3] 12.5V ENET0_RX_DV PIN_C17GMII and MII receive data valid 1ENET0_RX_ER PIN_D18GMII and MII receiv2.5Ve error 1ENET0_TX_CLK PIN_B17MII transmit clock 12.5V ENET0_TX_DATA[0]PIN_C18MII transmit data[0]2.5V12.5V ENET0_TX_DATA[1]PIN_D19MII transmit data[1]12.5V ENET0_TX_DATA[2]PIN_A19MII transmit data[2]12.5V ENET0_TX_DATA[3]PIN_B19MII transmit data[3]12.5V ENET0_TX_EN PIN_A18GMII and MII transmit enable 12.5V ENET0_TX_ER PIN_B18GMII and MII transmit error 1ENET1_GTX_CLK PIN_C23GMII Transmit Cloc2.5Vk 22.5V ENET1_INT_N PIN_D24Interrupt open drainoutput 22.5V ENET1_LINK100PIN_D13Parallel LED outputof 100BASE-TX link22.5V ENET1_MDC PIN_D23Management data clock reference 2ENET1_MDIO PIN_D25Management data 22.5V ENET1_RST_N PIN_D22Hardware reset sig2.5Vnal 22.5V ENET1_RX_CLK PIN_B15GMII and MII receive clock 22.5V ENET1_RX_COL PIN_B22GMII and MII collision 22.5V ENET1_RX_CRS PIN_D20GMII and MII carrier sense 22.5V ENET1_RX_DATA[0]PIN_B23GMII and MII receive data[0] 22.5V ENET1_RX_DATA[1]PIN_C21GMII and MII receive data[1] 22.5V ENET1_RX_DATA[2]PIN_A23GMII and MII receive data[2] 2ENET1_RX_DATA[3]PIN_D21GMII and MII receiv2.5Ve data[3] 2ENET1_RX_DV PIN_A22GMII and MII receiv2.5Ve data valid 22.5V ENET1_RX_ER PIN_C24GMII and MII receive error 2ENET1_TX_CLK PIN_C22MII transmit clock 22.5V2.5V ENET1_TX_DATA[0]PIN_C25MII transmit data[0]2ENET1_TX_DATA[1]PIN_A26MII transmit data[1]2.5V2ENET1_TX_DATA[2]PIN_B26MII transmit data[2]2.5V2ENET1_TX_DATA[3]PIN_C26MII transmit data[3]2.5V22.5V ENET1_TX_EN PIN_B25GMII and MII transmit enable 22.5V ENET1_TX_ER PIN_A25GMII and MII transmit error 2ENETCLK_25PIN_A14Ethernet clock sour3.3Vce表15 TV 解码芯片引脚配置Signal Name FPGA Pin No.Description I/O Standard TD_ DATA [0]PIN_E8TV Decoder Data[0] 3.3VTD_ DATA [1]PIN_A7TV Decoder Data[1] 3.3VTD_ DATA [2]PIN_D8TV Decoder Data[2] 3.3VTD_ DATA [3]PIN_C7TV Decoder Data[3] 3.3VTD_ DATA [4]PIN_D7TV Decoder Data[4] 3.3VTD_ DATA [5]PIN_D6TV Decoder Data[5] 3.3VTD_ DATA [6]PIN_E7TV Decoder Data[6] 3.3VTD_ DATA [7]PIN_F7TV Decoder Data[7] 3.3VTD_HS PIN_E5TV Decoder H_SYNC 3.3VTD_VS PIN_E4TV Decoder V_SYNC 3.3V3.3VTD_CLK27PIN_B14TV Decoder Clock Input.TD_RESET_N PIN_G7TV Decoder Reset 3.3VI2C_SCLK PIN_B7I2C Clock 3.3VI2C_SDAT PIN_A8I2C Data 3.3V 表16 USB (ISP1362)引脚配置Signal Name FPGA Pin No.Description I/O StandardOTG_ADDR[0]PIN_H7ISP1362 Address[0] 3.3V OTG_ADDR[1]PIN_C3ISP1362 Address[1] 3.3V OTG_DATA[0]PIN_J6ISP1362 Data[0] 3.3V OTG_DATA[1]PIN_K4ISP1362 Data[1] 3.3V OTG_DATA[2]PIN_J5ISP1362 Data[2] 3.3V OTG_DATA[3]PIN_K3ISP1362 Data[3] 3.3V OTG_DATA[4]PIN_J4ISP1362 Data[4] 3.3V OTG_DATA[5]PIN_J3ISP1362 Data[5] 3.3V OTG_DATA[6]PIN_J7ISP1362 Data[6] 3.3V OTG_DATA[7]PIN_H6ISP1362 Data[7] 3.3V OTG_DATA[8]PIN_H3ISP1362 Data[8] 3.3V OTG_DATA[9]PIN_H4ISP1362 Data[9] 3.3V OTG_DATA[10]PIN_G1ISP1362 Data[10] 3.3V OTG_DATA[11]PIN_G2ISP1362 Data[11] 3.3V OTG_DATA[12]PIN_G3ISP1362 Data[12] 3.3V OTG_DATA[13]PIN_F1ISP1362 Data[13] 3.3V OTG_DATA[14]PIN_F3ISP1362 Data[14] 3.3V OTG_DATA[15]PIN_G4ISP1362 Data[15] 3.3V OTG_CS_N PIN_A3ISP1362 Chip Select 3.3VOTG_RD_N PIN_B3ISP1362 Read 3.3V OTG_WR_N PIN_A4ISP1362 Write 3.3V OTG_RST_N PIN_C5ISP1362 Reset 3.3V OTG_INT[0]PIN_A6ISP1362 Interrupt 0 3.3V OTG_INT[1]PIN_D5ISP1362 Interrupt 1 3.3V OTG_DACK_N[0]PIN_C4ISP1362 DMA Acknowledge 0 3.3V OTG_DACK_N[1]PIN_D4ISP1362 DMA Acknowledge 1 3.3V OTG_DREQ[0]PIN_J1ISP1362 DMA Request 0 3.3V OTG_DREQ[1]PIN_B4ISP1362 DMA Request 1 3.3V3.3V OTG_FSPEED PIN_C6USB Full Speed, 0 = Enable, Z= Disable3.3V OTG_LSPEED PIN_B6USB Low Speed, 0 = Enable, Z= Disable表17 IR 引脚配置Description I/O StandardSignal Name FPGA Pin No.IRDA_RXD PIN_Y15IR Receiver 3.3V表18 SRAM 引脚配置Signal Name FPGA Pin No.Description I/O Standard SRAM_ADDR[0]PIN_AB7SRAM Address[0] 3.3VSRAM_ADDR[1]PIN_AD7SRAM Address[1] 3.3VSRAM_ADDR[2]PIN_AE7SRAM Address[2] 3.3VSRAM_ADDR[3]PIN_AC7SRAM Address[3] 3.3VSRAM_ADDR[4]PIN_AB6SRAM Address[4] 3.3V SRAM_ADDR[5]PIN_AE6SRAM Address[5] 3.3V SRAM_ADDR[6]PIN_AB5SRAM Address[6] 3.3V SRAM_ADDR[7]PIN_AC5SRAM Address[7] 3.3V SRAM_ADDR[8]PIN_AF5SRAM Address[8] 3.3V SRAM_ADDR[9]PIN_T7SRAM Address[9] 3.3V SRAM_ADDR[10]PIN_AF2SRAM Address[10] 3.3V SRAM_ADDR[11]PIN_AD3SRAM Address[11] 3.3V SRAM_ADDR[12]PIN_AB4SRAM Address[12] 3.3V SRAM_ADDR[13]PIN_AC3SRAM Address[13] 3.3V SRAM_ADDR[14]PIN_AA4SRAM Address[14] 3.3V SRAM_ADDR[15]PIN_AB11SRAM Address[15] 3.3V SRAM_ADDR[16]PIN_AC11SRAM Address[16] 3.3V SRAM_ADDR[17]PIN_AB9SRAM Address[17] 3.3V SRAM_ADDR[18]PIN_AB8SRAM Address[18] 3.3V SRAM_ADDR[19]PIN_T8SRAM Address[19] 3.3V SRAM_DQ[0]PIN_AH3SRAM Data[0] 3.3V SRAM_DQ[1]PIN_AF4SRAM Data[1] 3.3V SRAM_DQ[2]PIN_AG4SRAM Data[2] 3.3V SRAM_DQ[3]PIN_AH4SRAM Data[3] 3.3V SRAM_DQ[4]PIN_AF6SRAM Data[4] 3.3V SRAM_DQ[5]PIN_AG6SRAM Data[5] 3.3V SRAM_DQ[6]PIN_AH6SRAM Data[6] 3.3VSRAM_DQ[7]PIN_AF7SRAM Data[7] 3.3VSRAM_DQ[8]PIN_AD1SRAM Data[8] 3.3VSRAM_DQ[9]PIN_AD2SRAM Data[9] 3.3VSRAM_DQ[10]PIN_AE2SRAM Data[10] 3.3VSRAM_DQ[11]PIN_AE1SRAM Data[11] 3.3VSRAM_DQ[12]PIN_AE3SRAM Data[12] 3.3VSRAM_DQ[13]PIN_AE4SRAM Data[13] 3.3VSRAM_DQ[14]PIN_AF3SRAM Data[14] 3.3VSRAM_DQ[15]PIN_AG3SRAM Data[15] 3.3VSRAM_OE_N PIN_AD5SRAM Output EnableSRAM_WE_N PIN_AE8SRAM Write EnableSRAM_CE_N PIN_AF8SRAM Chip SelectSRAM_LB_N PIN_AD4SRAM Lower Byte StrobeSRAM_UB_N PIN_AC4SRAM Higher Byte Strobe表19 SDRAM 引脚配置Signal Name FPGA Pin No.Description I/O Standard DRAM_ADDR[0]PIN_R6SDRAM Address[0] 3.3VDRAM_ADDR[1]PIN_V8SDRAM Address[1] 3.3VDRAM_ADDR[2]PIN_U8SDRAM Address[2] 3.3VDRAM_ADDR[3]PIN_P1SDRAM Address[3] 3.3VDRAM_ADDR[4]PIN_V5SDRAM Address[4] 3.3VDRAM_ADDR[5]PIN_W8SDRAM Address[5] 3.3V DRAM_ADDR[6]PIN_W7SDRAM Address[6] 3.3V DRAM_ADDR[7]PIN_AA7SDRAM Address[7] 3.3V DRAM_ADDR[8]PIN_Y5SDRAM Address[8] 3.3V DRAM_ADDR[9]PIN_Y6SDRAM Address[9] 3.3V DRAM_ADDR[10]PIN_R5SDRAM Address[10] 3.3V DRAM_ADDR[11]PIN_AA5SDRAM Address[11] 3.3V DRAM_ADDR[12]PIN_Y7SDRAM Address[12] 3.3V DRAM_DQ[0]PIN_W3SDRAM Data[0] 3.3V DRAM_DQ[1]PIN_W2SDRAM Data[1] 3.3V DRAM_DQ[2]PIN_V4SDRAM Data[2] 3.3V DRAM_DQ[3]PIN_W1SDRAM Data[3] 3.3V DRAM_DQ[4]PIN_V3SDRAM Data[4] 3.3V DRAM_DQ[5]PIN_V2SDRAM Data[5] 3.3V DRAM_DQ[6]PIN_V1SDRAM Data[6] 3.3V DRAM_DQ[7]PIN_U3SDRAM Data[7] 3.3V DRAM_DQ[8]PIN_Y3SDRAM Data[8] 3.3V DRAM_DQ[9]PIN_Y4SDRAM Data[9] 3.3V DRAM_DQ[10]PIN_AB1SDRAM Data[10] 3.3V DRAM_DQ[11]PIN_AA3SDRAM Data[11] 3.3V DRAM_DQ[12]PIN_AB2SDRAM Data[12] 3.3V DRAM_DQ[13]PIN_AC1SDRAM Data[13] 3.3V DRAM_DQ[14]PIN_AB3SDRAM Data[14] 3.3VDRAM_DQ[15]PIN_AC2SDRAM Data[15] 3.3V SRAM_OE_N PIN_AD5SRAM Output Enable 3.3V SRAM_WE_N PIN_AE8SRAM Write Enable 3.3V SRAM_CE_N PIN_AF8SRAM Chip Select 3.3V SRAM_LB_N PIN_AD4SRAM Lower Byte Strobe3.3VSRAM_UB_N PIN_AC4SRAM Higher Byte Strobe3.3V 表20 SDRAM 引脚配置Signal Name FPGA Pin No.Description I/O StandardDRAM_ADDR[0]PIN_R6SDRAM Address[0] 3.3V DRAM_ADDR[1]PIN_V8SDRAM Address[1] 3.3V DRAM_ADDR[2]PIN_U8SDRAM Address[2] 3.3V DRAM_ADDR[3]PIN_P1SDRAM Address[3] 3.3V DRAM_ADDR[4]PIN_V5SDRAM Address[4] 3.3V DRAM_ADDR[5]PIN_W8SDRAM Address[5] 3.3V DRAM_ADDR[6]PIN_W7SDRAM Address[6] 3.3V DRAM_ADDR[7]PIN_AA7SDRAM Address[7] 3.3V DRAM_ADDR[8]PIN_Y5SDRAM Address[8] 3.3V DRAM_ADDR[9]PIN_Y6SDRAM Address[9] 3.3V DRAM_ADDR[10]PIN_R5SDRAM Address[10] 3.3V DRAM_ADDR[11]PIN_AA5SDRAM Address[11] 3.3V DRAM_ADDR[12]PIN_Y7SDRAM Address[12] 3.3VDRAM_DQ[0]PIN_W3SDRAM Data[0] 3.3V DRAM_DQ[1]PIN_W2SDRAM Data[1] 3.3V DRAM_DQ[2]PIN_V4SDRAM Data[2] 3.3V DRAM_DQ[3]PIN_W1SDRAM Data[3] 3.3V DRAM_DQ[4]PIN_V3SDRAM Data[4] 3.3V DRAM_DQ[5]PIN_V2SDRAM Data[5] 3.3V DRAM_DQ[6]PIN_V1SDRAM Data[6] 3.3V DRAM_DQ[7]PIN_U3SDRAM Data[7] 3.3V DRAM_DQ[8]PIN_Y3SDRAM Data[8] 3.3V DRAM_DQ[9]PIN_Y4SDRAM Data[9] 3.3V DRAM_DQ[10]PIN_AB1SDRAM Data[10] 3.3V DRAM_DQ[11]PIN_AA3SDRAM Data[11] 3.3V DRAM_DQ[12]PIN_AB2SDRAM Data[12] 3.3V DRAM_DQ[13]PIN_AC1SDRAM Data[13] 3.3V DRAM_DQ[14]PIN_AB3SDRAM Data[14] 3.3V DRAM_DQ[15]PIN_AC2SDRAM Data[15] 3.3V DRAM_DQ[16]PIN_M8SDRAM Data[16] 3.3V DRAM_DQ[17]PIN_L8SDRAM Data[17] 3.3V DRAM_DQ[18]PIN_P2SDRAM Data[18] 3.3V DRAM_DQ[19] PIN_N3SDRAM Data[19] 3.3V DRAM_DQ[20]PIN_N4SDRAM Data[20] 3.3V DRAM_DQ[21]PIN_M4SDRAM Data[21] 3.3V DRAM_DQ[22]PIN_M7SDRAM Data[22] 3.3VDRAM_DQ[23]PIN_L7SDRAM Data[23] 3.3V DRAM_DQ[24]PIN_U5SDRAM Data[24] 3.3V DRAM_DQ[25]PIN_R7SDRAM Data[25] 3.3V DRAM_DQ[26]PIN_R1SDRAM Data[26] 3.3V DRAM_DQ[27]PIN_R2SDRAM Data[27] 3.3V DRAM_DQ[28]PIN_R3SDRAM Data[28] 3.3V DRAM_DQ[29]PIN_T3SDRAM Data[29] 3.3V DRAM_DQ[30]PIN_U4SDRAM Data[30] 3.3V DRAM_DQ[31]PIN_U1SDRAM Data[31] 3.3V DRAM_BA[0]PIN_U7SDRAM Bank Address[0] 3.3V DRAM_BA[1]PIN_R4SDRAM Bank Address[1] 3.3V DRAM_DQM[0]PIN_U2SDRAM byte Data Mask[0] 3.3V DRAM_DQM[1]PIN_W4SDRAM byte Data Mask[1] 3.3V DRAM_DQM[2]PIN_K8SDRAM byte Data Mask[2] 3.3V DRAM_DQM[3]PIN_N8SDRAM byte Data Mask[3] 3.3V DRAM_RAS_N PIN_U6SDRAM Row Address Strobe 3.3V3.3V DRAM_CAS_N PIN_V7SDRAM Column Address StrobeDRAM_CKE PIN_AA6SDRAM Clock Enable 3.3V DRAM_CLK PIN_AE5SDRAM Clock 3.3V DRAM_WE_N PIN_V6SDRAM Write Enable 3.3V DRAM_CS_N PIN_T4SDRAM Chip Select 3.3V 表21 Flash 引脚配置Signal Name FPGA Pin No.Description I/O StandardFL_ADDR[0]PIN_AG12FLASH Address[0] 3.3V FL_ADDR[1]PIN_AH7FLASH Address[1] 3.3V FL_ADDR[2]PIN_Y13FLASH Address[2] 3.3V FL_ADDR[3]PIN_Y14FLASH Address[3] 3.3V FL_ADDR[4]PIN_Y12FLASH Address[4] 3.3V FL_ADDR[5]PIN_AA13FLASH Address[5] 3.3V FL_ADDR[6]PIN_AA12FLASH Address[6] 3.3V FL_ADDR[7]PIN_AB13FLASH Address[7] 3.3V FL_ADDR[8]PIN_AB12FLASH Address[8] 3.3V FL_ADDR[9]PIN_AB10FLASH Address[9] 3.3V FL_ADDR[10]PIN_AE9FLASH Address[10] 3.3V FL_ADDR[11]PIN_AF9FLASH Address[11] 3.3V FL_ADDR[12]PIN_AA10FLASH Address[12] 3.3V FL_ADDR[13]PIN_AD8FLASH Address[13] 3.3V FL_ADDR[14]PIN_AC8FLASH Address[14] 3.3V FL_ADDR[15]PIN_Y10FLASH Address[15] 3.3V FL_ADDR[16]PIN_AA8FLASH Address[16] 3.3V FL_ADDR[17]PIN_AH12FLASH Address[17] 3.3V FL_ADDR[18]PIN_AC12FLASH Address[18] 3.3V FL_ADDR[19]PIN_AD12FLASH Address[19] 3.3V FL_ADDR[20]PIN_AE10FLASH Address[20] 3.3V FL_ADDR[21]PIN_AD10FLASH Address[21] 3.3V。
基于DE2-115开发板的FPGA入门设计实验
基于DE2-115开发板的FPGA入门设计实验1、Lab1: 4位加法器、减法器的设计1.1 摘要在文件add_sub里面的工程文件operation_4.v为顶层文件，该顶层文件包含了三个子模块，分别为数码管显示模块，4位带进位的二进制加法器模块和4位带借位的二进制减法器模块，最后通过DE2-115开发板显示实验结果。
1.2 程序1）add_4bits.v 加法器module adder_4bits(input clk,input rst_n,input [3:0] x,input [3:0] y,output reg [3:0] sum,output reg carry_out //溢出位);always@(posedge clk or negedge rst_n)beginif(!rst_n){carry_out, sum} <= 0;else{carry_out, sum} = x + y;endendmodule2）substractor_4bits.v减法器module subtractor_4bits(input clk,input rst_n,input [3:0] x,input [3:0] y,output r eg [3:0] sub,output r eg borrow_out);always@(posedge clk or negedge rst_n) beginif(!rst_n){borrow_out, sub} <= 0;elsebeginif(x >= y){borrow_out, sub} = {1'b0, x - y};else{borrow_out, sub} = {1'b1, x - y};endendendmodule3)seg7_lut.v 数码管显示译码模块module Seg7_lut(input [3:0] iDIG,output r eg [6:0] oSEG);always @(iDIG)begincase(iDIG)4'h1: oSEG = 7'b1111001; // ---t----4'h2: oSEG = 7'b0100100; // | |4'h3: oSEG = 7'b0110000; // lt rt4'h4: oSEG = 7'b0011001; // | |4'h5: oSEG = 7'b0010010; // ---m----4'h6: oSEG = 7'b0000010; // | |4'h7: oSEG = 7'b1111000; // lb rb4'h8: oSEG = 7'b0000000; // | |4'h9: oSEG = 7'b0011000; // ---b----4'ha: oSEG = 7'b0001000;4'hb: oSEG = 7'b0000011;4'hc: oSEG = 7'b1000110;4'hd: oSEG = 7'b0100001;4'he: oSEG = 7'b0000110;4'hf: oSEG = 7'b0001110;4'h0: oSEG = 7'b1000000;endcaseendendmodule1.3 结果本设计通过Verilog HDL硬件描述语言。
Altera DE2-70多媒体开发板解析
Altera DE2-70多媒体开发板这里主要介绍Altera DE2-70多媒体开发板的外观和设计特性。
一、 配置和组件图1是Altera DE2-70多媒体开发板的外观图，描述了Altera DE2-70多媒体开发板的外观，指明了每个接口和开关组件的位置。
Altera DE2-70多媒体开发板具有很多特性，可以让用户实现从简单电路到各种各样的多媒体电路的大范围设计。
2片32M 字节SDRAM28MHz 晶振2M 字节SSRAM4个按钮开关50MHz 晶振 VGA 数模转换器 以太网10/100M 控制器 PS2端口 2片TV 解码器扩展头2 扩展头1SD 卡槽IrDA 收发器 Cyclone Ⅱ FPGA SMA 外部时钟8个绿色LED Flash 存储器 RS-232端口VGA 输出视频输入1视频输入2音频输入音频输出USB Blsster 端口麦克风USB Host 端口USB Device 端口12V 直流电源 18个栓扣开关18个红色LED 七段数码管显示 16 2 LCD 模块 JTAG/AS模式转换开关 RUN/PROG Altera EPCS16 USB Blaster 控制器芯片 音频编码解码器以太网10/100M 端口图1 DE2-70多媒体开发板外观USB 主从控制器 电源开关Altera DE2-70多媒体开发板上携带的硬件• Altera Cyclone II 2C70 FPGA 装置• Altera 串行结构装置EPCS16•用于程序编制和用户API控制的USB Blaster (在板上) ；支持JTAG和Active Serial (AS) 两种程序编制方式• 2M字节SSRAM• 2个32M字节SDRAM• 8M字节Flash存储器• SD卡插座• 4个按钮开关• 18个栓扣开关• 18个红色发光二极管• 9个绿色发光二极管•提供时钟源的50MHz 晶振和28.63MHz 晶振• 24比特CD形式音频编码解码器和音频输入，音频输出，麦克风输入端口• VGA数模转换器和VGA输出端口• 2个TV编码器(NTSC/PAL/SECAM) 和TV输入端口• 10/100M以太网控制器和外接端口• USB主从控制器和型式A和型式B两个端口• RS-232收发器和9针端口• PS/2鼠标/键盘端口• IrDA收发器• 1个IrDA端口• 2个有二极管保护的40针扩展头除了上面所陈述的硬件特性，Altera DE2-70多媒体开发板还具有支持标准I/O接口的软件，一个链接各种组件的控制面板。
DE2-70_简介及引脚安排
DE2-70 简介
（详细内容见文件DE2_70_User_manual_v109.pdf和DE2-70 实验指导书）
一、DE2-70开发板面板结构
二、DE2-70开发板简介
70,000逻辑单元的FPGA器件
4个按键开关（通常高电平，按下时产生低电平脉冲），18个拨动开关（拨到下面时产生逻辑0，拨到上面时产生逻辑1），18个红色LED，8个绿色LED，8个数码管三、计算机通过USB blaster Port 与DE2-70相连，并需要为此安装驱动文件
查看方法：控制面板→硬件→设备管理器
DE2-70在计算机上类别为：通用串行总线控制器,若自动安装正确显示为Altera USB-Blaster, 若安装不正确，会显示一个黄色的! 需要更新驱动文件，驱动文件及路径为：C:\altera\90\quartus\drivers\usb-blaster\usbblstr.inf （注意：WIN7 X64系统对驱动程序要求微软认证的数字签名，否则无法正常使用，所以计算机最好用WIN XP或WIN7 X32）
四、DE2-70 引脚安排见参考文献DE2_70_User_manual_v109.pdf的P34-P39
五、引脚安排。
DE2开发板指导手册
DE2 教学开发板感谢您使用 Altera DE 教学开发板。
这块板子的着眼于为在数字逻辑，计算机组织和FPGA 方面的学习提供一个理想的工具。
它在硬件和CAD 工具上应用先进的技术为学生和专业人员展示了一个宽广的主题。
该板具有多种特点，非常适合各大学课程在实验室环境下的一系列设计项目和非常复杂尖端的数字系统的开发和应用。
Altera 公司为DE2 板提供了一套支持文件，例如学习指导，现成的教学实验练习和丰富的插图说明。
DE2 的特点DE2 板是以CycloneII 2C35FPGA为特点的672 针引脚的包装。
板上所有重要的部件都与板上的芯片相连，使用户能够控制板上各种的操作。
DE2 板包括了很多开关（兼有拨动开关和按键），发光二极管和七段数码管。
在更多进一步的实验中还用到了SRAM，SDRAM，Flash以及16×2的字符液晶。
需要进行处理器和I/O接口试验时，可以简单的用Altera NiosII处理器和象RS-232和PS/2标准接口。
进行涉及音频和视频的实验时，也有标准MIC、line-in、line-out接口（24位音频解编码器），video-in（TV Decoder）和VGA（10-bit DAC），这些特点都能够被用来制作CD质量的音频应用程序和专业的视频图象。
为了能够设计更强大的项目，DE2 还提供了USB2.0 接口（包括主、从USB），10/100M自适应以太网，红外（IRDA）接口，以及SD卡接口。
最后，可以通过两排扩展I/O口与其它用户自定义的板子相连。
支持材料软件拥有DE2开发板的特征的QUARTUS II网络版的CAD系统，以及NiosII嵌入式处理器，也为学生和师提供了该板的一些帮助文件，如使用说明和应用实例。
传统的FPGA 教学开发板的制造商提供了大量的的硬件和软件CAD工具支持，但极少提供直接面向教学目的的帮助文件。
但Altera 公司的DE2 板别树一帜，除了DE2 板的硬件和软件外，Aletra 公司也为一些典型的逻辑设计课程和计算机组织提供了全套的能够在实验室条件下实现的实验练习。
fpga开发板DE2实验讲义
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电子工程学院
微电子学系实验名称：移位寄存器
专业名称:集成电路设计与集成系统
实验小组成员：
朱潮涌岳龙飞张泉鑫风永东孔栓栓
指导老师：刘有耀副教授
实验时间： 7.18--7.19
第 一 页
1.实 验 目 的:
一 掌握以下操作
1 使用MegaFunction 加上符号框图进行设计
2 使用MegaFunction 添加移位寄存器
3 确定移位寄存器的HDL 类型
4 Analysis&Synthesis 与qsf 文件
5 编辑qsf 文件分配引脚（引脚分配方式之三）
6 PIN_AD25 无法分配bug 的解决方法
7 移位寄存器逻辑概略图
8 移位寄存器Technology Map Viewer
9 移位寄存器实验运行
10 使用Verilog 语言完成移位寄存器设计
11 为.v 文件创建对应的符号框图
12 用.v 语言代替符号框图作为顶层实体
13 再次执行移位寄存器Technology Map Viewer
二 掌握移位寄存器的门级描述
移位寄存器是借助quartus 自带的megafunction 功能，直接创建一个右移寄存器，然后通过符号框图的调用同时对管脚进行定义和分配，最终实现一个右移的移位寄存器功能。
第 二 页 2.实 验
环 境:
WINDOWS XP windows 7 Quartus 8.0
Quartus 7.2
DE2-70开发板 DE2-35开发板
3. 实 验 内 容 及 过 程:
1.建立quartus 工程，设置功能文件的输出文件的存储位置。
2.用megafunction 调用的右移寄存器，经设定最后结果如下图所示：
3.在符号框图中引用上述寄存器，然后给管脚重新命名，命名之时要注意的是那几个多管脚输入和输出的名字的正确输入，命名之后的结果如下：
第 三 页
4.进行管脚的分配，直接在.sof 文件上将以下的文字直接粘贴在后面，保存即可：
set_location_assignment PIN_AA23 -to iSW[0]
set_location_assignment PIN_AB26 -to iSW[1]
set_location_assignment PIN_AB25 -to iSW[2]
set_location_assignment PIN_AC27 -to iSW[3]
set_location_assignment PIN_AC26 -to iSW[4]
set_location_assignment PIN_AC24 -to iSW[5]
set_location_assignment PIN_AC23 -to iSW[6]
set_location_assignment PIN_AD25 -to iSW[7]
set_location_assignment PIN_AD24 -to iSW[8]
set_location_assignment PIN_AE27 -to iSW[9]
set_location_assignment PIN_W5 -to iSW[10]
set_location_assignment PIN_W27 -to oLEDG[0]
set_location_assignment PIN_W25 -to oLEDG[1]
set_location_assignment PIN_W23 -to oLEDG[2]
set_location_assignment PIN_Y27 -to oLEDG[3]
第 四 页 set_location_assignment PIN_Y24 -to oLEDG[4]
set_location_assignment PIN_Y23 -to oLEDG[5]
set_location_assignment PIN_AA27 -to oLEDG[6]
set_location_assignment PIN_AA24 -to oLEDG[7]
set_location_assignment PIN_T29 -to iKEY[0]
set_location_assignment PIN_AC14 -to oLEDG[8]
可以直接将以上的段落直接粘贴复制到工程文件所产生的.qsf 文件的后面，然后直接保存修改就实现了管脚的分配。
5.全编译，发现编译成功。
6.然后我们打开编译后产生的文件，可以看到分配后的管脚如下所示：
7，下载下来进行相应操作：（具体的操作细节如下：iSW0到iSW7是对初始值的设定，iSW8是将要移过来的数据，iSW9是清楚之前数据的功能键，iSW10是是否进行右移操作的选定按钮，1时进行右移，0
第 五 页 时做置数功能。
iKEYO 是移动的脉冲信号。
）
8,。
经验证可知实现了右移寄存器的功能。
4.实 验 结 果 及 分 析：
第 六 页 实验在引用megafunction 进行元件的调用是本次实验相对于前几次实验的新奇之处，之后借用符号框图的引用和对管脚的命名和配置和前面实验的过程完全相同，最后的难点在于正确的理解每个管脚所具有的操作中的实际的含义，完成功能验证的时候只有完全的明晰每个操作键的功能才能正确的完成实验结果的验证。
5.讨 论 与 心 得：
移位寄存器是我们比较熟悉的器件，当然我们也可以用下面的verliog 语言来实现那些功能，具体的代码参考实验书即可，两个在功能上是完全相同的。