Construction of DNA-based logic gates on nanostructured microelectrodes
logisim四位加减法器 计算机组成原理

logisim四位加减法器计算机组成原理English:A four-bit adder-subtractor in Logisim can be designed using basic logic gates such as AND, OR, XOR, and NOT gates. The adder circuit takes two inputs, A and B, and produces a sum output and a carry output. The subtractor circuit, on the other hand, utilizes two's complement arithmetic to perform subtraction by adding the negative number. By incorporating multiplexers and control signals, the adder-subtractor can switch between addition and subtraction modes. In computer organization, the adder-subtractor plays a crucial role in arithmetic and logic unit (ALU) of the CPU. The ALU is responsible for performing arithmetic and logical operations on data, and the adder-subtractor is a fundamental component in this process. Understanding the design and operation of the adder-subtractor in Logisim provides insight into the inner workings of the CPU and the principles of digital logic.中文翻译:在Logisim中设计一个四位加减法器可以使用基本的逻辑门,如与门、或门、异或门和非门。
电子与通信技术专业英语UnitⅠ-5

Notes
6
…such as a computer, control, or digital-communication system, there are only a few basic operations, which must be performed.
……例如计算机系统、控制系统、或数字通信 系统中,需要进行的基本运算也只有几种。
倒置
scale
[skeil]
n.
刻度, 衡量, 比例,
数值范围
flip-flop ['flipflɔp] n.
触发器
Phrases and Expressions
integrated circuits 集成电路
Chinese Translation of Texts
Lesson 5 Digital Circuit
刘 骋 蔡 静 刘小芹 主编
Unit Ⅰ
01
Unit Ⅰ
Basic Knowledge of Electronics
Lesson 5
Digital Circuit
New Words
Primarily [‘praimərəli]
Binary Switch Achieve
[‘bainəri] [switʃ] [ə'tʃi:v]
非门的重要功能是产生反向信号,即产生与 输入信号性质相反的输出信号。
不定式to produce signal inversion or an output signal 充当表语 ,其后是定语从句 that is opposite in nature to the input signal, 用以修饰该表语。
Notes
4
英语作文-集成电路设计行业:从初学者到专家的必备技能

英语作文-集成电路设计行业:从初学者到专家的必备技能The journey from a novice to an expert in the field of integrated circuit (IC) design is marked by the acquisition of a diverse set of skills, ranging from theoretical knowledge to practical application. Integrated circuits, the bedrock of modern electronics, are found in everything from smartphones to spacecraft. The complexity of designing these microscopic marvels can be daunting, but with the right approach, it is possible to master this domain.Understanding the fundamentals of semiconductor physics is the cornerstone of IC design. One must be well-versed in the behavior of electrons within various materials and the principles of current flow and voltage. This knowledge forms the basis for comprehending how transistors, the fundamental building blocks of ICs, operate. A solid grasp of digital logic design is also crucial. This involves learning how to create complex functions and algorithms using simple logic gates.As one progresses, familiarity with electronic design automation (EDA) tools becomes essential. These sophisticated software suites assist designers in creating and simulating complex circuit designs before they are fabricated. Proficiency in programming languages such as VHDL or Verilog is necessary, as they are used to describe the hardware in a manner that EDA tools can interpret.Another key skill is the ability to perform analog design. Unlike digital circuits, which operate at fixed voltage levels, analog circuits deal with a continuous range of values, making them vital for interfacing with the real world. Designing analog circuits requires a deep understanding of operational amplifiers, resistors, capacitors, and other components.As expertise grows, one must also learn about the manufacturing process. Knowledge of lithography, etching, doping, and other fabrication techniques is important to understand the constraints and possibilities of physical IC design. This includeslearning about different materials such as silicon, gallium arsenide, and silicon carbide, each with its own set of properties and uses.Thermal management is another critical area. As ICs operate, they generate heat, which can affect performance and reliability. Designers must learn how to manage heat through proper circuit design and the use of heat sinks or other cooling methods.Testing and validation are the final steps in the IC design process. A designer must be adept at creating test scenarios to ensure that the IC performs as intended under all conditions. This involves both software simulations and physical testing using oscilloscopes, multimeters, and other equipment.In conclusion, becoming an expert in IC design requires a blend of theoretical knowledge and practical skills. It demands a commitment to continuous learning and adaptation to the rapid technological advancements in the field. With dedication and the right approach, the transition from a beginner to a specialist in IC design is not only possible but also incredibly rewarding, opening doors to a world of innovation and creativity. 。
内建式自我测试(BuiltInSelfTest,BIST)为超大型积体电路常用的测试

Problem A1: Test Pattern Generation by Using Reseedable LFSRsAbstractBuilt-In-Selft-Test (BIST) is one of most popular test solutions to test the embedded cores in a chip. The BIST circuit can generate pseudo random test patterns to test these embedded cores without using expensive Automatic Test Equipments (A TEs). On the other way, if you have test vectors which are generated by the test generator, you can design a pseudo random pattern generator suitable for hitting these test vectors in short time. In this subject, try to write a program to create the pseudo random pattern generator, performed by Linear Feedback Shift Registers (LFSRs), for hitting the generated test vectors. The output of LFSRs can be rearranged before feeding to the input of Core Under Test (CUT). The lengths of LFSRs and the numbers of LFSRs are no limit. In the vectors generation procedure, the seeds of LFSRs can be changed for the purpose of saving BIST time.1.Introduction:Linear Feedback Shift Registers (LFSRs) are widely adopted as the pseudo-random test pattern generators for built-in self test (BIST) of logic circuits shown in Figure1, due to its low hardware overhead. However, there are many faults in the circuits under test (CUTs) that are hardly detected by the test patterns generated by using the traditional LFSRs, certain deterministic patterns are needed for achieved higher fault coverage. These extra patterns can be stored in the memory of an external tester or the on-chip memory.In order to reduce the time of LFSR to generate patterns for testing such hard to detect fault, storage requirements, one of the solutions is to change seeds of the LFSRs during test pattern generation. A seed refers to the initial state of an LFSR. The procedure for changing the seed of the LFSR is called reseeding. Since the seeds still need to be stored in the memory, it needs a good reseeding strategy to reduce a large test data volume into a smaller set of seeds.Test ResultFigure 1: BIST ArchitectureThe structure of an LFSR is composed of D-FFs and exclusive-OR gates. It can be expressed by a polynomial of X. Figure 2 shows the division type LFSR with polynomial X 4 + X 3 + 1:11 0 0 1 Coefficient Exponent 0 (Seed)O 4 O 3 O 2 O 1Figure 2: The division type LFSR with polynomial X 4 + X 3 + 1It is easy to figure out that the radix-N polynomial requires N D-FFs. The coefficient of each exponent denotes the insertion points of exclusive-OR gates in the shifting path. When the LFSR starts or restarts for a new seed, the LFSR is reset to zero first. Then the seed value is applied sequentially from I 0, see Figure 2. As the LFSR is operating in test pattern generation mode, the I 0 is set to 0. Therefore, there are two penalties for reseeding, one is the memory occupied by the seeds, and another is the clock cycles to reset and shift the seeds into the LFSR. 2. LFSR Design Issue and PartitionIt is not practical to implement a big LFSR to test a circuit with large number of inputs. It is because such implementation often results in lower F.C. and longer BIST time. A good partition of LFSR will improve F.C. and BIST time. Figure 3 shows a CUT with k-bit inputs (I k , I k-1, …, I 1). The LFSR is partitioned into m smaller LFSRs (LFSR m , LFSR m-1, …, LFSR 1). Each LFSR is with a size of L m , L m-1, …, L 1, respectively , and hence the total size of the LFSRs is L m +L m-1+…+ L 1 = k. Since the LFSRs nees s seeds to generate the test vectors for the CUT, it needs an (s *k)-bitmemory to store the seeds.Figure 3: LFSR partitionAssume that there are n test vectors (V1, V2, …, V n) in the test set. If you cannot find any correlation (equivalent or inversion, i.e., I i= I j or I i=I j’) between inputs of test patterns, the optimal size of LFSR is k. However, the correlations between inputs are possible in the test set. Hence, there are two cost considerations in test application:2.1The hardware cost:Figure 4: Example of a test setY ou can use both of the bit broadcast and bit inversion techniques to reduce the required length of LFSRs if the correlations, I i=I j or I i=I j’, exist between inputs of test pattern. The total length of LFSRs, L1+L2+…+ L m = L total, will smaller than k. In the Figure 4, the input length k is 10. Thetest set is composed of 13 test vectors (V1, V2, …, V13) . The minus sign denotes “don’t care”. The patterns are listed in descending order from I10 to I1. In the test set, the I8 and I5 in every test vector are equivalent or compatible. The I7and I3in every test vector are inversion or compatible. The two bits are called equivalent, inversion or compatible are list in Table 1. Y ou can combine I8 and I5 into a single bit and combine I7 and I3with adding an inverter to save 2 D-FFs of LFSRs.2.2The test time costIn some cases, if we use all bits of LFSRs to be test inputs, it will expense more test time for the purpose of high Pattern Coverage Rate (= Hit Patterns / Total Test Patterns). One of the solutions is to appropriately increase the size of LFSRs and use some of them to be test inputs. In such condition, L total will larger than k.3.Subject of this problem:Please write a program which can generate appropriate structures of LFSRs and a set of seeds for the applied test set. The program must consider four factors: (1) the hardware test cost, (2) pattern coverage rate, (3) the total data volume of seeds, and (4) BIST time. The seeds of every LFSRs can be changed values during the test. The input file to the program is the description of the test set. Its format will be described in detail in the Input Format section. Y ou must generate a output file to describe the structures of LFSRs, the cycles for applying seeds, the ending cycle, and pattern coverage. The required formats are listed in the Output Format section.The command line format for this program is<exe_filename> <vector_file>.vecWhere the <exe_filename> is the execution file of this program after compiling, and the <vector_file>.vec is the input filename with (.vec) file extension. The program must write an output file after execution. The output filename format is<vector_file>.outWhere (.out) is the file extension of the output file.4.Input FormatThe input file contains three keywords: INPUT_NO, VECTOR_NO, and VECTORS, which represent the number of input, the number of test vector, and the test vectors, respectively. In figure4, the number of input is 10 and the number of test vector is 13. The input file is written as follows:INPUT_NO10VECTOR_NO13VECTORS // I10 I9 I8 I7 I6 I5 I4 I3 I2 I11-01101000 // V1000-101111 // V2….1001100011 // V135.Output FormatThe output structure file contains 8 keywords: TOTAL_SIZE, LFSR_NO, POLY, INPUT_SEQ, SEED, CYCLE, END, and COVERAGE which represent: total size of LFSR, the number of LFSR, polynomials of LFSRs, seeds of LFSRs, input order, the number of clock cycles for reseeding, end of the pattern generation procedure, and the pattern coverage in percentage, respectively. Note that POLY and SEED represent all LFSRs’ polynomial and seed from LFSR m to LFSR n, respectively. The polynomial is expressed in a list of exponents whose coefficient is 1. For example, three LFSRs (LFSR3, LFSR2 and LFSR1) are used in the design. The polynomials of LFSR3, LFSR2and LFSR1are X4+ X3+ 1, X3+ X2+ 1 and X3+ X + 1, respectively. The corresponding arguments of POLY are 4 3 0, 3 2 0, and 3 1 0. All numbers in POLY are separated by blank or tab. The numbers are listed in a descending order for each LFSR’s polynomial.The seed is represented in the binary format. For example, if the initial (or reseeding) state of X4 + X3+ 1 is {0 0 1 0} in your design, its corresponding representation is 0010. Y ou can insert space, tab, or underlines between binary digits for readability.The LFSRs’ output IDs, which are not listed in the output file but used for INPUT_SEQ, are set from TOTAL_SIZE to 1 by default. The INPUT_SEQ specifies the connection from LFSRs’outputs to CUT’s inputs. For example, a 3-LFSR structure with X4 + X3+ 1, X3 + X2+ 1 and X3 + X+ 1 forms a 10-bit test pattern generator. Eight of them are used as inputs of CUT. The output structure file is shown as follows, and the connection between LFSRs and CUT is shown in figure 5.At the 0th clock cycle, the LFSR is reset. At the 1st clock cycles, the 1st seed will be shifted into the LFSR from I0 to all DFFs in the LFSRs, which initializes the pattern generation sequence. This initialization step takes k clock cycles for shifting a seed into the LFSRs, if the LFSR size is equal to k. When the LFSRs need a new seed, it needs to take one extra clock cycle to reset the LFSRs before it takes another k clock cycles for shifting the new seed. So the total time penalty for s seeds is:s* (k+1) clock cyclesTake the output-structure file in Figure 5 as an example. At the 0th cycle, all DFFs in the LFSRs are reset to 0. Then the seeds (0011), (001), and (010) will be shifted into the 3 LFSRs in 10 cycles. After this initialization step, the pattern sequence starts, and in fact, the first pattern is the seed itself. When reseeding, the LFSRs will be reset, and then a new seed will be shifted into the LFSRs again. After the zz th cycle, if no further generated pattern can match any of the undetected input vectors, the pattern generation procedure ends. Then, (CLOCK zz, END) will be written into the output file. Last, the program must report the pattern coverage in percentage at the last line of the output file.TOTAL_SIZE10 //the structure of LFSRsLFSR_NO 3 // partitions of LFSRsPOLY 4 3 0 3 2 0 3 1 0INPUT_SEQ8 5 4 3 2 1 – 6 –7SEED0011 001 010 // Initial seedCYCLE xx // 1st reseedingSEED xxxx xxx xxxCYCLE yy // 2nd reseedingSEED yyyy yyy yyyCYCLE zz // end of pattern generationENDCOVERAGE PC % // pattern coverageFigure 5: Example of output structure file.ExampleWe can use exhaustive methods to search the best solution for the example in figure 5, but it is time consuming when the test data is enormous. For the example in Figure 4, if we choose the following two LFSRs, X3 + X + 1 and X5 + X4 + X3 + X + 1, its output structure is:TOTAL_SIZE8LFSR_NO 2POLY 3 1 0 5 4 3 1 0INPUT_SEQ 2 4 9 7,-3 6 1 8,5 10SEED 010 11001CYCLE 51ENDCOVERAGE 100%If we use a single seed to generate test patterns, such as Case 1, it takes 51 cycles to cover all the test patterns.Case 1:cycle 1: resetcycle 2~9: seeding 010 11001cycle 10:LFSR=010 11001, LFSR out=10011100Applied pattern=1001101000, Hit pattern V1cycle 15:LFSR=101 01010, LFSR out=01101010Applied pattern=0110110110, Hit pattern V9cycle 18:LFSR=100 11101, LFSR out=10011011Applied pattern=1001100011, Hit pattern V7 V13cycle 30:LFSR=001 01110, LFSR out=01101001Applied pattern=0110110101, Hit pattern V4 V10cycle 33:LFSR=011 00110, LFSR out=01100101Applied pattern=0110011101, Hit pattern V6cycle 34:LFSR=110 01100, LFSR out=00001111Applied pattern=0000101111, Hit pattern V2cycle 36:LFSR=101 01011, LFSR out=11101010Applied pattern=1110110110, Hit pattern V8cycle 37:LFSR=001 10110, LFSR out=01110001Applied pattern=0111010001, Hit pattern V11 V12cycle 51:LFSR= 001 00010, LFSR out=01100000Applied pattern=0110010100, Hit pattern V3If we apply two seeds during the pattern generation procedure, such as Case 2, it only takes 45 cycles to cover all the test patterns. The comparison results are shown in Table 2.Case 2:TOTAL_SIZE8LFSR_NO 2POLY 3 1 0 5 4 3 1 0INPUT_SEQ 2 4 9 7,-3 6 1 8,5 10SEED 010 11001CYCLE 19SEED 001 01110CYCLE 36SEED 001 00010CYCLE 45ENDCOVERAGE 100%cycle 1: resetcycle 2~9: seeding 010 11001cycle 10:LFSR=010 11001, LFSR out=10011100Applied pattern=1001101000, Hit pattern V1cycle 15:LFSR=101 01010, LFSR out=01101010Applied pattern=0110110110, Hit pattern V9cycle 18:LFSR=100 11101, LFSR out=10011011Applied pattern=1001100011, Hit pattern V7 V13cycle 19: resetcycle 20~27: seeding 001 01110cycle 28:LFSR=001 01110, LFSR out=01101001Applied pattern=0110110101, Hit pattern V4 V10cycle 31 :LFSR=011 00110, LFSR out=01100101Applied pattern=0110011101, Hit pattern V6cycle 32:LFSR=110 01100, LFSR out=00001111Applied pattern=0000101111, Hit pattern V2cycle 34:LFSR=101 01011, LFSR out=11101010Applied pattern=1110110110, Hit pattern V8cycle 35:LFSR=001 10110, LFSR out=01110001Applied pattern=0111010001, Hit pattern V11 V12cycle 36: resetcycle 37~44: seeding 001 00010cycle 45:LFSR= 001 00010, LFSR out=01100000Applied pattern=0110010100, Hit pattern V3Table 2. The solutions for the test set in figure 4Grade criterion:1.Pattern coverage:= (Detected Pattern) / (Total Test Pattern)2.BIST time (the number of required clock cycles including reset and reseeding)= Applied test cycles + Seed number * (1 + Total size of LFSRs) = last CYCLE 3.Total LFSR size= L m + L m-1 + … + L14.The total data volume of the seeds (in bits)= Seed number * Total size of LFSRs5.The upper bound of the number of seeds in use= 0.2 * Total Test Pattern6.Performance (Run time, Memory usage)7.Program must be terminated within six hours for all cases.Reference:1. B. Koenemann, “LFSR-coded test patterns for scan designs,” Proc. Of European Test Conf.,1991, p.237-242.2.S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns ThroughReseeding of Multiple-Polynomial Linear Feedback Shift Registers,” Proc. Of IEEE Int’l Test Conf., 1992, p.120-129.3.P. H. B ardell, W. H. McAnney, and J. Savir, “Built-In Test for VLSI: PseudorandomTechniques”, John Wiley & Sons, 1987.4.M. Abramovici, M. A. Breuer, and A. D. Friedman, “Digital Systems Testing and TestableDesign”, Computer Science Press, 1990.5.M. L. Bushnell, a nd V. D. Agrawal, “Essentials of electronic testing for digital, memory, andmixed-signal VLSI circuits”, Kluwer Academic Publishers, 2000.11AppendixDivision type LFSR with polynomial: X 3 + X 2+ 10 0 1 0 1 0 1 0 0 1 0 1 1 1 1 0 1 1 1 1 0Cyclic pattern sequence: 00 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 10 11 1 0 1。
Logic-Gates

2. Fundamentals of Logic gates2.1 LOGIC GATESWe have seen that the foundation of logic design is seated in a well defined axiomatic system called Boolean algebra, which was shown to be what is known as a“Huntington system”.In this axiomatic system the definition of AND and OR operators or functions was set forth and these were found to be well defined operators having certain properties that allow us to extend their definition to Hardware applications.These AND and OR operators,sometimes referred to as connectives, actually suggest a function that can be emulated by some H/w logic device. The logic Hardware devices just mentioned are commonly referred to as “gates”.Keep in mind that the usage of “gate” refers to an actual piece of Hardware where “function” or “operation” refers to a logic operator AND. On the other hand, when we refer to a “gate” we are referring directly to a piece of hardware called a gate. The main point to remember is ‘Don’t confuse gates with logic operators’.2.1.1 Basic Logic GatesPositive and Negative Logic DesignationThe binary signals at the inputs or outputs of any gate can have one of the two values except during transition. One signal levels represents logic 1 and the other logic 0. Since two signal values are assigned two to logic values, there exist two different assignments of signals to logic.Logics 1 and 0 are generally represented by different voltage levels. Consider the two values of a binary signal as shown in Fig. 2.5.1. One value must be higher than the other since the two values must be different in order to distinguish between them. We designate the higher voltage level by H and lower voltage level by L. There are two choices for logic values assignment. Choosing the high-level (H) to represent logic 1 as shown in (a) defines a positive logic system. Choosing the low level L to represent logic-1 as shown in (b), defines a negative logic system.Fig. 2.5.1The terms positive and negative are somewhat misleading since both signal values may be positive or both may be negative. Therefore, it is not signal polarity that determines the type of logic,but rather the assignment of logic values according to the relative amplitudes of the signals.The effect of changing from one logic designation to the other equivalent to complementing the logic functions because of the principle of duality of Boolean algebra.Gate DefinitionA‘gate’is defined as a multi-input (> 2) hardware device that has a two-level output. The output level (1–H/0–L) of the gate is a strict and repeatable function of the two-level(1–H/0–L)combinations applied to its inputs.Fig. 2.5.2shows a general model of a gate.Fig. 2.5.2 The general model of a gate.The term “logic” is usually used to refer to a decision making process. A logic gate, then, is a circuit that can decide to say yes or no at the output based upon inputs. We apply voltage as the input to any gate, therefore the Boolean (logic) 0 and 1 do not represent actual number but instead represent the state of a voltage variable or what is called its logic level. Sometimes logic 0 and logic 1 may be called as shown in table below:Table 2.5.2a.OR GateThe OR gate is sometimes called the “any or all gate”. To show the OR gate we use the logical symbol in Fig. 2.5.4(a).b.c.Fig. 2.5.4 (a) OR gate logic symbol. (b) Practical OR gate circuit.d.e. A truth-table for the ‘OR’ gate is shown below according to Fig. 2.5.4(b).The truth-table lists the switch and light conditions for the OR gate. The unique output from the OR gate is a LOW only when all inputs are low. The output column in Table (2.5.4) shows that only the first line generates a 0 while all others are 1.Table 2.5.4f.g.Fig. 2.5.4(c) shows the ways to express that input A is ORed with input B toproduce output Y.h.i.Fig. 2.5.4 (c)j.Example.Determine the output Y from the OR gate for the given input waveform shown in Fig. 2.5.4(d).k.l.Fig. 2.5.4 (d)m.Solution. The output of an OR gate is determined by realizing that it will be low only when both inputs are low at the same time. For the inputs the outputs is low only during period t2. In remaining time output is 1 as shown in Fig. 2.5.4(e).n.o.Fig. 2.5.4 (e)p.We are now familiar with AND and OR gates. At this stage, to illustrate at least in part how a word statement can be formulated into a mathematical statement (Boolean expression) and then to hardware network, consider the following example:q.Example. Utkarsha will go to school if Anand and Sawan go to school, or Anand and Ayush go to school.r.Solution. T his statement can be symbolized as a Boolean expression as follows:s.t.The next step is to transform this Boolean expression into a Hardware network and this is where AND and OR gates are used.u.v.The output of gate 1 is high only if both the inputs A and S are high (mean both Anandand Sawan go to school). This is the first condition for Utkarsha to go to school.w.The output of gate 2 is high only if both the inputs A and A.Y are high (means both Anand and Ayush go to school). This is the second condition for Utkarsha to go to school.x.According to example atleast one condition must be fullfilled in order that Utkarsha goesto school. The output of gate 3 is high when any of the input to gate 3 is high means at leastone condition is fulfilled or both the inputs to gate 3 are high means both the conditions are fulfilled.y.The example also demonstrates that Anand has to go to school in any condition otherwise Utkarsha will not go to school.z.b. AND GateThe AND gate is sometimes called the “all or nothing gate”. To show the AND gate we use the logic symbol in Fig. 2.5.3(a).This is the standard symbol to memorize and use from now on for AND gates.Fig. 2.5.3 (a) AND Gate logic symbol. (b) Practical AND gate circuit.Now, let us consider Fig. 2.5.3(b). The AND gate in this figure is connnected to input switches A and B. The output indicator is an LED. If a low voltage (Ground, GND) appears at inputs, A and B, then the output LED is not bit. This situation is illustrated in table (). Line 1 indicates that if the inputs are binary 0 and 0, then the output will be binary 0.Notice that only binary1s at both A and B will produce a binary 1 at the output.Table 2.5.3 AND Truth TableIt is a+5V compared to GNDappearing at A, B, or Y that is called a binary1or a HIGH voltage.A binary0,or Lowvoltage, is defined as a GND voltage (near0V compared to GND) appearing at A, B or Y.We are using positive logic because it takesa positive+5V to produce what we call abinary 1.The truth table is said to discribe theANDfunction.The unique output from the ANDgate is a HIGH only when all inputs are HIGH.Fig. 2.5.3 (c) shows the ways to expressthat input A is ANDed with input B to produceoutput Y.Pulsed OperationIn many applications, the inputs to a gate may be voltage that change with time betweenthe two logic levels and are called as pulsed waveforms. In studying the pulsed operation of an AND gate, we consider the inputs with respect to each other in order to determine the output level at any given time. Following example illustrates this operation:Example. Determine the output Y from the AND gate for the given input waveform shown in Fig. 2.5.3(d)..Fig. 2.5.3 (d)Solution. The output of an AND gate is determined by realizing that it will be high only when both inputs are high at the same time. For the inputs the outputs is high only during t3 period. In remaining times, the outputs is 0 as shown in Fig.2.5.3(e).Fig. 2.5.3 (e)Fig. 2.5.3 (e)c. NOT GateNOT gates are often called inverters. A NOT gate's output signal is the opposite of its input signal. Note that the symbol of the NOT gate is the same as that of the buffer, except for the small circle near its output. Small circles at input or output lines of a gate's schematic symbol denote the fact that the signal is inverted.Input OutputL HH L2.1.2 Universal GatesNAND and NOR gates. The NAND and NOR gates are widely used and are readily available from most integrated circuit manufacturers. A major reason for the widespread use of these gates is that they are both UNIVERSAL gates, universal in the sense that both can be used for AND operators,OR operators,as well as Inverter. Thus, we see that a complex digital system can be completely synthesized using only NAND gates or NOR gates.a.NAND GateThe NAND gate is a NOT AND, or an inverted AND function. The standard logic symbol for the NAND gate is shown in Fig. (2.5.7a). The little invert bubble(small circle)on the right end of the symbol means to invert the output of AND.b.Fig. 2.5.7(a)NAND gate logic symbol (b)A Boolean expression for the output of a NAND gate.Figure 2.5.7(b)shows a separate AND gate and inverter being used to produce the NAND logic function. Also notice that the Boolean expression for the AND gate, (A.B) and the NAND (A.B) a re shown on the logic diagram of Fig. 2.5.7(b).The truth-table for the NAND gate is shown in Fig. 2.5.7(c). The truth-table for the NAND gate is developed by inverting the output of the AND gate. ‘The unique output from the NAND gate is a LOW only when all inputs are HIGH.c.d.Fig. 2.5.7 (c) Truth-table for AND and NAND gates.Fig. 2.5.7 (d) shows the ways to express that input A is NANDed with input B yielding output Y.e.f.Fig. 2.5.7 (d)Example. Determine the output Y from the NAND gate from the given input waveformshown in Fig. 2.6.7 (e).g.h.Fig. 2.5.7 (e)Solution. The output of NAND gate is determined by realizing that it will be low onlywhen both the inputs are high and in all other conditions it will be high. The ouput Y isshown in Fig. 2.5.7(f).i.j.Fig. 2.5.7 (f)The NAND gate as a UNIVERSAL GateThe chart in Fig. 2.5.7(g) shows how would you wire NAND gates to create any of the other basic logic functions. The logic function to be performed is listed in the left column of the table; the customary symbol for that function is listed in the center column. In the right column, is a symbol diagram of how NAND gates would be wired to perform the logic function.k.l.Fig. 2.5.7 (g)m.The NOR gate.The NOR gate is actually a NOT OR gate or an inverted OR function.n.The standard logic symbol for the NOR gate is shown in Fig. 2.5.7(h)o.p.Fig. 2.5.7 (h) NOR gate logic symbol (i) Boolean expression for the output of NOR gate. Note that the NOR symbol is an OR symbol with a small invert bubble on the right side. The NOR function is being performed by an OR gate and an inverter in Fig. 2.5.7(i). The Boolean function for the OR function is shown(A+B),the Boolean expression for the final NOR function is (A + B).q.The truth-table for the NOR gate is shown in Fig. 2.5.7(j). Notice that the NOR gate truth table is just the complement of the output of the OR gate.The unique output from the NOR gate is a HIGH only when all inputs are LOW.r.s.Fig. 2.5.7 (j) Truth-table for OR and NOR gates.t.Figure 2.5.7(k) shows the ways to express that input A is ORed with inputB yieldingu.output Y.v.w.x.Fig. 2.5.7 (k)y.Example.Determine the output Y from the NOR gate from the given input waveform shown in Fig. 2.5.7(l).z.aa.Fig. 2.5.7 (l)bb.Solution. The output of NOR gate is determined by realizing that it will be HIGH only when both the inputs are LOW and in all other conditions it will be high. The output Y is shown in Fig. 2.5.7(m).cc.dd.Fig. 2.5.7 (m)B . NOR GateThe NOR gate as a UNIVERSAL gate.The chart in Fig. 2.5.7(n) shows how would your wire NOR gates to create any of the other basic logic functions.Fig. 2.5.7 (n)2.1.3 Coincidence gatesa.The Exclusive OR GateThe exclusive OR gate is sometimes referred to as the “Odd but not the even gate”. It is often shortend as “XOR gate”. The logic diagram is shown in Fig. 2.5.8 (a) with its Boolean expression. The symbol m eans the terms are XORed together.Fig. 2.5.8 (a)The truth table for XOR gate is shown in Fig. 2.5.8 (b). Notice that if any but not all the inputs are 1, then the output will be 1. ‘The unique characteristic of the XOR gates that it produces a HIGH output only when the odd no. of HIGH inputs are present.’Fig. 2.5.8 (b)To demonstrate this, Fig. 2.5.8 (c) shows a three input XOR gate logic symbol and the truth table Fig. 2.5.8 (d). The Boolean expression for a three input XOR gate can be written asFig. 2.5.8 (c)Fig. 2.5.8 (d)Putting the value of X, we getY = (AB + A B)C + (AB + AB).CY = AB C + A BC + A B C + ABCThe HIGH outputs are generated only when odd number of HIGH inputs are present (see T.T.)‘This is why XOR function is also known as odd function’.Fig. 2.5.8 (e) shows the ways to express that input A is XORed with input B yielding output Y.Fig. 2.5.8 (e)The XOR gate using AND OR-NOT gates.we know A B = AB + A BAs we know NAND and NOR are universal gates means any logic diagram can be made using only NAND gates or using only NOR gates.XOR gate using NAND gates only.XOR using NOR gates only.The procedure for implementing any logic function using only universal gate (only NAND gates or only NOR gates) will be treated in detail in section 2.6.Example. Determine the output Y from the XOR gate from the given input waveform shown in Fig. 2.5.8 (f).Fig. 2.5.8 (f)Solution. The output XOR gate is determined by realizing that it will be HIGH only when the odd number of high inputs are present therefore the output Y is high for time period t2 and t5 as shown in Fig. 2.5.8 (g).b.The Exclusive NOR gatec.d.The Exclusive NOR gate is sometimes reffered to as the ‘COINCIDENCE’ or‘EQUIVALENCE’gate.This is often shortened as‘XNOR’gate.The logic diagram is shown in Fig. 2.5.9 (a).e.f.Fig. 2.5.9 (a)g.Observe that it is the XOR symbol with the added invert bubble on theoutput side. The Boolean expression for XNOR is therefore, the invert of XOR function denoted by symbol O.h.i.j. The truth table for XNOR gate is shown in Fig. 2.5.9 (b).k.l.Fig. 2.5.9 (b)m.Notice that the output of XNOR gate is the complement of XOR truth table. n.‘The unique output of the XNOR gate is a LOW only when an odd number of input are HIGH’.o.p.Fig. 2.5.9 (c)q.r.Fig. 2.5.9 (d)s.To demonstrate this, Fig. 2.5.9 (c) shows a three input XNOR gate logic symbol and the truth-table 2.5.9 (d).t.Figure 2.5.9 (e) shows the ways to express that input A is XNORed with input B yieldingu.output Y.v.w.x.Fig. 2.5.9 (e)y.Now at this point, it is left as an exercise for the reader to make XNOR gate using ANDOR-NOT gates,using NAND gates only and using NOR gates only.z.Example.Determine the output Y from the XNOR gate from the given input waveform shown in Fig. 2.5.9 (f).aa.bb.Fig. 2.5.9 (f)cc.Solution.The output of XNOR gate is determined by realizing that it will be HIGH only when the even-number of high inputs are present, therefore the output Y is high for time period t2 and t5 as shown in Fig. 2.5.9 (g).dd.ee.F ig. 2.5.9 (g)ff.a.The Exclusive NOR gateThe Exclusive NOR gate is sometimes reffered to as the‘COINCIDENCE’or ‘EQUIVALENCE’ gate. This is often shortened as ‘XNOR’ gate. The logic diagram is shown in Fig. 2.5.9 (a).gg.hh.Fig. 2.5.9 (a)ii.Observe that it is the XOR symbol with the added invert bubble on the output side. The Boolean expression for XNOR is therefore, the invert of XOR function denoted by symbol O.jj.kk.ll. The truth table for XNOR gate is shown in Fig. 2.5.9 (b).mm.nn.Fig. 2.5.9 (b)oo.Notice that the output of XNOR gate is the complement of XOR truth table. pp.‘The unique output of the XNOR gate is a LOW only when an odd number of input are HIGH’.qq.rr.Fig. 2.5.9 (c)ss.tt.Fig. 2.5.9 (d)uu.To demonstrate this, Fig. 2.5.9 (c) shows a three input XNOR gate logic symbol and the truth-table 2.5.9 (d).vv.Figure 2.5.9 (e) shows the ways to express that input A is XNORed with input B yieldingww.output Y.xx.yy.zz.Fig. 2.5.9 (e)aaa.Now at this point, it is left as an exercise for the reader to make XNOR gate using ANDOR-NOT gates, using NAND gates only and using NOR gates only.bbb.Example.Determine the output Y from the XNOR gate from the given input waveform shown in Fig. 2.5.9 (f).ccc.ddd.Fig. 2.5.9 (f)eee.Solution. The output of XNOR gate is determined by realizing that it will be HIGH only when the even-number of high inputs are present, therefore the output Y is high for time period t2 and t5 as shown in Fig. 2.5.9 (g).fff.ggg.F ig. 2.5.9 (g)hhh.2.2 L OGIC DIAGRAMAre diagrams in the field of logic, used for representation and to carry out certain types of reasoning.Basic Logic Diagrams Basic logic diagrams are used to show the operation of a particular unit or component. Basic logic symbols are shown in their proper relationship so as to show operation only in the mostsimplified form possible. Figure 6-24 shows a basic logic diagram for a serial subtractor. The operation of the unit isdescribed briefly in the next paragraph. In the basic subtractor in figure 6-24, assume you want to subtract binary 011 (decimal 1) from binary 100 (decimal 4). At time I o, the 0 input at A and 1 input at B of inhibitor I1 results in a 0 output from inhibitor I1and a 1 output from inhibitor I2. The 0 output from I1and the 1 output from I2are applied to OR gate G1, producing a 1 output from G1. The 1 output from I2 is also applied to the delay line. The I output from G1 along with the 0 output from the delay line produces 1 output from I3. The 1 input from G1 and the 0 input from the delay line produce a 0 output from inhibitor I4. The 0 output from L and the 1 output from I3are applied to OR gate G2 producing a 1 output.At time t1the 0 inputs on the A and B input lines of I1produce 0 outputs from I1and I2. The 0 inputs on both input lines of OR gate G1result in a 0 output from G1. The I input applied to the delay line at time t o emerges (1 bit time delay) and is now applied to the inhibit line of 13 producing an 0 output from I3. The 1 output from the delay line is also applied to inhibitor I4, and along with the 0 output from G1produces a 1 output from I4. The I4output is recycled back into the delay line, and also applied to OR gate G2. As a result of the 0 and 1 inputs from I3, and I4, OR gate G2 produces a 1 output. At time t2, the 1 input on the A line and the 0 input on the B line of I1 produce a 1 output from I1and a 0output from I2. These outputs applied to OR gate G1produce a 1 output from G1, which is applied to 13 and I4. The delay line now produces a 1 output (recycled in at time t1), which is applied to I3 and I4. The 1 output from the delay line along with the 1 output from G1 produces a 0 output from I3. The 1 output from G1 along with the 1 output from the delay line produces a 0 output from I4. With 0 outputs from I3 and I4, OR gate G2 produces a 0 output.2.3 Truth TableA truth table shows how a logic circuit's output responds to various combinations of the inputs, using logic 1 for true and logic 0 for false. All permutations of the inputs are listed on the left, and the output of the circuit is listed on the right. The desired output can be achieved by a combination of logic gates. A truth table for two inputs is shown, but it can be extended to any number of inputs. The input columns are usually constructed in the order of binary counting with a number of bits equal to the number of inputs.This notation is useful especially if the operations are commutative, although one can additionally specify that the rows are the first operand and the columns are the second operand. This condensed notation is particularly useful in discussing multi-valued extensions of logic, as it significantly cuts down on combinatoric explosion of the number of rows otherwise needed. It also provides for quickly recognizable characteristic "shape" of the distribution of the values in the table which can assist the reader in grasping the rules more quickly.。
加州理工学院钱璐璐

加州理工学院钱璐璐:利用人工合成的DNA制成迄今最复杂生化电路2011美国加州理工学院研究人员利用人工合成的DNA(脱氧核糖核酸)分子,在试管中制成了迄今最复杂的生化电设计这样的电路,目的并非要与电子计算机竞争,而是用来探索生物系统处理信息的原理。
在传统计算机中,集成电路的基本元件逻辑门由晶体管制成,但在这一新制成的生化电路中,逻辑门由短的单链链特征DNA组成。
晶体管以电子流入和流出晶体管作为信号,而DNA逻辑门以接收和发出分子作为信号。
研究人员在最新一期《科学》杂志上报告说,他们设计了多个电路,其中最大的一个包括74个不同的DNA分超过15的整数的平方根,给出的答案是小于该平方根的最大整数。
研究人员通过监测试管溶液中输出信号分子的浓案。
整个运算过程需要大约10个小时。
研究人员表示,设计具有决策能力的生化电路,可以帮助更好掌控应用于生物工程、化学工程以及生化工业中的说在未来,一个设计合成的生化电路可以被放入临床血液样本中,检测各种分子在样本中的水平,然后根据这些信息断。
“我们试图借用已为电子世界带来巨大成功的理念,例如对运算的抽象、编程语言以及编译器,并将它们应用到中,”论文第一作者、加州理工学院生物工程系博士后钱璐璐说。
此前在实验室里制造的生化电路普遍具有局限性,因为当电路的规模增大时,工作的稳定性和可预测性也随之降说,造成这种局限性最可能的原因是,不同的电路功能需要用不同结构的分子元件来实现,这样当电路变得越来越大试的难度也随之增加。
在此次设计的新生化电路中,分子元件的结构非常简单且标准化,运作稳定且容易升级。
钱璐璐说,在计算机工业中,大家努力制造越来越好的计算机,“我们也在做相同的努力。
我们要制造越来越好成更加尖端的任务,让分子设备根据它们的环境而行动。
”裔博士最新Science文章走在世界最前沿点击次数:360 发布时间:2011-6-7来自加州理工学院生物工程系,计算机科学、计算与神经系统学的研究人员利用人工合成的DNA分子,在试管中完成了迄今最复杂的生化电路。
介绍计算机组成原理这门学科的英语作文

介绍计算机组成原理这门学科的英语作文Computer organization and design is a fundamental subject in the field of computer science. 计算机组成原理和设计是计算机科学领域的一门基础课程。
It focuses on the understanding and design of computer systems at the hardware level, and plays a crucial role in shaping the way modern computing systems work. 它关注的是在硬件层面上理解和设计计算机系统,并且在塑造现代计算系统的工作方式上起着至关重要的作用。
At its core, computer organization and design delves into the architecture and functionality of computer hardware components such as the CPU, memory, and I/O devices. 在其核心,计算机组成原理和设计深入研究了计算机硬件组件的体系结构和功能,如CPU、内存和I/O 设备。
It aims to provide a comprehensive understanding of how these components work together to execute instructions, process data, and perform various computational tasks. 它旨在提供对这些组件如何一起执行指令、处理数据和执行各种计算任务的全面理解。
Furthermore, the study of computer organization and design often involves exploring the principles of digital logic and circuit design. 此外,计算机组成原理和设计的研究通常涉及探索数字逻辑和电路设计的原理。
英语作文-掌握集成电路设计中的关键技术与方法

英语作文-掌握集成电路设计中的关键技术与方法Integrated Circuit (IC) design plays a pivotal role in modern electronics, serving as the foundation for virtually all electronic devices we use today. Mastering the key techniques and methods in IC design is crucial for engineers and researchers in this field. This article explores the essential aspects of IC design, highlighting the methodologies and technologies that drive innovation and efficiency in this complex discipline.### Understanding IC Design Fundamentals。
At its core, IC design involves the creation of miniature electronic circuits that integrate thousands to billions of components onto a single semiconductor chip. This integration enables devices to perform complex functions while minimizing size and power consumption. The process begins with conceptualizing the circuit's functionality and architecture, followed by detailed design and verification stages.### Key Stages in IC Design。
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Construction of DNA-based logic gates on nanostructured microelectrodesTao Wei 1,2•Min Li 2•Yue-Yue Zhang 2•Ali Aldalbahi 3•Li-Hua Wang 2•Xiao-Lei Zuo 2•Yun Zhao 1Received:14October 2016/Revised:3December 2016/Accepted:19December 2016/Published online:2February 2017ÓShanghai Institute of Applied Physics,Chinese Academy of Sciences,Chinese Nuclear Society,Science Press China and Springer Science+Business Media Singapore 2017Abstract Electrochemical logical operations utilizing biological molecules (protein or DNA),which can be used in disease diagnostics and bio-computing,have attracted great research interest.However,the existing logic opera-tions,being realized on macroscopic electrode,are not suitable for implantable logic devices.Here,we demon-strate DNA-based logic gates with electrochemical signal as output combined with gold flower microelectrodes.The designed logic gates are of fast response,enzyme-free,and micrometer scale.They perform well in either pure solu-tion or complex matrices,such as fetal bovine serum,suggesting great potential for in vivo applications.Keywords Logic gates ÁMicroelectrode ÁBio-computing ÁElectrochemical ÁNanostructured electrode1IntroductionA logic gate is a physical device implementing a Boo-lean function.It performs a logical operation on one or more logical inputs and produces a single logical output.Enzymes and nucleic acids are promising for constructing molecular logic gates for computational purposes [1–11],and DNA is advantageous in its high stability,suitable for bio-imaging,and precise programmability [12–17],and hence it is an excellent candidate for building logic oper-ating systems.Since Adleman’s invention of bio-computations in 1994using just DNA molecules [18],a diverse range of DNA logic devices have been designed [19–24].Willner and co-workers developed fluorescent logic gates,such as ‘AND,’‘OR,’and ‘SET-RESET,’constructed with ions as inputs and the fluorescence intensity of a G-quadruplex as outputs [25].Wang and co-workers constructed an optical-output ‘INHIBIT’logic gate utilizing structural switched DNA probe with the addition of targets (K ?or Pb 2?)[26,27].Kevin and co-workers reported a reagentless,molecular logic gates with electrochemical signal outputs by using electrochemical E-DNA sensor architectures on a mil-limeter-sized electrode [28].So far,most of DNA-based logic gates have been con-structed in bulk solution or on a macroscopic electrode at millimeter level,which hinders their in vivo applications.An electrode in micrometer or even nanometer diameter can be readily matched to the dimensions of cells and suitable for implantation in vivo [29,30].At SINAP,weThis work was supported by the National Natural Science Foundation of China (Nos.31470960and 21422508).Authors Tao Wei and Min Li contributed equally to this work.&Li-Hua Wangwanglihua@ &Xiao-Lei Zuozuoxiaolei@ &Yun Zhaozhaoyun@1Key Laboratory of Bio-Resources and Eco-Environment,Ministry of Education,College of Life Sciences,Sichuan University,Chengdu 610064,China2Division of Physical Biology and Bioimaging Center,Shanghai Synchrotron Radiation Facility,CAS KeyLaboratory of Interfacial Physics and Technology,Shanghai Institute of Applied Physics,Chinese Academy of Sciences,Shanghai 201800,China3Chemistry Department,King Saud University,Riyadh 11451,SaudiArabiaNUCL SCI TECH (2017)28:35DOI 10.1007/s41365-017-0191-1studied the application of gold nanoparticles in radiother-apy and synthesized gold nanostructures in different shapes [31–33].Besides,we developed the protocol to prepare gold flower microelectrode.By immobilizing with bio-logical probes,the gold flower microelectrode can be successfully used for small molecule (such as cocaine)detection,with fast response and high specificity [34].In this work,we used gold flower microelectrode and developed DNA XOR logic gates,which were based on two electrochemical biosensors for ATP and DNA detec-tions,respectively.The targets (ATP and DNA)and the denaturant urea were used as inputs,and changes in faradic current observed via square-wave voltammetry (SWV)caused by the presence or absence of targets were used as outputs (Scheme 1).2Experimental section2.1MaterialsCarbon fiber (U 7l m)was obtained from Toray Inc.(Japan).For microelectrode fabrication,glass capillaries (1.1mm outer diameter,0.9mm inner diameter)and copper wire (U 0.5mm)were from Sinopharm Chemical Reagent Co.Ltd (Shanghai,China).Graphite conductive adhesive was from Ted Pella (USA),and epoxy resin was from Zhongjingkeyi Technology Co.Ltd (Nanjing,China).DNA oligonucleotides modified with a six-carbon thiol (HSC6)and the redox-active methylene blue (MB)were synthetized and purified by Sangon Biotechnology Inc.(Shanghai,China),and their sequences were as follows:ATP sensor:50-HS-C6-ACCTGGGGGAGTATTGCG GAGGAAGGTTT-MB-30.cDNA sensor:50-HS-C6-GACACTGGATCGGCGTTT TATTGTGTC-MB-30.cDNA target:50AATAAAACGCCGATCCA30.6-Mercaptohexanol (MCH)and tris (2-carboxyethyl)phosphine hydrochloride (TCEP)were purchased from Sigma.Fetal bovine serum (FBS),qualified grade,was used as received from Life Technologies (Gibco).All other chemicals were of analytical grade,and all chemicals were used without further purification.All solutions were pre-pared using Milli-Q water (18.2M X Ácm -1)from a Milli-pore system.The buffers used were as follows:Gold electrodepositing solution included 20mM gold chloride and 0.5M hydrochloric acid.Tris buffer contained 20mM Tris,50mM MgCl 2,pH 8.0(TM buffer).The electrodes were rinsed in 0.1M PBS (PBS buffer).In total,10mM phosphate buffer (PB)contained 20mM MgCl 2,1M NaCl,pH 7.4(PB buffer).Electrochemical detection for methylene blue (MB)was performed in 10mM HEPES,500mM NaCl,pH 7.0(HEPES buffer).2.2Electrodes preparationGold flower microelectrode fabrication was carried out using well-established methods [35–37].Briefly,the glass capillary was pulled with a single-line heating and pulling program (Heat:290;Fil:4;Vel:60;Del:200;Pul:15)using a P-2000micropipette puller,leading to the pro-duction of two symmetric micropipette tips.Then,a single carbon fiber was attached to one end of a copper wire with graphite conductive adhesive and was carefullyinsertedScheme 1Design principle of electrochemical logic gates.In our design,the microelectrode with flower-like nanostructure was used to immobilize bio-probes.Here,a stem-loop structured DNA probe and an aptamer of ATP,both modified with methylene blue (MB),were employed.When the target DNA (cDNA)was introduced,the electron transfer (eT)of MB was blocked due to theconformational change of DNA structure;while when ATP was introduced,the eT was facilitated due to theconformational structure change of aptamer.(Color figure online)35Page 2of 6T.Wei et al.into the capillary with carbon fiber exposed to the fine open end of the capillary.The other end of the copper wire was sealed with epoxy resin.Burned and etched by flame of alcohol lamp carefully,the fine open end of the capillary was sealed with 1-mm-long carbon fiber protruding.In this way,the carbon fiber microelectrode (CFME)was acquired.Then,the gold nanoparticles (AuNPs)were electrochemically deposited on the pretreated CFME electrode in a solution of 20mM gold chloride and 0.5M HCl by applying a potential of 0V versus Ag/AgCl for 200s.Finally,rinse the gold flower microelectrodes with ultrapure water.2.3Fabrication and characterization of E-DNAsensor The cleaned gold electrodes were soaked in TM buffer containing 1l M DNA probes and 3mM TCEP and allowed to immobilize overnight at room temperature.The modified electrodes were then exposed to a 2mM MCH solution (in PB buffer)at room temperature for 1h to replace nonspecific interactions and form a self-assembled monolayer (SAM)that resisted nonspecific adsorption of target DNA.The electrode was rinsed with PBS buffer,and the electrochemical signals were detected using the tradi-tional electrochemical configuration of three-electrode system.An Ag/AgCl (3M KCl)was used as a reference electrode,and a platinum wire was used as counter elec-trode.Electrochemical workstation CHI 660B was used for electrochemical signal collection.The electrodes were incubated for 30min with appropriate concentration of target in HEPES buffer or 20%fetal calf serum mixed with HEPES buffer.Considering its high sensitivity,square-wave voltammetry (SWV)was employed for the determi-nation of ATP and cDNA.Relative signal changes in square-wave voltammetry peak current were calculated by subtracting the background current (SWV peak current in the blankbuffer).Fig.1Kinetics for the ATP (a )and DNA (b )sensors in the presence of 500nM of cDNA targets and 1mM of ATP,respectivelyFig.2a A schematic presentation of an XOR gate.To fabricate this two-input logic device,two electrochemical DNA probes described previously,i.e.,the E-DNA sensor [38–40],composed of a stem-loop oligonucleotide and E-AB sensor [38]composed of a ATP-binding DNA aptamer,attached together to a single gold flower microelec-trode via an alkane thiol and modified with a redox reporter.When interrogated via square-wave voltammetry (SWV),the probesresponded to their respective targets (a complementary DNA and ATP,respectively)via decreasing and increasing faradic current,respectively.b The probes of the logic device for which four input combinations lead to different electrochemical output currents via SWV.c The truth table for this two-input logic gate.d The symbol of this logic gateConstruction of DNA-based logic gates on nanostructured microelectrodes Page 3of 6353Results and discussionWe investigated the target-binding kinetics of the two electrochemical biosensors,respectively.The target-bind-ing processes were monitored by continuously recording the SWV current peak at -0.25V (Fig.1).The SWV current of ATP biosensor increased upon the ATP binding since the redox moiety (MB)approached the electrode surface to facilitate the electron transfer.As shown in Fig.1,the ATP sensor demonstrated fast kinetics with a saturated time of *5min.The SWV current of DNA biosensor decreased upon the DNA hybridization since the redox moiety (MB)was forced to separate from the elec-trode surface to block the electron transfer.Although the DNA sensor demonstrated relatively slower target-binding kinetics than that of ATP sensor,we could still obtain the saturated signal within 30min.A two-analyte XOR logic device was hen designed by immobilizing the two bioprobes on a single gold flower microelectrode,which compressed two input states into one output state,and the concentration of ATP and cDNA was defined as inputs,and the signal change of the faradic current resulted from methylene blue (MB)was defined as outputs.For input,we defined the presence of 1000l M ATP and 200nM cDNA as the ‘1’states,and lower (to 0M)concentrations as the ‘0’states.As outputs,we defined signal changes of greater than 5%and less than 5%as the ‘1’and ‘0’states,respectively.Thus,wecouldFig.3Adding denaturant urea into this two-input gate as the third input to produce a three-input logic gate.It could unfold DNA probe inducing decrease in faradic current upon SWV interrogation.a A schematic representation of this three-input logic gate and the activation of the gate using varying concentrations of ATP,DNA,and urea as inputs b The eight input combinations induced different changes of electrochemical currents.c Truth table for the three-input logic gate.d The symbol of this logicgateFig.4a Rinsing with 19PBS,signal regeneration of this dual-analyte sensor could recover more than 90%.b The dual-analyte device showed similar signal change both in buffer solution and in complex samples,such as 20%FBS (diluted with HEPES buffer)35Page 4of 6T.Wei et al.control the inputs(the concentration of ATP and DNA)to obtain a logic signal output and produce the truth table of our designed logic gate.The logic gate is shown schematically in Fig.2.From the truth table,if one,and only one,of the inputs to the gate is at‘1’state,the output is‘1’,while if both inputs are‘0’states or both are‘1’states,the logic gate produced an output‘0.’Thus,this label-free,dual-analyte device serves as a XOR logic gate. The logic device can be designed to monitor the ratio of two inputs.For example,when two inputs(ATP and cDNA)are controlled in optimal concentration ratio of 1000l M ATP:200nM cDNA,the logic gate output is‘0,’indicating that the system works well and the ratio of the two chemicals is under control.When the ratio of the two inputs shifts to a concentration ration of0l M ATP: 200nM cDNA,the output changes to‘1,’indicating a state out of control that should be adjusted.Based on the two-analyte logic device,we have also designed a three-input logic gate by using urea to this system as the third input.Urea can denature the structure of DNA probes and change the ability to transfer electrons. For input,we also defined the presence of1M urea as the ‘‘1’’state,and lower(to0M)concentrations as the‘‘0’’state.As before,we defined signal changes greater than5% and less than5%as‘‘1’’and‘‘0’’states,respectively.As a result,a three-input logic operation was constructed by controlling the concentrations of ATP,DNA,and urea.The truth table and schematic representation of this logic gate were presented in Fig.3.Regeneration and stability of the logic gate were stud-ied.The signal changed at the presence of the targets(ATP or DNA).Interestingly,through a simple rinsing by 19PBS,the signal could be recovered for more than90%. Furthermore,the logic gate performed well in relatively complex sample matrices(20%FBS)and(Fig.4).The logic device showed similar signal change both in buffer solution and in diluted FBS.Thus,the designed logic gates showed potential for the continuous monitoring in complex system.4ConclusionIn conclusion,we have constructed dual-analyte,DNA-based logic devices that functioned as an electrochemical XOR logic gate on the goldflower microelectrode.The combination of this logic gates and the goldflower microelectrode showed the advantages of electrochemical logic gate in signal readout.Most of the logic operations designed previously were realized throughfluorescence output and in solution phase[2,7,12,20–22,43,44], which may limit the connection between biological devices and electronics.Our design also reflected the application potential of ultramicroelectrode in applications of implantable device.Most of the electrochemical logic operations that designed previously were realized on microscopic electrode[28,42].For some biological applications such as applications in living cells and in situ monitoring small molecules released by living cells,the scale of the electrode should be decreased to micrometers and even nanometers tofit the scale of living cells.The use of macroscopic electrode would not accomplish such tasks or result in damaging of living cells[41,45–49]. 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