内嵌BRAM设计LIFO堆栈
深圳大学实验报告课程名称：数字系统现场集成技术实验项目名称：内嵌BRAM设计LIFO堆栈学院：信息工程学院专业：集成电路设计与集成系统指导教师：报告人：学号：班级：报告人：学号：班级：实验时间：实验报告提交时间：教务部制图1 VGA接口信号基本时序图图3 VGA(640*480@60Hz)时序图VGA显示的设计模块为：VGA显示模块clkrst_n vs hs r g b说明：设计中FPGA板的VGA接口将R，G，B分别设为定义为2位，3位，3位，例如显示红色RGB可以输出为11000000,绿色输出为00111000，蓝色输出为00000111.表1 25MHz 640*480@60Hz模式下VGA的时序五、ASM图lifo的控制状态图为：图5.1 lifo控制状态图图中的cnt为写进BRAM中的个数，所以减去1就是BRAM中的地址，write 和read的信号是按键的经处理后的脉冲。
RTL图：图5.1.1 顶层模块RTL图1 图5.1.2 顶层模块RTL图2-----------------------------------------------------------------------------2、div_clk模块代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity div_clk isgeneric (cnt : integer range 1 to 2**30 := 2**30); --分频系数port(clk : in std_logic;.CLK2X180(),.CLK90(),.CLK180(),.CLK270(),.LOCKED(),.PSDONE(),.STATUS()); endmoduleRTL图为图5.3.1 clkf倍频模块RTL图仿真代码为：module clk300m_tb;// Inputsreg clk;reg rst_p;// Outputswire clk_out;// Instantiate the Unit Under Test (UUT)clkf uut (.clk(clk),.rst_p(rst_p),.clk_out(clk_out));initial begin// Initialize Inputsclk = 0;rst_p = 0;// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #10 clk = ~clk;endmodule结果为：、图5.3.1 clkf倍频模块仿真因为clkfx_divide为1,clkfx_multiply为5，所以是倍频5倍，由图可看出刚好5倍，所以结果是对的。
-----------------------------------------------------------------------------4、sf采样模块此模块是采样滤波，只要是为了消抖。
//singal filtermodule sf #(parameter times = 20'b1111_0100_0010_0100_0000, //1000000width = 20)(clk,rst_n,in,out);input clk;input rst_n;图5.4.1 RTL图仿真代码为：`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company:// Engineer://// Create Date: 17:00:39 04/25/2016// Design Name: sf// Module Name: D:/my class/Digital system integration technology/lab3_lifo/lifo3/sf_tb.v // Project Name: lifo// Target Device:// Tool versions:// Description://// Verilog Test Fixture created by ISE for module: sf//// Dependencies://// Revision:// Revision 0.01 - File Created// Additional Comments://////////////////////////////////////////////////////////////////////////////////module sf_tb;// Inputsbegin#10 in = 1;#10 in = 0;end// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #5 clk = ~clk;endmodule结果为图5.4.2 仿真代码结果前面几段故意仿真不小心抖动一下按键，结果并不会产生信号，长按按键才会出现高电平。
-----------------------------------------------------------------------------5、psp电平转脉冲模块module psp #(parameter width = 2)(clk,rst_n,in,pulse);input clk;input rst_n;input [width-1:0] in;output [width-1:0] pulse;reg [width-1:0] in_r1 = {width{1'b0}};reg [width-1:0] in_r2 = {width{1'b0}};always@(posedge clk or negedge rst_n)if(!rst_n)beginin_r1 <= {width{1'b0}};in_r2 <= {width{1'b0}};endelsebeginin_r1 <= in;in_r2 <= in_r1;endassign pulse = ~in_r2 & in_r1;endmoduleRTL图：图5.6.1 RTL图图5.6.2 RTL展开图仿真代码：module psp_tb;parameter width = 3;// Inputsreg clk;reg rst_n;reg [width-1:0] in;// Outputswire [width-1:0] pulse;// Instantiate the Unit Under Test (UUT)psp #(width)uut (.clk(clk),.rst_n(rst_n),.in(in),.pulse(pulse));initial begin// Initialize Inputsclk = 0;rst_n = 1;in = 0;#1 rst_n = 0;#1 rst_n = 1;repeat(4)begin#40 in = 3'h1;#100 in = 3'h0;#40 in = 3'h2;#100 in = 3'h0;#40 in = 3'h4;#100 in = 3'h0;#40 in = 3'h7;#100 in = 3'h0;end// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #10 clk = ~clk;endmodule结果为：这是两个电平信号转换成相对应的脉冲信号，如结果所示，正确无误。
-----------------------------------------------------------------------------6、spf脉冲时间拉长模块always@(posedge clk or negedge rst_n)if(!rst_n)filter <= {width{1'b0}};elsefilter <= filter_pre;assign filter_pre = in_r3 ? {width{1'b0}} :(filter == times) ? filter :filter + 1'b1;always@(posedge clk or negedge rst_n)if(!rst_n)beginout_r <= 1'b0;endelsebeginout_r <= out_pre;endassign out_pre = (filter == times) ? in_r3 : (out_r | in_r3);assign out = out_r;endmoduleRTL图为：图5.6.1 RTL图仿真代码为：module spf_tb;由图看可达到想要的结果。
-----------------------------------------------------------------------------7、lifo模块此模块是控制RAM的读和写来实现lifo功能的。
module lifo(clk,rst_n,wr,rd,din,full,empty,num,//addr,wrdout, //writing datarddout //read data);input clk;input rst_n;input wr;input rd;input [3:0] din;output [3:0] num;output [3:0] wrdout;output [3:0] rddout;output full;output empty;//output [3:0] addr;wire [3:0] addr;reg [4:0] cnt = 5'h00;wire [4:0] cnt_pre;wire [3:0] ramdout;reg [3:0] rddout_r = 4'h0;wire [3:0] rddout_pre;reg [3:0] wrdout_r = 4'h0;wire [3:0] wrdout_pre;wire we;assign video_de = hs_de & vs_de;//generate point coordinate (x,y)assign video_x = hs_de ? (x_cnt - HSTPW - HSTBP + 1'b1) : {width_x{1'b0}};assign video_y = vs_de ? (y_cnt - VSTPW - VSTBP) : {width_y{1'b0}};//r,g,b控制液晶屏颜色显示assign video_r = video_de ? video_rgb[7:5] : 3'b000;assign video_g = video_de ? video_rgb[4:2] : 3'b000;assign video_b = video_de ? video_rgb[1:0] : 2'b00;endmoduleRTL图：图5.4.1 video_signal_gen 展开图测试代码为module vga256_tb;// Inputsreg clock;reg rst_p;// Outputswire vsync;wire hsync;wire vga_de;wire [1:0] vga_b;wire [2:0] vga_g;wire [2:0] vga_r;// Instantiate the Unit Under Test (UUT)vga256 uut (.clock(clock),.rst_p(rst_p),.vsync(vsync),.hsync(hsync),.vga_de(vga_de),.vga_b(vga_b),.vga_g(vga_g),.vga_r(vga_r));initial begin// Initialize Inputsclock = 0;rst_p = 0;//rst_n = 1;#1 rst_p = 1;#1 rst_p = 0;// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #5 clock = ~ clock;endmodule测试结果：图5.4.2 测试结果1图5.4.3 测试结果2之前本人有根据上面的时间计算过，确实是一个hs周期里有800个时钟，一个vs周期里有525个时钟，所以大胆猜测是对的，烧到板子上果然是对的。
氯化铯离子晶体的嵌套结构和马德隆常数的迭代计算
氯化铯离子晶体的嵌套结构和马德隆常数的迭代计算
马德隆常数( Madelung constant )是一种测量离子晶体立方排布的模式的系数。
它描述了
一种离子晶体里相邻离子之间的势垒，因此也被称作势垒系数或势垒常数。
马德隆常数可
以运用于离子化合物中具有立方对称性和非常定离子处理的多种物质，如金刚石晶体和卤
素晶体，如氯化铯晶体。
马德隆常数是一个有深度的计算式，它的计算方法包括使用离子晶体的嵌套结构和迭代计算法。
嵌套结构( nested structure )描述了晶体中离子的立方排列模式，它有多种类型，变化的范围也极其恢宏。
比如氯化铯晶体是个典型的嵌套结构，一开始只有离子核，沿着每个价态在晶体中交替排列着，就像一堆彼此挤压着却不会消失的中国结一样，每一种价态都有一
定的可持续排布模式，这就是嵌套结构。
第二步就是迭代计算法，它是一个不断重复计算相互作用势垒的过程。
首先，重复使用某
种数值解法，如梯度消去法( GR )结合嵌套结构模型，计算嵌套的每一部分的势垒的大小。
然后用马德隆定律将这些势垒大小累乘结果，得到Madelung常数。
最后，这一迭代计算又要重复进行，重新计算新的嵌套结构的大小，以及势垒的强度。
一
般而言，只有当势垒的强度变化得非常小时，整个迭代计算才会停止，以确保该离子晶体
中每个价态离子核处于能量最低状态。
以上就是使用离子晶体的嵌套结构和马德隆常数的迭代计算法计算Madelung常数的详细
过程。
它是一种复杂的计算方法，是对物质的一个很好的物理分析，其成果可以在实验研究中得到验证和利用。
嵌入式快速3D界面框架的设计与实现
嵌入式快速3D界面框架的设计与实现林梅燕;杨盛国;彭井花【摘要】目前随着嵌入式设备的功能越来越强大,人们对嵌入式的界面和游戏性能的要求也越来越高。
但3D界面开发周期长,针对以上问题提出了一个基于嵌入式3D界面的快速开发框架,该嵌入式界面框架已应用在Android Launcher程序实践中,呈现出流畅、实用的3D界面效果,为Android设备的界面差异化、定制化提供了一种途径。
%As embedded devices become more powerful,people are more dependent on the performance of the embedded interface and game.Since the 3D interface takes a long development cycle,this paper proposes a rapid development framework based on embedded 3D interface.The embedded interface framework has been used in the program practice of Android Launcher,showing a smooth,practical 3D interface effects.It also provides a way for the Android device interface being differential.【期刊名称】《福建师大福清分校学报》【年(卷),期】2012(000)005【总页数】6页(P23-28)【关键词】界面框架;3D;嵌入式;OpenGL;ES;动画框架【作者】林梅燕;杨盛国;彭井花【作者单位】福州大学阳光学院电子信息工程系,福建福州350005;福州大学阳光学院电子信息工程系,福建福州350005;福州大学阳光学院电子信息工程系,福建福州350005【正文语种】中文【中图分类】TP3910 引言目前，嵌入式技术的应用越来越广泛，已经渗透到我们生活的各个领域，因此开发一个优秀的图像界面是非常有必要的，但设计一个良好的界面首要条件是使人机交互更加方便快捷、画面更加形象逼真。
嵌入式图片滑动的3D桌面设计
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IEC61400-1-2005风电机组设计要求标准英汉对照
需要什么文档直接在我的文档里搜索比直接在网站大海捞针要容易的多也准确省时的多
INTERNATIONAL STANrbines – Part 1:
Design requirements
Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in the 60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
Further information on IEC publications The technical content of IEC publications is kept under constant review by the IEC, thus ensuring that the content reflects current technology. Information relating to this publication, including its validity, is available in the IEC Catalogue of publications (see below) in addition to new editions, amendments and corrigenda. Information on the subjects under consideration and work in progress undertaken by the technical committee which has prepared this publication, as well as the list of publications issued,is also available from the following: IEC Web Site (www.iec.ch) Catalogue of IEC publications The on-line catalogue on the IEC web site (www.iec.ch/searchpub) enables you to search by a variety of criteria including text searches,technical committees and date of publication. Online information is also available on recently issued publications, withdrawn and replaced publications, as well as corrigenda. IEC Just Published This summary of recently issued publications (www.iec.ch/online_news/justpub) is also available by email. Please contact the Customer Service Centre (see below) for further information. Customer Service Centre If you have any questions regarding this publication or need further assistance, please contact the Customer Service Centre: Email: custserv@iec.ch Tel: +41 22 919 02 11 Fax: +41 22 919 03 00 .
使用Android SwipeRefreshLayout了解Android的嵌套滑动机制
使用Android SwipeRefreshLayout 了解Android的嵌套滑动机制SwipeRefreshLayout 是在Android Support Library, revision 19.1.0添加到support v4库中的一个下拉刷新控件，关于android的下拉刷新框架现在有好多，曾经用过XListView，现在工作中基本上无需用到下拉刷新的功能。
废话不多说了，这里来记录一下android自带的刷新控件SwipeRefreshLayout的使用，借此顺便来熟悉一下android在Lollipop版本推出的嵌套滑动机制（NestedScrolling）。
首先来看SwipeRefreshLayout的使用，使用很简单，看一下布局文件[html]view plain copy1.<?xml version="1.0"encoding="utf-8"?>2.<android.support.v4.widget.SwipeRefreshLayout xmlns:android="http://schemas./apk/res/android"3.xmlns:tools="/tools"4.android:id="@+id/swiperefresh"5.android:layout_width="match_parent"6.android:layout_height="match_parent"7.tools:context=".recyclerviewdemo.RecyclerViewActivity">8.9.<android.support.v7.widget.RecyclerView10.android:id="@+id/my_recycler_view"11.android:layout_width="match_parent"12.android:layout_height="wrap_content"/>13.</android.support.v4.widget.SwipeRefreshLayout>注意SwipeRefreshLayout只能有一个直接的子View。
智能融合2和冰雪2嵌入式非易失性存储（eNVM）模拟说明书
SmartFusion2 and IGLOO2 Embedded Nonvolatile Memory (eNVM) SimulationSmartFusion2 and IGLOO2 Embedded Nonvolatile Memory (eNVM) Simulation Table of ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31NVM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42eNVM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 eNVM Internal Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 eNVM Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63eNVM Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Writing to the eNVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reading from the eNVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Erasing the eNVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Product Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12IntroductionThe SmartFusion2 MSS has an on-chip embedded non-volatile memory (eNVM). You can access theeNVM using the eNVM controller. This controller is a slave of the MSS AHB Switch Matrix and canreceive commands from a master located either inside the MSS (i.e., Cortex M3) or a master located inthe fabric via the Fabric Interface Controllers (FIC_0 or FIC_1).This document describes the steps required to simulate eNVM operation.1 – NVM ConfigurationYou can configure the eNVM using the MSS eNVM configurator. Using the eNVM configurator, you can:•Add Serialization and Data Storage clients•Supply data files that will be used to initialize the eNVM block when you program your device For details, and to learn about the eNVM configurator options, refer to the SmartFusion2 MSS eNVMConfiguration Guide.2 – eNVM OrganizationThis chapter describes the internal organization of the eNVM, and how it is accessed by Masters in the MSS and the FPGA fabric.The eNVM is a nonvolatile (flash) memory that is divided into pages. Each page of the eNVM contains 128 bytes (accessible as 32 words).The total capacity of the eNVM varies with the SmartFusion2 or IGLOO2 device you are using. Table 2-1 provides a list of devices and eNVM capacities.Note:On the larger (M2S/M2GL090/150) devices, the eNVM is composed of two blocks (eNVM_0 andeNVM_1), which are accessed separatelyeNVM Internal OrganizationEach eNVM is divided into pages. One page is a 128-byte section of the eNVM. The eNVM is word-addressable. Table 2-2 and Table 2-3 list the ranges of the eNVM pages for different devices.Table 2-1 • eNVM Capacity by Device DeviceeNVM capacity (bytes)SmartFusion2M2S0051 x 128KB M2S010, M2S025, M2S050, M2S0601 x 256KB M2S090, M2S1502 x 256KB IGLOO2M2GL0051 x 128KB M2GL010, M2GL025, M2GL050, M2GL0601 x 256KB M2GL090, M2GL1502 x 256KBTable 2-2 • SmartFusion2 eNVM Page RangesDevice Capacity Total Pages (User + Reserved)Total Reserved Pages User Page Range (Available to User) Reserved Page Range(Unavailable to User)M2S005128KB1024160-10071008-1023M2S010, M2S025, M2S050256KB2048160-20312032-2047M2S050T_ES256KB2048330-20142015-2047Note:For IGLOO2, Reserved Pages are used by the HPMS to store Certificate/Digest and Peripheralconfiguration data for SERDES, FDDR and MDDR. For SmartFusion2, Reserved Pages are used by the MSS to store Certificate/Digest only. Reserved pages are for internal use only and not available to the user.eNVM AccessThe SmartFusion2 eNVM is part of the MSS. It is accessed via the eNVM Controller, which is a slave of the MSS AHB Switch Matrix (Figure 2-1). Masters of the AHB Switch Matrix (MSS Cortex-M3), a Fabric Master (via the FIC32_0/1 interfaces) can read from and write to the eNVM.•All eNVM accesses are performed using AHB read and write transactions•Irrespective of the master initiating the access, the procedure to read and write the eNVM remains the sameM2S060256KB 2048640-19831984-2047M2S090, M2S150512KB4096640-40314032-4095Table 2-2 • SmartFusion2 eNVM Page Ranges (continued)Device Capacity Total Pages (User + Reserved)Total Reserved Pages User Page Range (Available to User) Reserved Page Range(Unavailable to User)Table 2-3 • IGLOO2 eNVM Page RangesDevice Capacity Total Pages (User+Reserved)Total Reserved Pages User Page Range (Available to User) Reserved PageRange(Unavailable to User)M2GL005128KB 1024480-975976-1023M2GL010,M2GL025, M2GL050256KB 2048480-19992000-2047M2GL060256KB 2048960-19511952-2047M2GL090, M2GL150512KB4096960-39994000-4095Figure 2-1 • eNVM Access3 – eNVM SimulationThe eNVM simulation model fully models the commands and bus transactions required to access theeNVM on silicon.To access the eNVM, you must initiate AMBA transactions using either the Cortex-M3 Master or a FabricMaster (Using the FIC Slave Interface).Before accessing the eNVM, Microsemi recommends that you poll bit #0 of the eNVM status register(address: 0x60080120). If this bit is 0, the eNVM is busy. Wait until this bit becomes 1 to access theeNVM.Writing to the eNVMYou can simulate writing to eNVM from the following bus masters:•Cortex-M3 (SmartFusion2 only)•Fabric AHB Master (via FIC_0 or FIC_1)•Fabric APB Master (via FIC_0 or FIC_1)Writes to the eNVM are buffered. You must first write your data into the write data buffer (WDB) and thenuse a single command to commit (program) your data into one page of the eNVM.The sequence of transactions required to program the eNVM is:1.Request exclusive access to the eNVM control register set. This is necessary to ensure that noother Master can write to the eNVM at the same time, and is done by writing 0x1 to theREQACCESS register (address: 0x600801FC)The Master that is requesting exclusive access must then check that the request has beengranted by reading back from the REQACCESS register.–On read back, check bit #2 (counting up from 0). If it is 1, the request was successful.–If bit #2 is 0, the request for exclusive access was denied, and the eNVM cannot be written at this time.2.Write your data into the WDB; the WDB is a byte-addressable 1024-bit buffer. Its base address is:0x60080080 for eNVM_0 and at 0x600C0080 for eNVM_1.pute values of bits that will be written into the eNVM Command Register:–Bits 31-24 should be 0x80 (Hex) to specify the ProgramADS command code.–Bits [17:7] corresponds to the eNVM page address to be written–Bits [23:18] and [6:0] are not relevant for the ProgramADS command and can be written 0x0 (Hex)For details about what values to use, refer to Table 4-7 in the SmartFusion2 Microcontroller SubsystemUser's Guide.4.Write eNVM Command Register (address: 0x60080148) with the data computed in Step 3 aboveNote that the eNVM will not respond to further commands until the write is completeNote that on silicon, writing a page of the eNVM may take up to 8ms, but in simulation, this stepcompletes in a few clock cycles5.Release exclusive access to the eNVM control register set by writing 0x0 to the REQACCESSregister.The following is an example of a Cortex-M3 BFM script configured to write a block of data to eNVM0.Assume that you want to write two 32-bit words 0xaaaaaaaa and 0xbbbbbbbb into page 25 of the eNVM.#1. Wait for bit 0 of status register to become 1pollbit w 0x60080120 0x0 0 1#2. Request exclusive access to the eNVM control register setwrite w 0x600801fc 0x0 0x1#2b. Readcheck to see if access has been grantedreadcheck w 0x600801fc 0x0 0x5 (for MSS master)#The simulation will fail if access has not been granted#3. Write data to the WDBwrite w 0x60080080 0x0 0xaaaaaaaawrite w 0x60080080 0x4 0xbbbbbbbb#4. Compute the value of the command register: Bits[31-19]: '0000 1000 0000 0'#Bits[18-7]: '000 0000 1100 1' (25 in decimal)#Bits[6-0]: '000 0000'#Complete string: 0x08000c80#5. Write the command registerwrite w 0x60080148 0x0 0x08000c80#6. Release exclusive access to the eNVMwrite w 0x600801fc 0x0 0x0Refer to the SmartFusion2 FPGA Microcontroller Subsystem BFM Simulation Guide for generalguidelines on BFM simulations for SmartFusion2 designs.Reading from the eNVMThe eNVM can be read as a byte-addressable random access memory. The address range for reads isgiven in Table3-1.Table3-1 • eNVM Read Address RangesENVM0ENVM1Base Address0x600000000x60040000Max read address (005)0x6002FFFF N/AMax read address (010,025,050, 060)0x6003FFFF N/AMax read address (090,150)0x6003FFFF 0x6007FFFF The eNVM is accessible directly, similar to a random access memory. The address ranges of the eNVMsare given in Table3-1. To read any location in the eNVM, first compute the offset address as follows:Offset Address = (Page #) * 0x80 + (Address of Word in Page)The Base Address will be either 0x60000000 or 0x60040000, depending on whether you are accessingeNVM_0 or eNVM_1.The following is an example that demonstrates how to read data from eNVM_0. In the example above,two 32-bit words "0xaaaaaaaa" and "0xbbbbbbbb" were written into addresses 0x0 and 0x4 of Page# 25of eNVM_0. The example below shows an attempt to read the same two words back.#1. Wait for bit 0 of status register to become 1pollbit w 0x60080120 0x0 0 1#2 Read first word#2a Base Address = 0x60000000#2b Word in Page = 0x0 (first word). Page Number = 25.# Offset Address = 0x80 * 25 + 0x0 = 0xc80#2c Read and compare word to what was written in Fig. 2readcheck w 0x60000000 0xc80 0xaaaaaaaa#3 Read second word#3a Base Address = 0x60000000#3b Word in Page = 0x4 (second word). Page Number = 25.# Offset Address = 0x80 * 25 + 0x4 = 0xc84#3c Read and compare word to what was written in Fig. 2readcheck w 0x60000000 0xc84 0xbbbbbbbbErasing the eNVMYou can also erase the contents of the eNVM, one page at a time using the following steps:1.Request exclusive access to the eNVM control register set. This is necessary to ensure that noother Master can write to the eNVM at the same time. This is done by writing 0x1 to theREQACCESS register (address: 0x600801FC). The Master that is requesting exclusive accessmust then check that the request has been granted by reading back from the REQACCESSregister.–On read back, check bit #2 (counting up from 0). If it is 1, the request was successful.–If bit #2 is 0, the request for exclusive access was denied, and the eNVM cannot be written at this time.pute values of bits that will be written into the eNVM Command Register:–Bits 31-20: "0x020"–Bit19:0–Bits 18-7 corresponds to the number of the page to be written–Bits 6-0: “0x0"3.Write eNVM Command Register (address: 0x60080148) with the data computed in the previousstep.The eNVM will not respond to further commands until the erase is complete.Note that on silicon, erasing a page of the eNVM may take up to 8ms, but in simulation, this stepcompletes in a few clock cycles.4.Release exclusive access to the eNVM control register set by writing 0x0 to the REQACCESSregister.The example below shows a sequence of instructions to erase page #25 of eNVM_0.#1. Wait for bit 0 of status register to become '1'pollbit w 0x60080120 0x0 0 1#2. Request exclusive access to the eNVM control register setwrite w 0x600801fc 0x0 0x1#2c. Readcheck to see if access has been grantedreadcheck w 0x600801fc 0x0 0x5 (for MSS master)#The simulation will fail if access has not been granted#3. Compute the value of the command register: Bits[31-19]: '0000 0010 0000 0'#Bits[18-7]: '000 0000 1100 1' (25 in decimal)#Bits[6-0]: '000 0000'#Complete string: 0x02000c80#4. Write the command registerwrite w 0x60080148 0x0 0x02000c80#5. Release exclusive access to the eNVMwrite w 0x600801fc 0x0 0x04 – Product SupportMicrosemi SoC Products Group backs its products with various support services, including CustomerService, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.This appendix contains information about contacting Microsemi SoC Products Group and using thesesupport services.Customer ServiceContact Customer Service for non-technical product support, such as product pricing, product upgrades,update information, order status, and authorization.From North America, call 800.262.1060From the rest of the world, call 650.318.4460Fax, from anywhere in the world, 408.643.6913Customer Technical Support CenterMicrosemi SoC Products Group staffs its Customer Technical Support Center with highly skilledengineers who can help answer your hardware, software, and design questions about Microsemi SoCProducts. The Customer Technical Support Center spends a great deal of time creating applicationnotes, answers to common design cycle questions, documentation of known issues, and various FAQs.So, before you contact us, please visit our online resources. It is very likely we have already answeredyour questions.Technical SupportVisit the Customer Support website (/soc/support/search/default.aspx) for moreinformation and support. Many answers available on the searchable web resource include diagrams,illustrations, and links to other resources on the website.WebsiteYou can browse a variety of technical and non-technical information on the SoC home page, at/soc.Contacting the Customer Technical Support CenterHighly skilled engineers staff the Technical Support Center. The Technical Support Center can becontacted by email or through the Microsemi SoC Products Group website.EmailYou can communicate your technical questions to our email address and receive answers back by email,fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.We constantly monitor the email account throughout the day. When sending your request to us, pleasebe sure to include your full name, company name, and your contact information for efficient processing ofyour request.The technical support email address is **********************.5-02-00498-2/07.15Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. 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Learn more at .Microsemi Corporate HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail:***************************©2015 Microsemi Corporation. All rightsreserved. Microsemi and the Microsemilogo are trademarks of MicrosemiCorporation. All other trademarks andservice marks are the property of theirrespective owners.My CasesMicrosemi SoC Products Group customers may submit and track technical cases online by going to My Cases .Outside the U.S.Customers needing assistance outside the US time zones can either contact technical support via email (**********************) or contact a local sales office. Sales office listings can be found at /soc/company/contact/default.aspx.ITAR Technical SupportFor technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via ***************************. Alternatively, within My Cases , select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the I TAR web page.。
堆叠设计 过程
堆叠设计过程在当今的设计领域中，堆叠设计是一种常用的设计技术，它通过将不同的层次和元素组合在一起，创造出丰富多样的视觉效果和用户体验。
本文将详细介绍堆叠设计的过程，旨在帮助设计师们更好地理解和应用这种设计方法。
第一步：明确设计目标在进行堆叠设计之前，我们首先要明确自己的设计目标。
这包括确定设计的用途、目标受众以及传达的信息。
只有明确了设计目标，我们才能有针对性地选择合适的层次和元素进行堆叠。
第二步：收集素材和准备资源在开始设计之前，我们需要收集和准备好所需的素材和资源。
这包括文字、图片、图标、背景等。
素材的选择要与设计目标相契合，并且要注意版权和可用性的问题。
准备充足的资源可以为后续的设计工作提供便利。
第三步：构建基本结构在进行堆叠设计时，我们首先需要构建一个稳定的基本结构。
这个基本结构可以是一个网格系统、一个页面框架或者一个界面布局。
通过建立基本结构，我们可以更好地控制元素的位置和排列，使设计更加有层次感和结构性。
第四步：选择合适的层次和元素在基本结构建立之后，我们需要选择合适的层次和元素进行堆叠。
这包括文字、图片、图标、按钮等。
在选择时，我们要考虑元素之间的关系和视觉效果，使它们能够相互补充和协调，形成一个整体。
第五步：调整样式和效果选择了合适的层次和元素之后，我们需要对它们进行样式和效果的调整。
这包括颜色、字体、大小、动画等。
样式和效果的选择要与设计目标相一致，突出重点，增加表现力和吸引力。
第六步：优化与调试在完成初步设计之后，我们需要对设计进行优化和调试。
这包括对页面加载速度、响应式设计以及用户体验等方面进行测试和改进。
只有经过不断优化和调试，我们的设计才能更加完善和出色。
第七步：评估和反馈最后一步是对设计进行评估和反馈。
我们可以邀请用户或同行进行评估，收集他们的意见和建议。
通过评估和反馈，我们可以了解设计的优点和不足之处，进一步改进和完善设计。
堆叠设计是一种重要的设计方法，它可以为我们创造出丰富多样的视觉效果和用户体验。
堆栈的总结
堆栈的总结什么是堆栈？在计算机科学中，堆栈（Stack）是一种线性数据结构，符合LIFO（Last In First Out）的原则。
LIFO意味着最后入栈的元素首先被弹出。
堆栈的操作包括压入（push）和弹出（pop），以及查看堆栈顶部元素（top）的值。
堆栈的特性堆栈具有以下特性：1.LIFO原则：最后入栈的元素首先被弹出。
2.仅访问顶部元素：堆栈只允许访问顶部元素，其他元素只有通过弹出操作才能访问。
3.有限容量：堆栈的大小有限，当容量达到上限时，再进行压栈操作会导致堆栈溢出。
4.轻量级：由于堆栈只需维护栈顶指针和元素数据，并不需要为每个元素分配内存空间，因此堆栈是一种轻量级的数据结构。
堆栈的应用堆栈在计算机科学中有广泛的应用，以下是一些常见的应用场景：函数调用在编程语言中，堆栈被用于保存函数调用的上下文信息。
每当一个函数调用另一个函数时，当前函数的状态（包括局部变量、函数参数和返回地址）都被压入堆栈。
当被调用函数执行完毕后，堆栈顶部的帧被弹出，程序流程回到调用函数的位置。
表达式求值在编程语言中，堆栈被用于解析和计算表达式。
具体地，中缀表达式通常被转换为后缀表达式后，通过堆栈来进行求值。
算法依次扫描表达式，遇到操作数时将其压入堆栈，遇到操作符时弹出必要数量的操作数进行计算，并将计算结果压入堆栈，直到整个表达式求值完成。
括号匹配堆栈常被用于检查表达式中的括号匹配情况。
算法通过扫描表达式，遇到左括号时将其压入堆栈，遇到右括号时弹出一个左括号进行匹配，如果堆栈为空或弹出的括号与当前右括号不匹配，则表示括号不匹配。
撤销操作在许多应用程序中，我们经常需要实现撤销操作。
对于这种情况，堆栈被用于保存操作的历史记录。
每当执行一个操作时，操作的结果被压入堆栈，当需要撤销操作时，只需弹出堆栈顶部的操作结果。
堆栈的实现堆栈可以通过数组或链表来实现。
以下是两种常见的实现方式：数组实现在数组实现中，可以使用固定大小的数组来表示堆栈。
Turbo C＋＋2.0实现堆栈式图形画面存取
Turbo C＋＋2.0实现堆栈式图形画面存取
李里
【期刊名称】《软件世界》
【年(卷),期】1994(000)005
【摘要】Turbo C++ 2.0具有丰富的图形功能,在我们用其编写各种窗口程序和菜单时,常常需要保存图形,而Turbo C++ 2.0本身提供的存取图形函数,是把图形放在内存中。
这样图形画面的大小和数量就受到内存的限制。
如果通过把图形页写到磁盘的方法来到达目的,则受到图形页缓冲区地址,程序兼容性差的限制。
为此,笔者通过在内存中构造一个堆栈表对其管理。
【总页数】2页(P28-29)
【作者】李里
【作者单位】无
【正文语种】中文
【中图分类】TP391.41
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2.用Turbo C实现图形方式下汉字菜单 [J], 邸剑
3.Turbo C 2.0实现堆栈式图形画面的存取 [J], 李里
4.Turbo C通用图形菜单的设计与实现 [J], 魏文平;马石安
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7HFKQRORJ\ PDSSLQJ XVLQJ 6,6Laboratory 2in course “Logic synthesis”2002-versionWritten by Tomas Bengtsson and Shashi KumarÃÃ,QWURGXFWLRQ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'RFXPHQWV QHHGHG IRU WKLV ODEBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6KRUW LQWURGXFWLRQ WR )3*$V BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7DVNV BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHU BBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUN BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'HVFULSWLRQ RI H[DPSOH BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6RPH WLSVBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7KH H[DPSOH WKURXJK 6,6BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBDecomposition_____________________________________________97.3.1. Gate7.3.2. LUTMapping_________________________________________________11commands_______________________________________127.3.3. Post-processing7.3.4. Programmable Logic Block Generation_____________________________14ÃÃ,QWURGXFWLRQAfter a circuit has been optimized using Logic Optimization tools, the next step is to bring the circuit closer to implementation by using the available information about implementation technology. This step is called Technology Mapping. This step involves converting the abstract description (FSM or Boolean functions) of the circuit to a network of limited type of components, normally from a library of components. Due to this reason, Technology Mapping is also sometimes referred as Library Binding. This step involves, selecting components from the library and forming a network of these components. Normally the objectives in Technology Mapping are to have the final implementation using a minimum number of components or to minimize the area of the implementation.Technology mapping to an FPGA results in the final implementation suitable for a specific FPGA type from a specific company. This is because the internal architecture of FPGAs from different companies is quite different. The internal architectures of various FPGAs from the same company also differ depending on the component series. For example, XILINX 4000 series FPGA has different type of logic blocks as compared to 3000 series. There are two further steps after a circuit has been converted to a network of blocks of a FPGA. These steps are called 3ODFHPHQW and 5RXWLQJ. In the placement step, the logic blocks in the network are assigned specific physical blocks within the FPGA. In the routing step, the used logic blocks are connected using programmable interconnection resources.In this laboratory, we are only concerned with the first step, which is converting the abstract design to a network of logic blocks for Xilinx FPGA family.'RFXPHQWV QHHGHG IRU WKLV ODEAmong the documents from the first lab you will need the document from UCLA (University of California Los Angeles), which describes the extension of SIS for technology mapping. In this document we recommend you to skip the first part and start reading the part starting with a header “Commands provided by UCLA FPGA Mapping Package”. This documents can be found in Appendix A of this lab manual.A “hand-in” form that you have to fill in to pass the lab is also given. That hand in form and this lab manual can be found in Pingpong.5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODETo be able to use the lab time more efficient we recommend you to study the document from UCLA the part mentioned in section 2 “Documents needed for this lab”. It is also recommended that you complete the task described in section 6.1 “Task 1 Making scripts for technology mapping” before the lab.ÃÃ6KRUW LQWURGXFWLRQ WR )3*$VFPGAs are one family of programmable logic circuits. An FPGA contains programmable logic blocks and programmable interconnection between the blocks. The programmable blocks are called CLBs (Complex Logic Block). The CLBs contain one or more LUTs (Look Up Table). A LUT is a combinatory device with some inputs and one output. It can be programmed to realize any Boolean function. The CLB can be programmed so the output of the LUTs goes to the output of the CLB direct or via a flip-flop. This can be done individually for every LUT. The inputs to the CLB are connected to the inputs in the LUTs. If the CLB contains more than one LUT, some inputs to the CLB may be connected to inputs in more than one LUT.To connect outputs and inputs of CLBs to other CLBs and to the ports of a chip the programmable interconnection part is used. In this lab we are not going to deal with this. We are only going to map logic into fit CLBs. We will use some old FPGAs, Xilinx3000 – series and Xilinx4000 – series. For our purpose we don’t gain anything by using newer ones. The CLBs in both series has two LUTs. The LUTs in Xilinx3000 – series has four inputs and in Xilinx4000 – series they have five inputs.The picture below shows an example of a simple CLB. The CLBs we will use in this lab looks a little different.,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODEAs written in the previous section the LUTs in Xilinx 3000-series have four inputs each and in Xilinx 4000-series the LUTs have five inputs each. The parameter “-k” used in many technology-mapping commands should specify number of inputs to one LUT.ÃÃ7DVNV7DVN 0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJIn this task you should prepare scripts for technology mapping. Make one script containing technology-mapping commands, which makes optimization with respect to area minimization for mapping to Xilinx 3000-series. Make another script doing the same but for minimizing the depth of the circuit. Copy those scripts and modify the copies to work for Xilinx 4000-series. You don’t need to put the final commands “match_3k” and “match_4k” into the scripts. You can write those commands in the SIS-prompt when you need them instead.Fill in the scripts in the “hand-in” form.7DVN 7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUIn this task you should use your multiplier from the previous lab and make technology mapping in some different ways. In this lab you should alter the following parameters:• You can either use technology-independent optimization before you make technology mapping or you can skip technology-independent optimization. When you are making technology-independent optimization in this task you should use “rugged-script”• You can optimize for area or for depth. To do this you should use your scripts from the previous task.• You can technology-map for either Xilinx 3000-series or Xilinx 4000-series.The alternatives enumerated above makes eight different combinations of optimizations. Make those and fill in the required results in the “hand-in” form. There are also some questions in the “hand-in” form you should answer.7DVN 7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHUIn this task you should use the “Gray-code to binary converter” you have made in the previous lab. The task is to technology-map it so it fits into two CLBs in Xilinx 3000-series. Do this and answer the questions in the “hand-in” form!7DVN 7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUNIn this task you should technology-map the benchmark “t481.pla”. You should map it so that it only requires five LUTs in Xilinx 3000-series. This is the goal of this task and you decide what should be done to get there. Answer the questions in the “hand-in”-form!$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ'HVFULSWLRQ RI H[DPSOHTo describe an example of technology mapping, an FSM to control one traffic light is used. This traffic-light controller is nothing that can be used in traffic rather it can be used to show a traffic light fitting in a fair. The controller is made as a Moore-machine.ÃÃThe FSM has three inputs. The first input let the traffic-light run in normal mode if it’s “0”, and in a mode with twinkle amber (amber ≈ yellow) if it is “1”. In the normal mode the traffic light is red, green or it is on its way between. If the second input is “1”, when the traffic light is green, it is forced to red via amber. If the third input is “1”, when the traffic light is red, it is forced to green via red_amber.The outputs from the FSM are signals to the three lamps. It is in the order green, amber and red, and “1” means on.The state-diagram below shows the system.ÃÃA description of this in kiss-format is shown below:.start_kiss.i 3.o 300- green green 10001- green amber 1001-- green twinkle_amber 1000-- amber red 0101-- amber twinkle_dark 0100-0 red red 0010-1 red red_amber 0011-- red twinkle_amber 0010-- red_amber green 0111-- red_amber twinkle_amber 0110-- twinkle_amber red 0101-- twinkle_amber twinkle_dark 0100-- twinkle_dark amber 0001-- twinkle_dark twinkle_amber 000.end_kiss.endThis file is available as “/home/beto/public/logic_synthesis/traf.kiss” in the UNIX-system.6RPH WLSVIt’s good to use commands like “print_stats” and “print_level” to see what is happening between the different steps in the optimization and mapping process. Also remember that “write_blif” can give some useful information in some cases.7KH H[DPSOH WKURXJK 6,6First we make the technology independent optimization. (That is what the first laboratory was about.) We use “state_minimize”, “state_assign” and then run “rugged-script”. We then get: UC Berkeley SIS with UCLA FPGA Extension (compiled 2-Apr-98 at 11:09 PM) VLV! UHDGBNLVV WUDI NLVV.start_kissVLV! VWDWHBPLQLPL]HRunning stamina, written by June Rho, University of Colorado at Boulder Number of states in original machine : 6Number of states in minimized machine : 5VLV! VWDWHBDVVLJQRunning nova, written by Tiziano Villa, UC BerkeleyWarning: network ‘SISEAAa29918’, node "v0" does not fanoutWarning: network ‘SISEAAa29918’, node "v1" does not fanoutWarning: network ‘SISEAAa29918’, node "v2" does not fanoutVLV! VRXUFH UXJJHGVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1ÃÃ.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names OUT_0 LatchOut_v4 OUT_201 1.names v6.1 v6.2 LatchOut_v5 v6.011- 11-0 1.names IN_0 IN_1 OUT_1 OUT_2 LatchOut_v5 v6.10-1-- 10--1- 100--0 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_1ÃÃ10- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endThe key-word “.exdc” means that the following blif-description is the don’t-care-set. The description above is the optimized description of the function where don’t-cares are forced to one and zero to make the function as small as possible.*DWH 'HFRPSRVLWLRQIn the description of technology mapping from UCLA, it’s written that command“tech_decomp” should be run before “dmig”-command is run. The parameter “-k 4” in the “dmig”-command is chosen to 4 because the plan is to map this to an FPGA with 4-input LUTs.VLV! WHFKBGHFRPS D RVLV! GPLJ NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_1ÃÃ00 1.names OUT_0 LatchOut_v4 OUT_201 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names [23] [24] v6.21- 1-1 1.names v6.1 LatchOut_v5 [21]10 1.names v6.1 v6.2 [22]11 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 [23]0011 1.names LatchOut_v4 LatchOut_v5 [24]00 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 OUT_2 [26]01 1.names IN_0 OUT_1 [27]01 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endÃÃ/87 0DSSLQJWhen gate decomposition is done there are some commands to choose between, which map the function to LUTs (Look Up Tables).VLV! GDJPDS NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 1ÃÃ0-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5.outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3RVW SURFHVVLQJ FRPPDQGVThe post-processing command “mpack” can for some cases merge two LUTs into one LUT. VLV! PSDFN NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 010ÃÃ0-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 10-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1ÃÃ.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3URJUDPPDEOH /RJLF %ORFN *HQHUDWLRQIn our installation of SIS it is possible to map to Xilinx 3000 and 4000 –series.VLV! PDWFKB N Y##PI=3 #PO=3 #LUT=11 #CLB=6 #LEVEL=3#0001: ( OUT_2 , v6.2 )#0002: ( OUT_1 , [26] )#0003: ( OUT_0 , [27] )#0004: ( v6.1 , [21] )#0005: ( v6.0 , [25] )#0006: ( [22] ) sis> match_3k -vThe argument “-v” makes it print the list about which LUTs should be in the same CLB. $SSHQGL[$SSHQGL[ $+--------------------------------------------------------------------------+ | RASP_SYN: LUT-Based FPGA Technology Mapping Package (Release B 1.0) | | -- Synthesis Core of the UCLA RASP Systems | +--------------------------------------------------------------------------+ | Copyright (C) 1991-1997 the Regents of University of California | +--------------------------------------------------------------------------+ | Authors: Eugene Ding, VLSI CAD Lab, UCLA CS Dept. <eugene@> | | Yean-Yow Hwang, VLSI CAD Lab, UCLA CS Dept.<yeanyow@>| | Chang Wu, VLSI CAD Lab, UCLA CS Dept. <changwu@> | | Songjie Xu, VLSI CAD Lab, UCLA CS Dept. <sxu@> | | Project Director: Prof. Jason Cong, UCLA CS Dept. <cong@> | +--------------------------------------------------------------------------+ | This release includes the following mapping algorithms: | | DAG_Map version 1.0 | | FlowMap version 2.1 | | FlowMap-r version 2.0 | | FlowSYN version 2.0 | | CutMap version 1.2 | | ZMap version 1.0 | | TurboMap version 1.0+--------------------------------------------------------------------------+ -------------------<0> ACKNOWLEDGEMENTÃÃ-------------------The FlowMap and CutMap and TurboMap packages are integrated into the SIS system and uses many of the routines provided by SIS. The SIS system was developed in UC Berkeley Electronic Research Lab.--------------------------------------<1> RELEASE AGREEMENT AND CONTACT INFO--------------------------------------Please refer to "release.statement".-----------<2> CONTENT-----------sis -- binary of SIS compiled with FlowMap andCutMap packages.doc -- this file.release.statement -- to be read first.rasp_syn -- a csh script of FPGA mappingselect -- mapping result selectorThis release contains programs primarily developed by September 1997. More functions will be added to future release when they are stablized. It runs on Sun SPARCstation under SunOS 4.1.3 and Solaris.Some commands are not included in the release due to nondisclosure agreement.RASP_SYN package provides a complete solution to SRAM-based FPGA mapping engine. The entire flow of RASP_SYN is:1. gate decomposition to get K-bounded circuit, where K is thefanin limit of LUTs of the target architecture2. generic LUT mapping3. post-processing mainly for area reduction4. architecture specific mapping.RASP_SYN comes with a user-friendly csh script for the ease of use. However, you can modify the script or write your own based on your specific needs.------------------------<3> TECHNICAL REFERENCES------------------------J. Cong, Y. Ding, "An Optimal Technology Mapping Algorithm for DelayOptimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.J. Cong, Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol 2., No. 2, June 1994,pp. 137-148.J. Cong, Y. Ding, T. Gao, K. Chen, "LUT-Based FPGA Technology Mappingunder Arbitrary Net-Delay Models," Computers & Graphics,Vol.18, No.4, 1994, 507-516.J. Cong, Y. Ding, "Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs," Proc. 1993 IEEE/ACM Int’l Conf. on CAD,Santa Clara, CA, Nov. 1993, pp. 110-114.K.Chen, J.Cong, Y.Ding, A.Kahng, P.Trajmar, "DAG-MAP: Graph-BasedÃÃFPGA Technology Mapping for Delay Optimization," IEEE Design & Testof Computers, Sept. 1992J. Cong, J. Peck, Y. Ding, "RASP: A General Logic Synthesis System forSRAM-based FPGAs," Proc. ACM 4th Int’l Symp. on FPGA, pp. 137-143, 1996J. Cong, Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-BasedFPGA Mapping," Proc. ACM 3rd Int’l Symp. on FPGA, Feb. 1995, pp. 68-74.J. Cong, Y. Hwang, "Structural Gate Decomposition for Depth-OptimalTechnology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rdDesign Automation Conf., pp. 726-729, 1996.J. Cong, C. Wu, "An Improved Algorithm for Performance Optimal TechnologyMapping with Retiming in LUT-Based FPGA Design," Proc. IEEE InternalConference on Computer Design, pp. 572-578, 1996Xilinx, FPGA Data Book, 1994---------<4> USAGE---------4.1 Running with a super scriptSuper Script of UCLA FPGA MappingUsage: rasp_syn circuit -sis path -k k -device xc3k/xc4k -algo algo -relax r -objective area/delay/tradeoff/allRasp_syn is a csh script for an easy usage of UCLA FPGA Mapping algorithms.In default, the input is in EQN format with extension .eqn. The output isan LUT network with/without matching information in EQN format as well.Please keep the program "select" in the current directory.To use other data formats as BLIF or SLIF which are supported by SIS of UCB, please set FMT in rasp_syn script to blif or slif and use .blif or .slifas the name extension of the input file. The output format will be changed automatically, except the CLB matching file format, which will be keptin EQN format. For Xilinx XC3K/XC4K CLBs, the CLB clustering informationwill be presented as:#CLB_number: (lut1, lut2)lut1 = ..lut2 = ..There are two ways to run rasp_syn:1. Running with single given mapping algorithmThe algorithm must be specified with option -algo algorithm. The targetis K-LUT. The output circuit is in circuit.k in EQN format.2. Running with multiple algorithmsRasp_syn can run all the built-in algorithms automatically and returnthe best result (in terms of area or delay) or a set of resultsbased on area-delay tradeoff or all the results for you.To run multiple algorithms, you simply do not specify any algorithm with-algo option.OptionsÃÃ-sis Specify the path of sis. The default is sis and the pathmust be specified in the environment.-k Used only in single algorithm mode. K is the input numberof LUTs. The output is in circuit.k.-device Used only in multi-algorithm mode. This is the default mode. The current supported devices are:xc3k Xilinx XC3000 Familyxc4k Xilinx XC4000 Family-algo Specify the mapping algorithm in single algorithm mode.The current supported algorithms are:flowmap: FlowMapflowmap-r: FlowMap-rflowsyn: FlowSYNcutmap: CutMapzmap: ZMap for delayzma: ZMap for area-relax Used only in single algorithm mode with FlowMap-r.R is the depth relaxation.-objective Used only in multi-algorithm mode. The objective can be:area: Area first. This is the default objective.delay: Depth firsttradeoff: Area-delay tradeoffall: All the results4.2 Running SIS without the super scriptSIS is a complete logic synthesis package. All of the following commands have been built in SIS which can be run directly from SIS.Commands provided by UCLA FPGA Mapping Package--------------------------------------------------------------------1. Gate Decomposition Commands* dmig [ -k <K_value> ] [ -f ]Decompose a simple gate network into a K-bounded network(i.e. each gate has no more than K inputs), orcomplex gates into K-bounded gates with -f option.For obtaining a simple gate network, use sis command"tech_decomp -a 1000 -o 1000."-k specifies max. gate input size K, with a default value 2.-f decompose complex gates in the network* dogma [ -k <K_value> ]Decompose a simple gate network into a 2-bounded networksuch that flowmap, cutmap, or zmap can obtain a best (small) depth.-k specifies the LUT input size K, with a default value 5.--------------------------------------------------------------------2. LUT Mapping Commands* dagmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of small depthÃÃ(might not be optimal).-k specifies the LUT input size K, with a default value 5.* flowmap [ -k <K_value> ] [-r <R_value> ] [ -s <S_value> ]Map a K-bounded network into a K-LUT network of optimal depth,or within the optimal depth plus R.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-r specifies the relaxed depth value R.If -r is not used, every node is at its optimal depth,-r 0 will trade depth on non-critical paths for a smaller area(the LUT network still has an optimal depth),-r R will allow depth to increase by R (then dfmap is called toreduce the area).-s specifies the cone input size S for which resynthesis of conesare performed for a smaller LUT network depth.* dfmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of optimal areaWITHOUT any node duplication.It is used after flowmap -r and mffc_shrink, and is followedby a LUT packing procedure. For example, we use dfmap in"flowmap -k 5 -r 1; mffc_shrink -k 5; dfmap -k 5; greedy_pack -k 5"-k specifies the LUT input size K, with a default value 5.* cutmap [ -k <K_value> ] [-x ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-x specifies depth relaxation on non-critical paths.* zmap [ -k <K_value> ] [-c ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization (cut enumeration approach).Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-c will minimize area only with no bound on depth* turbomap [ -k <K_value> ] [-c <clock_value> ] [ -a <area_reduction> ]Map a K-bounded network into a K-LUT network with the minimum clockperiod. Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K,default value: 5.-c specifies an upper-bound on the clock period,-1: no upper-bound, (default)。