内嵌BRAM设计LIFO堆栈

深圳大学实验报告课程名称：数字系统现场集成技术实验项目名称：内嵌BRAM设计LIFO堆栈学院：信息工程学院专业：集成电路设计与集成系统指导教师：报告人：学号：班级：报告人：学号：班级：实验时间：实验报告提交时间：教务部制图1 VGA接口信号基本时序图图3 VGA(640*480@60Hz)时序图VGA显示的设计模块为：VGA显示模块clkrst_n vs hs r g b说明：设计中FPGA板的VGA接口将R，G，B分别设为定义为2位，3位，3位，例如显示红色RGB可以输出为11000000,绿色输出为00111000，蓝色输出为00000111.表1 25MHz 640*480@60Hz模式下VGA的时序五、ASM图lifo的控制状态图为：图5.1 lifo控制状态图图中的cnt为写进BRAM中的个数，所以减去1就是BRAM中的地址，write 和read的信号是按键的经处理后的脉冲。

RTL图：图5.1.1 顶层模块RTL图1 图5.1.2 顶层模块RTL图2-----------------------------------------------------------------------------2、div_clk模块代码library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity div_clk isgeneric (cnt : integer range 1 to 2**30 := 2**30); --分频系数port(clk : in std_logic;.CLK2X180(),.CLK90(),.CLK180(),.CLK270(),.LOCKED(),.PSDONE(),.STATUS()); endmoduleRTL图为图5.3.1 clkf倍频模块RTL图仿真代码为：module clk300m_tb;// Inputsreg clk;reg rst_p;// Outputswire clk_out;// Instantiate the Unit Under Test (UUT)clkf uut (.clk(clk),.rst_p(rst_p),.clk_out(clk_out));initial begin// Initialize Inputsclk = 0;rst_p = 0;// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #10 clk = ~clk;endmodule结果为：、图5.3.1 clkf倍频模块仿真因为clkfx_divide为1,clkfx_multiply为5，所以是倍频5倍，由图可看出刚好5倍，所以结果是对的。

-----------------------------------------------------------------------------4、sf采样模块此模块是采样滤波，只要是为了消抖。

//singal filtermodule sf #(parameter times = 20'b1111_0100_0010_0100_0000, //1000000width = 20)(clk,rst_n,in,out);input clk;input rst_n;图5.4.1 RTL图仿真代码为：`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company:// Engineer://// Create Date: 17:00:39 04/25/2016// Design Name: sf// Module Name: D:/my class/Digital system integration technology/lab3_lifo/lifo3/sf_tb.v // Project Name: lifo// Target Device:// Tool versions:// Description://// Verilog Test Fixture created by ISE for module: sf//// Dependencies://// Revision:// Revision 0.01 - File Created// Additional Comments://////////////////////////////////////////////////////////////////////////////////module sf_tb;// Inputsbegin#10 in = 1;#10 in = 0;end// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #5 clk = ~clk;endmodule结果为图5.4.2 仿真代码结果前面几段故意仿真不小心抖动一下按键，结果并不会产生信号，长按按键才会出现高电平。

-----------------------------------------------------------------------------5、psp电平转脉冲模块module psp #(parameter width = 2)(clk,rst_n,in,pulse);input clk;input rst_n;input [width-1:0] in;output [width-1:0] pulse;reg [width-1:0] in_r1 = {width{1'b0}};reg [width-1:0] in_r2 = {width{1'b0}};always@(posedge clk or negedge rst_n)if(!rst_n)beginin_r1 <= {width{1'b0}};in_r2 <= {width{1'b0}};endelsebeginin_r1 <= in;in_r2 <= in_r1;endassign pulse = ~in_r2 & in_r1;endmoduleRTL图：图5.6.1 RTL图图5.6.2 RTL展开图仿真代码：module psp_tb;parameter width = 3;// Inputsreg clk;reg rst_n;reg [width-1:0] in;// Outputswire [width-1:0] pulse;// Instantiate the Unit Under Test (UUT)psp #(width)uut (.clk(clk),.rst_n(rst_n),.in(in),.pulse(pulse));initial begin// Initialize Inputsclk = 0;rst_n = 1;in = 0;#1 rst_n = 0;#1 rst_n = 1;repeat(4)begin#40 in = 3'h1;#100 in = 3'h0;#40 in = 3'h2;#100 in = 3'h0;#40 in = 3'h4;#100 in = 3'h0;#40 in = 3'h7;#100 in = 3'h0;end// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #10 clk = ~clk;endmodule结果为：这是两个电平信号转换成相对应的脉冲信号，如结果所示，正确无误。

-----------------------------------------------------------------------------6、spf脉冲时间拉长模块always@(posedge clk or negedge rst_n)if(!rst_n)filter <= {width{1'b0}};elsefilter <= filter_pre;assign filter_pre = in_r3 ? {width{1'b0}} :(filter == times) ? filter :filter + 1'b1;always@(posedge clk or negedge rst_n)if(!rst_n)beginout_r <= 1'b0;endelsebeginout_r <= out_pre;endassign out_pre = (filter == times) ? in_r3 : (out_r | in_r3);assign out = out_r;endmoduleRTL图为：图5.6.1 RTL图仿真代码为：module spf_tb;由图看可达到想要的结果。

-----------------------------------------------------------------------------7、lifo模块此模块是控制RAM的读和写来实现lifo功能的。

module lifo(clk,rst_n,wr,rd,din,full,empty,num,//addr,wrdout, //writing datarddout //read data);input clk;input rst_n;input wr;input rd;input [3:0] din;output [3:0] num;output [3:0] wrdout;output [3:0] rddout;output full;output empty;//output [3:0] addr;wire [3:0] addr;reg [4:0] cnt = 5'h00;wire [4:0] cnt_pre;wire [3:0] ramdout;reg [3:0] rddout_r = 4'h0;wire [3:0] rddout_pre;reg [3:0] wrdout_r = 4'h0;wire [3:0] wrdout_pre;wire we;assign video_de = hs_de & vs_de;//generate point coordinate (x,y)assign video_x = hs_de ? (x_cnt - HSTPW - HSTBP + 1'b1) : {width_x{1'b0}};assign video_y = vs_de ? (y_cnt - VSTPW - VSTBP) : {width_y{1'b0}};//r,g,b控制液晶屏颜色显示assign video_r = video_de ? video_rgb[7:5] : 3'b000;assign video_g = video_de ? video_rgb[4:2] : 3'b000;assign video_b = video_de ? video_rgb[1:0] : 2'b00;endmoduleRTL图：图5.4.1 video_signal_gen 展开图测试代码为module vga256_tb;// Inputsreg clock;reg rst_p;// Outputswire vsync;wire hsync;wire vga_de;wire [1:0] vga_b;wire [2:0] vga_g;wire [2:0] vga_r;// Instantiate the Unit Under Test (UUT)vga256 uut (.clock(clock),.rst_p(rst_p),.vsync(vsync),.hsync(hsync),.vga_de(vga_de),.vga_b(vga_b),.vga_g(vga_g),.vga_r(vga_r));initial begin// Initialize Inputsclock = 0;rst_p = 0;//rst_n = 1;#1 rst_p = 1;#1 rst_p = 0;// Wait 100 ns for global reset to finish#100;// Add stimulus hereendalways #5 clock = ~ clock;endmodule测试结果：图5.4.2 测试结果1图5.4.3 测试结果2之前本人有根据上面的时间计算过，确实是一个hs周期里有800个时钟，一个vs周期里有525个时钟，所以大胆猜测是对的，烧到板子上果然是对的。