1V-Overview of Semiconductor
semiconductormanufacturingtechnology

Can do : oxidation, diffusion, deposition, anneals, and alloy
Pressure controller
Exhaust
Semiconductor Manufacturing Technology
Figure 9.3
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by Michael Quirk and Julian Serda
Model of Typical Wafer Flow in a Sub-Micron CMOS IC Fab
Wafer Start Unpatterned
Wafer
Completed Wafer
Wafer Fabrication (front-end)
Thin Films
Polish
Diffusion
2. Give an overview of the six major process areas and the sort/test area in the wafer fab.
3. For each of the 14 CMOS manufacturing steps, describe its primary purpose.
p-well
1
p- Epitaxial layer
p+ Silicon substrate
Semiconductor Manufacturing Technology
Photolithography Bay in a Sub-micron Wafer Fab
Yellow fluorescent: do not affect photoresist
Semiconductor Manufacturing Technology
三星Exynos 4 Quad (Exynos 4412) RISC微处理器用户手册

Samsung Exynos 4 Quad(Exynos 4412)RISC MicroprocessorRevision 1.00October 2012 U s e r's M a n u a l2012 Samsung Electronics Co., Ltd. All rights reserved.Important NoticeSamsung Electronics Co. Ltd. (“Samsung”) reserves the right to make changes to the information in this publication at any time without prior notice. All information provided is for reference purpose only. Samsung assumes no responsibility for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.This publication on its own does not convey any license, either express or implied, relating to any Samsung and/or third-party products, under the intellectual property rights of Samsung and/or any third parties.Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.Customers are responsible for their own products and applications. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.Samsung products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur. Customers acknowledge and agree that they are solely responsible to meet all other legal and regulatory requirements regarding their applications using Samsung products notwithstanding any information provided in this publication. Customer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim (including but not limited to personal injury or death) thatmay be associated with such unintended, unauthorizedand/or illegal use.WARNING No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung. This publication is intended for use by designated recipients only. This publication contains confidential information (including trade secrets) of Samsung protectedby Competition Law, Trade Secrets Protection Act and other related laws, and therefore may not be, in part or in whole, directly or indirectly publicized, distributed, photocopied or used (including in a posting on the Internet where unspecified access is possible) by any unauthorized third party. Samsung reserves its right to take any and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung’s trade secrets and/or confidential information.警告本文件仅向经韩国三星电子株式会社授权的人员提供,其内容含有商业秘密保护相关法规规定并受其保护的三星电子株式会社商业秘密,任何直接或间接非法向第三人披露、传播、复制或允许第三人使用该文件全部或部分内容的行为(包括在互联网等公开媒介刊登该商业秘密而可能导致不特定第三人获取相关信息的行为)皆为法律严格禁止。
半导体二极管(中文+英文)

半导体二极管半导体二极管是含有一个PN结的二端器件。
它是最简单的半导体器件。
P型材料一端称为正极,而N型材料一端称为负极。
二极管是只允许电流朝一个方向流动的半导体器件。
它能被用来把交流电转换成直流电。
二极管的两个引线被分为阳极和阴极。
当二极管的正极电位高于负极电位(其差值大于开启电压,对锗管近似为0.3V,对硅管近似为0.7V)时称二极管是正向偏置,这时二极管的内阻是很小的,有一个较大的电流流过二极管,流过电流的大小取决于外部电路的电阻。
当二极管的正极电压高于负极电位时称二极管反向偏置,这时二极管的内部电阻非常高,所以一个理想的二极管可以阻挡反向的电流而让正向的电流通过。
一个二极管的实际特性曲线并不是十分理想的,如图所示。
当理想二极管反向偏置时,电流不能通过,而实际二极管却有约10μA的电流通过(虽然很小,但仍不够理想)。
如果加上足够大的反向电压,PN结就会被击穿,让电流反向通过。
一般要选择二极管的反向击穿电压远大于电路中可能出现的电压,二极管才不会击穿。
齐纳二极管(稳压管)稳压管是一种特殊的二极管,在正偏的条件下,它与一般的二极管有相同的特性(可以流过一个大电流)。
但是,在反向偏置时,在外加电压低于稳压电压(UZ)时它不导通,在外加电压等于稳压电压(UZ)时稳压管反向导通,同时维持稳压管两端的电压为稳压值(如图)。
流过稳压管电流的大小由两个因子决定,一个为串联的(限流)电阻(RS),另一个为并联的负载电阻(RL)。
电阻RS由公式RS=URs/IZ确定,其中URs=Usource-UZ,在没有负载时,一个特定大小的电流(IZ=IRs)流过稳压二极管和RS,电压降URs加UZ等Usource,Usource至少要比UZ高1V。
当一个负载并连到稳压二极管,流过二极管的电流由于负载的分流而减小,所以通过RS的电流保持为常数(IZ=IRs-IRL)。
稳压管通过改变流过它的电流来维持稳压管两端的电压稳定。
Semiconductor Introduction(半导体简介)

(小型化和轻便携带式)
o
Launched a completely new industry
(新产业完整地投放到市场)
o Invented by Jack Kilby, Texas Instruments, 1958
For internal use only
Copyright © Infineon Technologies 2008. All rights reserved.
Page 8
Semiconductor environment – an industry comparison (not really serious … but easy to memorize) (半导体行业的外界环境 – 行业的对比关系)
2012-12-16
For internal use only
Copyright © Infineon Technologies 2008. All rights reserved.
Page 2
什么是半导体呢?
顾名思义:导电性能介于导体与绝缘体(insulator)之间的材料,叫做半导体(semiconductor). 物质存在的形式多种多样,固体、液体、气体、等离子体等等。我们通常把导电性和导电导热性 差或不好的材料,如金刚石、人工晶体、琥珀、陶瓷等等,称为绝缘体。而把导电、导热都比较 好的金属如金、银、铜、铁、锡、铝等称为导体。可以简单的把介于导体和绝缘体之间的材料称 为半导体。与导体和绝缘体相比,半导体材料的发现是最晚的,直到20世纪30年代,当材料的提 纯技术改进以后,半导体的存在才真正被学术界认可。 1833年,英国巴拉迪最先发现硫化银的电阻随着温度的变化情况不同于一般金属,一般情况下, 金属的电阻随温度升高而增加,但巴拉迪发现硫化银材料的电阻是随着温度的上升而降低。这 是半导体现象的首次发现。 1839年法国的贝克莱尔发现半导体和电解质接触形成的结,在光照下会产生一个电压,这就是后 来人们熟知的光生伏特效应,这是被发现的半导体的第二个特征。
半导体制造技术

Semiconductor Manufacturing Technology半导体制造技术Instructor’s ManualMichael QuirkJulian SerdaCopyright Prentice HallTable of Contents目录OverviewI. Chapter1. Semiconductor industry overview2. Semiconductor materials3. Device technologies—IC families4. Silicon and wafer preparation5. Chemicals in the industry6. Contamination control7. Process metrology8. Process gas controls9. IC fabrication overview10. Oxidation11. Deposition12. Metallization13. Photoresist14. Exposure15. Develop16. Etch17. Ion implant18. Polish19. Test20. Assembly and packagingII. Answers to End-of-Chapter Review QuestionsIII. Test Bank (supplied on diskette)IV. Chapter illustrations, tables, bulleted lists and major topics (supplied on CD-ROM)Notes to Instructors:1)The chapter overview provides a concise summary of the main topics in each chapter.2)The correct answer for each test bank question is highlighted in bold. Test bankquestions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.2Chapter 1Introduction to the Semiconductor Industry Die:管芯 defective:有缺陷的Development of an Industry•The roots of the electronic industry are based on the vacuum tube and early use of silicon for signal transmission prior to World War II. The first electronic computer, the ENIAC, wasdeveloped at the University of Pennsylvania during World War II.•William Shockley, John Bardeen and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry grew rapidly in the 1950s to commercialize the new transistor technology, with many early pioneers working inSilicon Valley in Northern California.Circuit Integration•The first integrated circuit, or IC, was independently co-invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor in 1959. An IC integrates multiple electronic components on one substrate of silicon.•Circuit integration eras are: small scale integration (SSI) with 2 - 50 components, medium scale integration (MSI) with 50 – 5k components, large scale integration (LSI) with 5k to 100kcomponents, very large scale integration (VLSI) with 100k to 1M components, and ultra large scale integration (ULSI) with > 1M components.1IC Fabrication•Chips (or die) are fabricated on a thin slice of silicon, known as a wafer (or substrate). Wafers are fabricated in a facility known as a wafer fab, or simply fab.•The five stages of IC fabrication are:Wafer preparation: silicon is purified and prepared into wafers.Wafer fabrication: microchips are fabricated in a wafer fab by either a merchant chip supplier, captive chip producer, fabless company or foundry.Wafer test: Each individual die is probed and electrically tested to sort for good or bad chips.Assembly and packaging: Each individual die is assembled into its electronic package.Final test: Each packaged IC undergoes final electrical test.•Key semiconductor trends are:Increase in chip performance through reduced critical dimensions (CD), more components per chip (Moore’s law, which predicts the doubling of components every 18-24 months) andreduced power consumption.Increase in chip reliability during usage.Reduction in chip price, with an estimated price reduction of 100 million times for the 50 years prior to 1996.The Electronic Era•The 1950s saw the development of many different types of transistor technology, and lead to the development of the silicon age.•The 1960s were an era of process development to begin the integration of ICs, with many new chip-manufacturing companies.•The 1970s were the era of medium-scale integration and saw increased competition in the industry, the development of the microprocessor and the development of equipment technology. •The 1980s introduced automation into the wafer fab and improvements in manufacturing efficiency and product quality.•The 1990s were the ULSI integration era with the volume production of a wide range of ICs with sub-micron geometries.Career paths•There are a wide range of career paths in semiconductor manufacturing, including technician, engineer and management.2Chapter 2 Characteristics of Semiconductor MaterialsAtomic Structure•The atomic model has three types of particles: neutral neutrons(不带电的中子), positively charged protons(带正电的质子)in the nucleus and negatively charged electrons(带负电的核外电子) that orbit the nucleus. Outermost electrons are in the valence shell, and influence the chemical and physical properties of the atom. Ions form when an atom gains or loses one or more electrons.The Periodic Table•The periodic table lists all known elements. The group number of the periodic table represents the number of valence shell electrons of the element. We are primarily concerned with group numbers IA through VIIIA.•Ionic bonds are formed when valence shell electrons are transferred from the atoms of one element to another. Unstable atoms (e.g., group VIIIA atoms because they lack one electron) easily form ionic bonds.•Covalent bonds have atoms of different elements that share valence shell electrons.3Classifying Materials•There are three difference classes of materials:ConductorsInsulatorsSemiconductors•Conductor materials have low resistance to current flow, such as copper. Insulators have high resistance to current flow. Capacitance is the storage of electrical charge on two conductive plates separated by a dielectric material. The quality of the insulation material between the plates is the dielectric constant. Semiconductor materials can function as either a conductor or insulator.Silicon•Silicon is an elemental semiconductor material because of four valence shell electrons. It occurs in nature as silica and is refined and purified to make wafers.•Pure silicon is intrinsic silicon. The silicon atoms bond together in covalent bonds, which defines many of silicon’s properties. Silicon atoms bond together in set, repeatable patterns, referred to asa crystal.•Germanium was the first semiconductor material used to make chips, but it was soon replaced by silicon. The reasons for this change are:Abundance of siliconHigher melting temperature for wider processing rangeWide temperature range during semiconductor usageNatural growth of silicon dioxide•Silicon dioxide (SiO2) is a high quality, stable electrical insulator material that also serves as a good chemical barrier to protect silicon from external contaminants. The ability to grow stable, thin SiO2 is fundamental to the fabrication of Metal-Oxide-Semiconductor (MOS) devices. •Doping increases silicon conductivity by adding small amounts of other elements. Common dopant elements are from trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic and antimony).•It is the junction between the n-type and p-type doped regions (referred to as a pn junction) that permit silicon to function as a semiconductor.4Alternative Semiconductor Materials•The alternative semiconductor materials are primarily the compound semiconductors. They are formed from Group IIIA and Group VA (referred to as III-V compounds). An example is gallium arsenide (GaAs).•Some alternative semiconductors come from Group IIA and VIA, referred to as II-VI compounds. •GaAs is the most common III-V compound semiconductor material. GaAs ICs have greater electron mobility, and therefore are faster than ICs made with silicon. GaAs ICs also have higher radiation hardness than silicon, which is better for space and military applications. The primary disadvantage of GaAs is the lack of a natural oxide.5Chapter 3Device TechnologiesCircuit Types•There are two basic types of circuits: analog and digital. Analog circuits have electrical data that varies continuously over a range of voltage, current and power values. Digital circuits have operating signals that vary about two distinct voltage levels – a high and a low.Passive Component Structures•Passive components such as resistors and capacitors conduct electrical current regardless of how the component is connected. IC resistors are a passive component. They can have unwanted resistance known as parasitic resistance. IC capacitor structures can also have unintentional capacitanceActive Component Structures•Active components, such as diodes and transistors can be used to control the direction of current flow. PN junction diodes are formed when there is a region of n-type semiconductor adjacent to a region of p-type semiconductor. A difference in charge at the pn junction creates a depletion region that results in a barrier voltage that must be overcome before a diode can be operated. A bias voltage can be configured to have a reverse bias, with little or no conduction through the diode, or with a forward bias, which permits current flow.•The bipolar junction transistor (BJT) has three electrodes and two pn junctions. A BJT is configured as an npn or pnp transistor and biased for conduction mode. It is a current-amplifying device.6• A schottky diode is formed when metal is brought in contact with a lightly doped n-type semiconductor material. This diode is used in faster and more power efficient BJT circuits.•The field-effect transistor (FET), a voltage-amplifying device, is more compact and power efficient than BJT devices. A thin gate oxide located between the other two electrodes of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs, nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.•For many years, nMOS transistors have been the choice of most IC manufacturers. CMOS, with both nMOS and pMOS transistors in the same IC, has been the most popular device technology since the early 1980s.•BiCMOS technology makes use of the best features of both CMOS and bipolar technology in the same IC device.•Another way to categorize FETs is in terms of enhancement mode and depletion mode. The major different is in the way the channels are doped: enhancement-mode channels are doped opposite in polarity to the source and drain regions, whereas depletion mode channels are doped the same as their respective source and drain regions.Latchup in CMOS Devices•Parasitic transistors can create a latchup condition(???????) in CMOS ICs that causes transistors to unintentionally(无心的) turn on. To control latchup, an epitaxial layer is grown on the wafer surface and an isolation barrier(隔离阻障)is placed between the transistors. An isolation layer can also be buried deep below the transistors.Integrated Circuit Productsz There are a wide range of semiconductor ICs found in electrical and electronic products. This includes the linear IC family, which operates primarily with anal3og circuit applications, and the digital IC family, which includes devices that operate with binary bits of data signals.7Chapter 4Silicon and Wafer Preparation8z Semiconductor-Grade Silicon•The highly refined silicon used for wafer fabrication is termed semiconductor-grade silicon (SGS), and sometimes referred to as electronic-grade silicon. The ultra-high purity of semiconductor-grade silicon is obtained from a multi-step process referred to as the Siemens process.Crystal Structure• A crystal is a solid material with an ordered, 3-dimensional pattern over a long range. This is different from an amorphous material that lacks a repetitive structure.•The unit cell is the most fundamental entity for the long-range order found in crystals. The silicon unit cell is a face-centered cubic diamond structure. Unit cells can be organized in a non-regular arrangement, known as a polycrystal. A monocrystal are neatly arranged unit cells.Crystal Orientation•The orientation of unit cells in a crystal is described by a set of numbers known as Miller indices.The most common crystal planes on a wafer are (100), (110), and (111). Wafers with a (100) crystal plane orientation are most common for MOS devices, whereas (111) is most common for bipolar devices.Monocrystal Silicon Growth•Silicon monocrystal ingots are grown with the Czochralski (CZ) method to achieve the correct crystal orientation and doping. A CZ crystal puller is used to grow the silicon ingots. Chunks of silicon are heated in a crucible in the furnace of the puller, while a perfect silicon crystal seed is used to start the new crystal structure.• A pull process serves to precisely replicate the seed structure. The main parameters during the ingot growth are pull rate and crystal rotation. More homogeneous crystals are achieved with a magnetic field around the silicon melt, known as magnetic CZ.•Dopant material is added to the melt to dope the silicon ingot to the desired electrical resistivity.Impurities are controlled during ingot growth. A float-zone crystal growth method is used toachieve high-purity silicon with lower oxygen content.•Large-diameter ingots are grown today, with a transition underway to produce 300-mm ingot diameters. There are cost benefits for larger diameter wafers, including more die produced on a single wafer.Crystal Defects in Silicon•Crystal defects are interruptions in the repetitive nature of the unit cell. Defect density is the number of defects per square centimeter of wafer surface.•Three general types of crystal defects are: 1) point defects, 2) dislocations, and 3) gross defects.Point defects are vacancies (or voids), interstitial (an atom located in a void) and Frenkel defects, where an atom leaves its lattice site and positions itself in a void. A form of dislocation is astacking fault, which is due to layer stacking errors. Oxygen-induced stacking faults are induced following thermal oxidation. Gross defects are related to the crystal structure (often occurring during crystal growth).Wafer Preparation•The cylindrical, single-crystal ingot undergoes a series of process steps to create wafers, including machining operations, chemical operations, surface polishing and quality checks.•The first wafer preparation steps are the shaping operations: end removal, diameter grinding, and wafer flat or notch. Once these are complete, the ingot undergoes wafer slicing, followed by wafer lapping to remove mechanical damage and an edge contour. Wafer etching is done to chemically remove damage and contamination, followed by polishing. The final steps are cleaning, wafer evaluation and packaging.Quality Measures•Wafer suppliers must produce wafers to stringent quality requirements, including: Physical dimensions: actual dimensions of the wafer (e.g., thickness, etc.).Flatness: linear thickness variation across the wafer.Microroughness: peaks and valleys found on the wafer surface.Oxygen content: excessive oxygen can affect mechanical and electrical properties.Crystal defects: must be minimized for optimum wafer quality.Particles: controlled to minimize yield loss during wafer fabrication.Bulk resistivity(电阻系数): uniform resistivity from doping during crystal growth is critical. Epitaxial Layer•An epitaxial layer (or epi layer) is grown on the wafer surface to achieve the same single crystal structure of the wafer with control over doping type of the epi layer. Epitaxy minimizes latch-up problems as device geometries continue to shrink.Chapter 5Chemicals in Semiconductor FabricationEquipment Service Chase Production BayChemical Supply Room Chemical Distribution Center Holding tank Chemical drumsProcess equipmentControl unit Pump Filter Raised and perforated floorElectronic control cablesSupply air ductDual-wall piping for leak confinement PumpFilterChemical control and leak detection Valve boxes for leak containment Exhaust air ductStates of Matter• Matter in the universe exists in 3 basic states (宇宙万物存在着三种基本形态): solid, liquid andgas. A fourth state is plasma.Properties of Materials• Material properties are the physical and chemical characteristics that describe its unique identity.• Different properties for chemicals in semiconductor manufacturing are: temperature, pressure andvacuum, condensation, vapor pressure, sublimation and deposition, density, surface tension, thermal expansion and stress.Temperature is a measure of how hot or cold a substance is relative to another substance. Pressure is the force exerted per unit area. Vacuum is the removal of gas molecules.Condensation is the process of changing a gas into a liquid. Vaporization is changing a liquidinto a gas.Vapor pressure is the pressure exerted by a vapor in a closed container at equilibrium.Sublimation is the process of changing a solid directly into a gas. Deposition is changing a gas into a solid.Density is the mass of a substance divided by its volume.Surface tension of a liquid is the energy required to increase the surface area of contact.Thermal expansion is the increase in an object’s dimension due to heating.Stress occurs when an object is exposed to a force.Process Chemicals•Semiconductor manufacturing requires extensive chemicals.• A chemical solution is a chemical mixture. The solvent is the component of the solution present in larger amount. The dissolved substances are the solutes.•Acids are solutions that contain hydrogen and dissociate in water to yield hydronium ions. A base is a substance that contains the OH chemical group and dissociates in water to yield the hydroxide ion, OH-.•The pH scale is used to assess the strength of a solution as an acid or base. The pH scale varies from 0 to 14, with 7 being the neutral point. Acids have pH below 7 and bases have pH values above 7.• A solvent is a substance capable of dissolving another substance to form a solution.• A bulk chemical distribution (BCD) system is often used to deliver liquid chemicals to the process tools. Some chemicals are not suitable for BCD and instead use point-of-use (POU) delivery, which means they are stored and used at the process station.•Gases are generally categorized as bulk gases or specialty gases. Bulk gases are the relatively simple gases to manufacture and are traditionally oxygen, nitrogen, hydrogen, helium and argon.The specialty gases, or process gases, are other important gases used in a wafer fab, and usually supplied in low volume.•Specialty gases are usually transported to the fab in metal cylinders.•The local gas distribution system requires a gas purge to flush out undesirable residual gas. Gas delivery systems have special piping and connections systems. A gas stick controls the incoming gas at the process tool.•Specialty gases may be classified as hydrides, fluorinated compounds or acid gases.Chapter 6Contamination Control in Wafer FabsIntroduction•Modern semiconductor manufacturing is performed in a cleanroom, isolated from the outside environment and contaminants.Types of contamination•Cleanroom contamination has five categories: particles, metallic impurities, organic contamination, native oxides and electrostatic discharge. Killer defects are those causes of failure where the chip fails during electrical test.Particles: objects that adhere to a wafer surface and cause yield loss. A particle is a killer defect if it is greater than one-half the minimum device feature size.Metallic impurities: the alkali metals found in common chemicals. Metallic ions are highly mobile and referred to as mobile ionic contaminants (MICs).Organic contamination: contains carbon, such as lubricants and bacteria.Native oxides: thin layer of oxide growth on the wafer surface due to exposure to air.Electrostatic discharge (ESD): uncontrolled transfer of static charge that can damage the microchip.Sources and Control of Contamination•The sources of contamination in a wafer fab are: air, humans, facility, water, process chemicals, process gases and production equipment.Air: class number designates the air quality inside a cleanroom by defining the particle size and density.Humans: a human is a particle generator. Humans wear a cleanroom garment and follow cleanroom protocol to minimize contamination.Facility: the layout is generally done as a ballroom (open space) or bay and chase design.Laminar airflow with air filtering is used to minimize particles. Electrostatic discharge iscontrolled by static-dissipative materials, grounding and air ionization.Ultrapure deiniozed (DI) water: Unacceptable contaminants are removed from DI water through filtration to maintain a resistivity of 18 megohm-cm. The zeta potential represents a charge on fine particles in water, which are trapped by a special filter. UV lamps are used for bacterial sterilization.Process chemicals: filtered to be free of contamination, either by particle filtration, microfiltration (membrane filter), ultrafiltration and reverse osmosis (or hyperfiltration).Process gases: filtered to achieve ultraclean gas.Production equipment: a significant source of particles in a fab.Workstation design: a common layout is bulkhead equipment, where the major equipment is located behind the production bay in the service chase. Wafer handling is done with robotic wafer handlers. A minienvironment is a localized environment where wafers are transferred on a pod and isolated from contamination.Wafer Wet Cleaning•The predominant wafer surface cleaning process is with wet chemistry. The industry standard wet-clean process is the RCA clean, consisting of standard clean 1 (SC-1) and standard clean 2 (SC-2).•SC-1 is a mixture of ammonium hydroxide, hydrogen peroxide and DI water and capable of removing particles and organic materials. For particles, removal is primarily through oxidation of the particle or electric repulsion.•SC-2 is a mixture of hydrochloric acid, hydrogen peroxide and DI water and used to remove metals from the wafer surface.•RCA clean has been modified with diluted cleaning chemistries. The piranha cleaning mixture combines sulfuric acid and hydrogen peroxide to remove organic and metallic impurities. Many cleaning steps include an HF last step to remove native oxide.•Megasonics(兆声清洗) is widely used for wet cleaning. It has ultrasonic energy with frequencies near 1 MHz. Spray cleaning will spray wet-cleaning chemicals onto the wafer. Scrubbing is an effective method for removing particles from the wafer surface.•Wafer rinse is done with overflow rinse, dump rinse and spray rinse. Wafer drying is done with spin dryer or IPA(异丙醇) vapor dry (isopropyl alcohol).•Some alternatives to RCA clean are dry cleaning, such as with plasma-based cleaning, ozone and cryogenic aerosol cleaning.Chapter 7Metrology and Defect InspectionIC Metrology•In a wafer fab, metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer.•In-process data has traditionally been collected on monitor wafers. Measurement equipment is either stand-alone or integrated.•Yield is the percent of good parts produced out of the total group of parts started. It is an indicator of the health of the fabrication process.Quality Measures•Semiconductor quality measures define the requirements for specific aspects of wafer fabrication to ensure acceptable device performance.•Film thickness is generally divided into the measurement of opaque film or transparent film. Sheet resistance measured with a four-point probe is a common method of measuring opaque films (e.g., metal film). A contour map shows sheet resistance deviations across the wafer surface.•Ellipsometry is a nondestructive, noncontact measurement technique for transparent films. It works based on linearly polarized light that reflects off the sample and is elliptically polarized.•Reflectometry is used to measure a film thickness based on how light reflects off the top and bottom surface of the film layer. X-ray and photoacoustic technology are also used to measure film thickness.•Film stress is measured by analyzing changes in the radius of curvature of the wafer. Variations in the refractive index are used to highlight contamination in the film.•Dopant concentration is traditionally measured with a four-point probe. The latest technology is the thermal-wave system, which measures the lattice damage in the implanted wafer after ion implantation. Another method for measuring dopant concentration is spreading resistance probe. •Brightfield detection is the traditional light source for microscope equipment. An optical microscope uses light reflection to detect surface defects. Darkfield detection examines light scattered off defects on the wafer surface. Light scattering uses darkfield detection to detectsurface particles by illuminating the surface with laser light and then using optical imaging.•Critical dimensions (CDs) are measured to achieve precise control over feature size dimensions.The scanning electron microscope is often used to measure CDs.•Conformal step coverage is measured with a surface profiler that has a stylus tip.•Overlay registration measures the ability to accurately print photoresist patterns over a previously etched pattern.•Capacitance-voltage (C-V) test is used to verify acceptable charge conditions and cleanliness at the gate structure in a MOS device.Analytical Equipment•The secondary-ion mass spectrometry (SIMS) is a method of eroding a wafer surface with accelerated ions in a magnetic field to analyze the surface material composition.•The atomic force microscope (AFM) is a surface profiler that scans a small, counterbalanced tip probe over the wafer to create a 3-D surface map.•Auger electron spectroscopy (AES) measures composition on the wafer surface by measuring the energy of the auger electrons. It identifies elements to a depth of about 2 nm. Another instrument used to identify surface chemical species is X-ray photoelectron spectroscopy (XPS).•Transmission electron microscopy (TEM) uses a beam of electrons that is transmitted through a thin slice of the wafer. It is capable of quantifying very small features on a wafer, such as silicon crystal point defects.•Energy-dispersive spectrometer (EDX) is a widely used X-ray detection method for identifying elements. It is often used in conjunction with the SEM.• A focused ion beam (FIB) system is a destructive technique that focuses a beam of ions on the wafer to carve a thin cross section from any wafer area. This permits analysis of the wafermaterial.Chapter 8Gas Control in Process ChambersEtch process chambers••The process chamber is a controlled vacuum environment where intended chemical reactions take place under controlled conditions. Process chambers are often configured as a cluster tool. Vacuum•Vacuum ranges are low (rough) vacuum, medium vacuum, high vacuum and ultrahigh vacuum (UHV). When pressure is lowered in a vacuum, the mean free path(平均自由行程) increases, which is important for how gases flow through the system and for creating a plasma.Vacuum Pumps•Roughing pumps are used to achieve a low to medium vacuum and to exhaust a high vacuum pump. High vacuum pumps achieve a high to ultrahigh vacuum.•Roughing pumps are dry mechanical pumps or a blower pump (also referred to as a booster). Two common high vacuum pumps are a turbomolecular (turbo) pump and cryopump. The turbo pump is a reliable, clean pump that works on the principle of mechanical compression. The cryopump isa capture pump that removes gases from the process chamber by freezing them.。
半导体词汇(英汉对照)

半导体词汇(英汉对照)1. 半导体:semiconductor2. 晶体管:transistor3. 二极管:diode4. 集成电路:integrated circuit5. 电容:capacitor8. 金属氧化物场效应管:Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)9. 数字信号处理器:Digital Signal Processor (DSP)10. 有机发光二极管:Organic Light-Emitting Diode (OLED)11. 光纤放大器:Optical Fiber Amplifier (OFA)12. 直流-直流变换器:DC-DC Converter13. 脉冲编码调制:Pulse Code Modulation (PCM)14. 光耦合器:Optocoupler15. 调制解调器:Modem16. 电池管理系统:Battery Management System (BMS)17. 片上系统:System-on-a-Chip (SoC)18. 功率电子器件:Power Electronics Device20. 纳米技术:Nanotechnology21. 生物芯片:Biochip23. 激光器:Laser24. 双极型发射极晶体管:Bipolar Junction Transistor (BJT)28. 传感器:Sensor29. 能量收集器:Energy Harvester30. 固态驱动器:Solid State Drive (SSD)31. 磁性存储设备:Magnetic Storage Device32. 屏幕显示器:Display33. 快速门:Fast Gate35. 超高速芯片:Ultra-High-Speed Chip38. 量子计算机:Quantum Computer40. 机器人学:Robotics41. 表面声波器件:Surface Acoustic Wave (SAW) Device45. 长寿命电池:Long-Life Battery46. 红外光电探测器:Infrared Photodetector47. 树莓派:Raspberry Pi48. 可充电电池:Rechargeable Battery49. 无线充电器:Wireless Charger51. 控制电路:Control Circuit53. 逆变器:Inverter55. 拓扑优化器:Topology Optimizer57. 智能家居:Smart Home58. 传输线理论:Transmission Line Theory60. 片上调制器:On-Chip Modulator61. 内存芯片:Memory Chip63. 线性电源:Linear Power Supply64. 电机驱动器:Motor Driver66. 相变存储器:Phase-Change Memory (PCM)68. 氮化镓:Gallium Nitride (GaN)69. 自动驾驶:Autonomous Driving72. 机器学习:Machine Learning77. 差分信号:Differential Signal78. 相位锁定环:Phase Locked Loop (PLL)80. 峰值检测器:Peak Detector84. 相移器:Phase Shifter88. 滤波器:Filter91. 直流伏安表:Digital Multimeter (DMM)92. 频率计:Frequency Counter93. 降噪耳机:Noise-Canceling Headphones94. 耳返系统:In-Ear Monitoring (IEM) System95. 电学模型:Electrical Model97. 声音芯片:Audio Chip98. 跟踪器:Tracker。
半导体专业英语词汇

半导体专业词汇1. acceptance testing (WA T: wafer acceptance testing)2. acceptor: 受主,如B,掺入Si中需要接受电子3. ACCESS:一个EDA(Engineering Data Analysis)系统4. Acid:酸5. Active device:有源器件,如MOS FET(非线性,可以对信号放大)6. Align mark(key):对位标记7. Alloy:合金8. Aluminum:铝9. Ammonia:氨水10. Ammonium fluoride:NH4F11. Ammonium hydroxide:NH4OH12. Amorphous silicon:α-Si,非晶硅(不是多晶硅)13. Analog:模拟的14. Angstrom:A(1E-10m)埃15. Anisotropic:各向异性(如POL Y ETCH)16. AQL(Acceptance Quality Level):接受质量标准,在一定采样下,可以95%置信度通过质量标准(不同于可靠性,可靠性要求一定时间后的失效率)17. ARC(Antireflective coating):抗反射层(用于METAL等层的光刻)18. Antimony(Sb)锑19. Argon(Ar)氩20. Arsenic(As)砷21. Arsenic trioxide(As2O3)三氧化二砷22. Arsine(AsH3)23. Asher:去胶机24. Aspect ration:形貌比(ETCH中的深度、宽度比)25. Autodoping:自搀杂(外延时SUB的浓度高,导致有杂质蒸发到环境中后,又回掺到外延层)26. Back end:后段(CONTACT以后、PCM测试前)27. Baseline:标准流程28. Benchmark:基准29. Bipolar:双极30. Boat:扩散用(石英)舟31. CD:(Critical Dimension)临界(关键)尺寸。
半导体中英对照

倒序浏览|•Acceptor - An element, such as boron, indium, and gallium used to create a free hole in a semiconductor. The acceptor atoms are required to have one less valence electron than the semiconductor.•受主- 一种用来在半导体中形成空穴的元素,比如硼、铟和镓。
受主原子必须比半导体元素少一价电子•Alignment Precision - Displacement of patterns that occurs during the photolithography process. . u! F. W' }! b# j4 q•套准精度- 在光刻工艺中转移图形的精度。
2 v I; S4 U, T* r' d9 H3 b! c•Anisotropic - A process of etching that has very little or no undercutting , i( N: Z7 u; {3 z •各向异性- 在蚀刻过程中,只做少量或不做侧向凹刻。
: `3 v& P1 s1 }3 z. `; ?•Area Contamination - Any foreign particles or material that are found on the surface of a wafer. This is viewed as discolored or smudged, and it is the result of stains, fingerprints, water spots, etc. + {7 c* p' x H3 B0 m; r•沾污区域- 任何在晶圆片表面的外来粒子或物质。
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Semiconductor Elements
Period 2 3 4 5 6
Mg
Magnesium
II
III
B
Boron
IV
C
Carbon
V
N
Nitrogen
VI
Al
Aluminum
Si
Silicon
P
Phosphorus
S
Sulfur
Zn
Zinc
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n-type Si with donor (arsenic) The arsenic atom forms covalent bonds with its four neighboring silicon atoms, and the fifth electron becomes a conduction electron, thereby giving rise to a positively charged arsenic atom. The silicon crystal becomes ntype and arsenic is called a donor. Boron has only three outer shell electrons and is an acceptor in silicon. p-type Si with acceptor (boron)
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• The thermal motion of an individual electron can be visualized as a succession of random scattering from collisions with lattice atoms, impurity atoms, and other scattering centers • The average distance between collisions is called the mean free path, and the average time between collisions is termed the mean free time, τc
1 1+ e
( E − E F ) / kT
EF is the Fermi level, the energy at which the probability of occupation by an electron is exactly one-half. At room temperature, the intrinsic Fermi level lies very close to the middle of the bandgap.
Ga
Gallium
Ge
Germanium
As
Arsenic
Se
Selenium
Cd
Cadmium
In
Indium
Sn
Tin
Sb
Antimony
Te
Tellurium
Hg
Mercury
Pb
Lead
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Element and Compound Semiconductors
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Bohr Hydrogen Model
− mo q 4 −13.6 eV EH = 2 2 2 = 2 n 8ε o h n
mo denotes the free electron mass q denotes the electronic charge εo denotes the free space permittivity h denotes the Plank constant n denotes the principal quantum number Therefore, for n = 1, that is, ground state, EH = -13.6 eV For n = 2, the first excited state, EH = -3.4 eV
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Impurities such as arsenic and boron have energy levels very close to the conduction band and valence band, respectively
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n = NCexp{-(EC-EF)/kT} p = NVexp{-(EF-EV)/kT} where n is the electron density and p is the hole density
np = ni2 = NCNVexp{(EV-EC)/kT} = NCNVexp{-Eg/kT}
Elements
Si Ge
Compounds Compounds Compounds Compounds IV-IV III-V II-VI IV-VI
SiC AlAs AlSb BN GaAs GaP GaSb InAs InP InSb CdS CdSe CdTe ZnS ZnSe ZnTe PbS PbTe
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Insulator
Semiconductor
Conductor
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Indirect Bandgap Inefficient photon emission, requiring change in crystal momentum
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The effective density of states in the conduction band NC is equal to 2[2πmnkT/h2]3/2. Similarly, the effective density of states in the valence band NV is 2[2πmpkT/h2]3/2. At room temperature, NC for silicon is 2.8 x 1019 atoms/cm3. For an intrinsic semiconductor, the number of electrons per unit volume in the conduction band is equal to the number of holes per unit volume in the valence band. That is, n = p = ni where ni is the intrinsic carrier density.
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Eg of silicon: 1.12 eV at room temperature 1.17 eV at zero Kelvin
Formation of energy bands as a diamond lattice crystal by bringing together isolated silicon atoms
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Carrier Mobility
• Using the theorem of equipartition of energy, mnvth2/2 = 3kT/2, where mn is the electron effective mass and vth is the average thermal velocity • Electrons in the semiconductor therefore move rapidly in all directions
ni = ( N C N V )
1/ 2
eห้องสมุดไป่ตู้p{
−Eg 2kT
}
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• For a doped, or extrinsic, semiconductor, the increase of one type of carriers reduces the number of the other type. Thus, the product of the two types of carriers remains constant at a given temperature • For Si, ni = 1.45 x 1010 cm-3 and for GaAs, ni = 1.79 x 106 cm-3. GaAs has a lower intrinsic carrier density on account of its larger bandgap
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• When both donors and acceptors are present simultaneously, the impurity which is present at a higher concentration determines the type of conductivity in the semiconductor • The electron in an n-type semiconductor is called the majority carrier, whereas the hole in n-type semiconductor is termed the minority carrier • In a p-type semiconductor, holes are majority carriers and electrons are minority carriers