15_Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach_final

See discussions, stats, and author profiles for this publication at: https:///publication/265210876 Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control ApproachArticle in Circuits and Systems II: Express Briefs, IEEE Transactions on · September 2014Impact Factor: 1.23 · DOI: 10.1109/TCSII.2014.2331097CITATION 1READS 1264 authors, including:Guang-jun XieHefei University of Technology 50 PUBLICATIONS 135 CITATIONSSEE PROFILE Zhang ZhangTeesside University129 PUBLICATIONS 440 CITATIONS SEE PROFILEAll in-text references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.Available from: Guang-jun Xie Retrieved on: 04 June 2016Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control ApproachXin Cheng,Guangjun Xie,Zhang Zhang,and Yizhong YangAbstract—This brief presents a feedforward automatic gain control(AGC)circuit with a short settling time.The proposed AGC combines a digital coarse gain setting and an analogfine gain setting,in which thefine gain setting is carried out by a one-step algorithm,which shortens the settling time drastically.The chip is fabricated in0.13-μm CMOS technology and the measurement results show that the48-dB AGC converges to the desired level within1.2μs.Index Terms—Automatic gain control(AGC),fast-settling,feed-forward,variable gain amplifier(VGA).I.I NTRODUCTIONA UTOMATIC gain control(AGC)is an essential block inmany applications such as wireless receivers,disk drive read channels,and hearing aid instruments to maintain afixed output for different input signal levels[1]–[5].Conventional AGCs adopt a closed-loop feedback scheme to settle the desired output signal level,as shown in Fig.1[6]–[8].However,the closed-loop feedback technique makes the time to determine gain much longer than the time constant of the loopfilter for loop stability.Therefore,the closed-loop scheme is precluded in some applications,which introduce stringent settling-time constraints,such as wireless receivers[9],[10].Meanwhile, feedforward techniques have proved to be adequate to accel-erate gain-setting speed[11]–[14].In this brief,a feedforward AGC is proposed.To obtain fast gain settling and relax the input dynamic range requirement, the system includes a coarse gain-setting block and afine gain-setting block.Thefine gain setting is carried out by a new gain control approach to further accelerate locking speed.This brief is organized as follows.Section II describes the proposed AGC architecture.In Section III,the circuit design of main blocks is discussed.Section IV presents the experimental results and Section V draws the conclusion.II.P ROPOSED AGC A RCHITECTUREIn this brief,the proposed AGC includes a switched coarse gain-setting step and an analogfine gain-setting step to set theManuscript received January19,2014;revised April8,2014;accepted June12,2014.Date of publication June17,2014;date of current version September1,2014.This work was supported by the National Natural Science Foundation of China under Grant61401137.This brief was recommended by Associate Editor H.Sjoland.The authors are with the School of Electronic Science and Applied Physics, Hefei University of Technology,Hefei230009,China(e-mail:gjxie8005@ ).Color versions of one or more of thefigures in this brief are available online at .Digital Object Identifier10.1109/TCSII.2014.2331097Fig.1.Architecture of a conventional feedbackAGC.Fig.2.Architecture of the proposed AGC.gain.The coarse gain-setting step ensures that the input signal offine gain-setting block is not far from its optimal value and thus relaxes the input dynamic range requirement of thefine gain-setting block[9].As shown in Fig.2,the AGC consists of a digital gain control,a programmable gain amplifier(PGA), a root-mean-square(RMS)detector,a variable gain amplifier (VGA),and afixed gain amplifier(FGA).The digital gain control and the PGA serve as coarse gain-setting block to pro-vide a0/10/20/30/40/50-dB programmable gain,whereas the VGA and the RMS detector formfine gain-setting block with a feedforward topology.Finally,an FGA with good linearity is cascaded in the chain to improve linearity of the AGC,since linearity is dominated by the last stage of cascade amplifiers.III.M AIN C IRCUIT D ESCRIPTIONA.Coarse-Gain ControlThe PGA of coarse-gain control,as shown in Fig.3,provides a0/10/20/30/40/50-dB programmable gain throughfive10-dB FGAs A1–A5andfive pairs of control switches S1–S5.Gain control is realized by switches that selectively turn on or off according to the control bits generated by corresponding control.The operation process of the coarse gain setting is shown in Fig.4.Atfirst,input signal V in(V0)is compared with the reference voltage V ref.As soon as V in is larger than V ref,which means the peak voltage of V in is larger than V ref,the switch1549-7747©2014IEEE.Personal use is permitted,but republication/redistribution requires IEEE permission.See /publications_standards/publications/rights/index.html for more information.Fig.3.Topology of the coarse gaincontrol.Fig.4.Flowchart of the coarse gainsetting.Fig.5.Circuits implementation of fine-gain control.(a)Schematic of the detector.(b)Schematic of the VGA.S 1is on and so are S 2–S ly,the gain of PGA is set as 0dB and the output of PGA V out is equal to V in .Contrarily,if V in keeps smaller than V ref during the period,which means the peak voltage of V in is smaller than V ref ,the switch S 1is off and V in is amplified to V 1by A 1.Then,V 1is compared with V ref again.The process for adjusting gain will not stop until the peak voltage of the amplified signal V i (i =1,...,5)islargerFig.6.Schematic of theFGA.Fig.7.Chip photograph of the proposed AGC.than V ref or V in is amplified by all of the five amplifiers,namely the gain of PGA is set as 50dB and the output of PGA V out is equal to V 5.As shown in Fig.3,the proposed digital gain control consists of a comparator and a digital logic circuit.The comparator compares the input signal (V i ,i =0,...,4)with V ref and converts the analog input signal into a digital signal.When the input signal is larger than V ref ,the output of comparator is “1,”whereas when the input signal is smaller than V ref ,the output of comparator is “0.”Based on the output of comparator,the digital logic circuit generates a control bit to decide whether the corresponding switch in PGA is on or off and thus set the gain of PGA.It should be noted that the coarse gain control employs a novel comparator-based configuration,instead of a conventional peak detector to reduce gain-settling time.B.Fine-Gain ControlAs shown in Fig.2,the fine-gain control consists of a VGA and an RMS detector.The proposed feedforward algorithm operates in two stages.First,the RMS detector detects signal strength at the input of the VGA and generates a control voltage proportional to the signal strength.Second,the gain of the VGA is set based on the control voltage.The RMS detector is shown in Fig.5(a):Differential inputs V in+and V in −from VGA are fed to gates of NMOS M 1and M 2,which are operated in strong inversion to provide a squaring function.Cross-coupled differential pairs M 3–M 6full-wave rectify the currents I 1and I 2.The differential pairs must work as switches;thus,their gate voltages are driven by large signals V p and V n ,boosted by amplifier A.During the positive half of period when V in+>V in −,V p outputs high level to turn on M 4and M 5,whereas V n outputs low level to turn offCHENG et al.:FAST-SETTLING FEEDFORWARD AGC BASED ON A NEW GAIN CONTROL APPROACH653Fig.8.Measured output signals of the AGC with different amplitudes of input signal;(a)input amplitude of0.5mV(CH1:50mV/div,CH2:100mV/div, CH3:500mV/div);(b)input amplitude of10mV(CH1:50mV/div, CH2:100mV/div,CH3:500mV/div);(c)input amplitude of120mV(CH1: 100mV/div,CH2:100mV/div,CH3:500mV/div).M3and M6.Therefore,I9,which is equal to I1is larger than I8,which is equal to I2.During the negative half-period,I9, which is equal to I2is still larger than I8,which is equal to I1.The full-wave rectified currents I8and I9are averaged to complete the amplitude detection.A cascade of twofirst-order low-passfilters with a corner frequency of10kHz performs the averaging.By current mirror and current subtraction,the current I c is equal to I9−I8,which is proportional to the detected amplitude.I c is then mirrored to VGA via V c to achieve gain control.Assuming thatI C=k1A in(1)where A in is the amplitude of input signal,and k1is a constant depending on the detector and input signal.For a sinusoidal input signal,k1=(4/π)·μn C ox(W/L)1,2.As shown in Fig.5(b),the proposed VGA is implemented by a cascade of two identical amplifiers[15],where the tailcurrent Fig.9.Plot of gain versus input amplitude.I c is mirrored from the detector,as mentioned before.In A1 (A2),the output resistances of M1b–M6b are designed to be several hundred times of1/g m3b,4b;therefore,the gain of A1 (A2)can be approximately expressed asAv1=G m·R L≈g m1b,2bg m3b,4b=WL1b,2bI bWL3b,4bI C=k2I C(2)where k2=((W/L)1b,2b I b)/(W/L)3b,4b.So the gain of the VGA is given byAv=A2v1=k2I C(3) and substituting(1)in(3)yieldsAv=k2k1A in(4)which means the gain of the VGA is inversely proportional to input signal amplitude.Thus,for a VGA input signal with amplitude A in,the amplitude of the VGA output can be expressed asA out=Av·A in=k2k1A in·A in=k2k1(5)which means that the output of the VGA remains constant for any signal within input dynamic range.Furthermore,the gain convergence is done with“one step”;as soon as the input signal is detected,the gain of the VGA is settled.C.Fixed-Gain AmplifierIn general,a large variable gain range for VGA results in poor linearity.To settle down the tradeoff,an FGA with constant gain but good linearity is cascaded as the last stage. The FGA schematic is shown in Fig.6.Differential input V in= V i+−V i−is applied between the gates of source followers M1a and M1b,which are connected in feedback loops with M2a and M2b to form a pair offlipped voltage followers(FVFs). The FVFs force constant current in M1a and M1b,so that the nodes X1and X2follow V i+and V i−with a constant V GS offset.Thus,the current I X through resistor R X is accurately654IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II:EXPRESS BRIEFS,VOL.61,NO.9,SEPTEMBER2014Fig.10.Measurement of AGC convergence;(a)attack time with an upward stepwise input signal;(b)decay time with a downward stepwise input signal. proportional to V in.A highly linear transconductance G m= 2/R X can be achieved.Feeding the output current of the transconductor to a load R L gives a constant gain2R L/R X. This topology provides a gain range of0dB to20dB within the allowed distortion limit,and in this application the gain of the FGA is set as15dB.IV.E XPERIMENTAL R ESULTSThe AGC was been fabricated in a standard0.13-μm CMOS process.The microphotograph of the chip is shown in Fig.7. The area including pads is0.6mm×0.9mm.The measurement is performed with sinusoidal input signal.At an input frequency of5MHz,the measured transient plots of the AGC with different amplitudes of input signal are shown in Fig.8,which are output of PGA,output of VGA,and output of AGC in turn.Note that the distances between adjacent horizontal grid lines for every plot of each figure.For an input amplitude of0.5mV,as Fig.8(a)shows, an amplified signal with amplitude of48mV appears at the output of PGA.The signal settles down with an amplitude of 85mV through VGA,andfinally its amplitude is amplified to 400mV by FGA.For an input amplitude of10mV,as Fig.8(b) shows,it is amplified to about30mV through PGA.Thenthe Fig.11.THD versus input amplitude plot of theAGC.Fig.12.Output spectrums for different input signal amplitudes;(a)40-mVp input signal;(b)0.5-mVp input signal.signal settles down with amplitude of80mV via VGA and,finally,amplified to375mV.For an input amplitude of120mV, as Fig.8(c)shows,it keeps its initial amplitude120mV at an output of PGA and then its amplitude is compressed to82mV by VGA and isfinally is amplified to385mV.This illustrates that the PGA can afford proper gain based on the power of inputCHENG et al.:FAST-SETTLING FEEDFORWARD AGC BASED ON A NEW GAIN CONTROL APPROACH 655TABLE IC OMPARISON OF P RINCIPAL CHARACTERISTICSsignal and that the signal power can be settled down around a steady value through VGA and amplified by fixed gain of FGA finally.In other words,the three blocks of AGC work well.Fig.9gives the plot of gain versus input amplitude,which shows a gain range of 10to 58dB with a gain error less than 0.9dB when the amplitude of the input signal varies from 120to 0.5mV .To check convergence of the AGC,a 5-MHz stepwise input signal is introduced.The minimum input amplitude is 20mV ,which is restricted by the wave generator,and the maximum in-put amplitude is 120mV .An upward and a downward stepwise signal are employed to measure attack time and decay time,respectively.Fig.10shows that the AGC can adjust signal to the desired level within 1.2μs for the worst case.The measured total harmonic distortion (THD)versus input amplitude plot is given in Fig.11.It shows a minimum THD of 0.32%for 40-mVp input signal.See Fig.12(a)and a maximum THD of 1.37%for 0.5-mVp input signal and see also Fig.12(b).The complete AGC circuit operates from 1.2-V supply and draws 4.3mA.Finally,the principal characteristics of this brief and the comparison with other AGC designs are summarized in Table I.Considering the different frequencies of input signals,the proposed structure achieves a shorter settling time while not sacrificing linearity and noise performance compared with other AGCs.This architecture can be used in wireless receivers and other applications with tight settling-time requirements.V .C ONCLUSIONA fast-settling feedforward AGC,which consists of coarse-gain control and fine-gain control,is presented.The fine-gain setting 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