EDA三八译码器程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clk_div is
port(clk:in std_logic;
clk_div:out std_logic);
end clk_div;
architecture rt1 of clk_div is
signal q_temp:integer range 0 to 5999999;
begin
process(clk)
begin
if(clk'event and clk='1') then
if(q_temp=5999999) then
q_temp<=0;
else
q_temp<=q_temp+1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if(q_temp=5999999) then
clk_div<='1';
else
clk_div<='0';
end if;
end if;
end process;
end rt1;
library ieee;
use ieee.std_logic_1164.all;
entity seg7 is
port(q: in std_logic_vector(3 downto 0);
segment: out std_logic_vector(0 to 7));
end seg7;
architecture rt1 of seg7 is
begin
process(q)
begin
case q is
when "0000"=> segment <="11000000";
when "0001"=> segment <="11111001";
when "0010"=> segment <="10100100";
when "0011"=> segment <="10110000";
when "0100"=> segment <="10011001";
when "0101"=> segment <="10010010";
when "0110"=> segment <="10000010";
when "0111"=> segment <="11011000";
when "1000"=> segment <="10000000";
when "1001"=> segment <="10010000";
when others=> segment <="XXXXXXXX";
end case;
end process;
end rt1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count3081 is
port(
enable:in std_logic;
clk0:in std_logic;
q1:out std_logic_vector(3 downto 0);
q2:out std_logic_vector(3 downto 0);
q3:out std_logic_vector(3 downto 0);
q4:out std_logic_vector(3 downto 0));
end count3081;
architecture rt1 of count3081 is
signal q1_temp,q2_temp,q3_temp,q4_temp:std_logic_vector(3 downto 0);
begin
process(clk0)
begin
if(clk0'event and clk0='1')then
if(enable='1')then
if(q4_temp="0011" and q3_temp="0000" and q2_temp="1000" and q1_temp="0001") then
q1_temp<="0000";
q2_temp<="0000";
q3_temp<="0000";
q4_temp<="0000";
else
if(q1_temp="1001")then
q1_temp<="0000";
q2_temp<=q2_temp+1;
else
q1_temp<=q1_temp+1;
if(q2_temp="1001")then
q2_temp<="0000";
q3_temp<=q3_temp+1;
else
q2_temp<=q2_temp+1;
if(q3_temp="1001")then
q3_temp<="0000";
q4_temp<=q4_temp+1;
else
q3_temp<=q3_temp+1;
if(q4_temp="0011")then
q4_temp<="0000";
end if;
end if;
end if;
end if;
end if;
end if;
end if;
q1<=q1_temp;
q2<=q2_temp;
q3<=q3_temp;
q4<=q4_temp;
end process;
end rt1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ch30 is
port(clk:in std_logic;
enable:in std_logic;
segment1:out std_logic_vector(0 to 7);
segment2:out std_logic_vector(0 to 7);
segment3:out std_logic_vector(0 to 7);
segment4:out std_logic_vector(0 to 7)
);
end ch30;
architecture rt1 of ch30 is
component clk_div
port(clk:in std_logic;
clk_div:out std_logic);
end component;
component count3081
port(
enable:in std_logic;
clk0:in std_logic;
q1:out std_logic_vector(3 downto 0);
q2:out std_logic_vector(3 downto 0);
q3:out std_logic_vector(3 downto 0);
q4:out std_logic_vector(3 downto 0));
end component;
component seg7
port(q: in std_logic_vector(3 downto 0); segment: out std_logic_vector(0 to 7));
end component;
signal x:std_logic;
signal q1:std_logic_vector(3 downto 0);
signal q2:std_logic_vector(3 downto 0);
signal q3:std_logic_vector(3 downto 0);
signal q4:std_logic_vector(3 downto 0);
begin
U0:clk_div port map(clk,x);
U1:count3081 port map(enable,x,q1,q2,q3,q4);
U2:seg7 port map(q1,segment1);
U3:seg7 port map(q2,segment2);
U4:seg7 port map(q3,segment3);
U5:seg7 port map(q4,segment4);
end;。