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1. INTRODUCTION
Multimedia applications are being used increasingly in many embedded and portable systems, such as mobile phones and PDAs, which require low power consumption while meeting throughput constraints. Power reduction methods optimized for these applications are therefore becoming more important than ever. In general, multimedia applications require less emphasis on reducing latency than on maintaining a constant rate of input or output. This is achieved by ironing out fluctuations in the inter-arrival time of input frames by buffering several frames to achieve a constant rate of input consumption. Similarly, output buffering is also used to cope with
Power-efficient design of multimedia applications becomes more important as they are used increasingly in many embedded systems. We propose a simple dynamic voltage scheduling technique which suits multimedia applications well and, in case of soft real-time applications, allows all idle intervals of the processor to be fully exploited by using buffers. Our main theme is to determine the minimum buffer size to maximize energy saving in three cases: (i) single-task, (ii) multiple-subtask and (iii) multi-task. We also present a technique of adjusting task deadlines for further reducing energy consumption in the multiple-subtask and multi-task cases. Unlike other DVS techniques using buffers, we guarantee to meet the real-time latency constraint. Experimental results show that the proposed technique does indeed achieve significant power reduction in real-world multimedia applications. Categories and Subject Descriptors: C.3 [Computer Systems Organization]: Special-Purpose and ApplicationBased Systems - Real-Time and Embedded Systems; F2.2 [Analysis of Algorithms and Problem Complexity]: Nonnumerical Algorithms and Problems - Sequencing and Scheduling General Terms: Algorithms, Performance Additional Key Words and Phrases: Dynamic voltage scheduling, low-power systems, multimedia applications, buffer requirement estimation
Dynamic Voltage Scheduling with Buffers in LowPower Multimedia Applications
CHAESEOK IM AND SOONHOI HA Seoul National University, Korea and HUISEOK KIM Hankook MDS, Korea ________________________________________________________________________
Fig. 1. WST & VST for an example task.
We denote dynamic voltage scheduling (DVS) as a method that dynamically assigns a supply voltage for each task to utilize the slack time and we propose a simple but effective task-by-task DVS technique suitable for multimedia applications. We exploit the slack time fully by buffering multiple input data or output results so there is always at least one runnable task on the processor. Nielsen et al. [1994] and Gutnik [1996] have proposed some ideas for using buffers in power reduction. They use buffers to average workloads among input samples. However, unlike us, they do not consider VST and adopt the critical assumption that the exact workloads of all input samples can be known a priori. The main theme of our proposed technique is to estimate the minimum buffer size so as to achieve the maximum energy saving in three cases: (i) single-task, (ii) multiplesubtask and (iii) multi-task. And we also adjust the deadlines of tasks adequately to
This work was supported by National Research Laboratory Program (No. M1-0104-00-0015) and the Brain Korea 21 Project. The ICT at Seoul National University provided research facilities for this study. Authors’ addresses: C. Im and S. Ha, School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sinlim-dong, Gwanak-gu, Seoul, 151-742, Korea; email: {csim; sha}@iris.snu.ac.kr; H. Kim, Hankook MDS, 5F Uniana B/D, 907-18, Mok-5-dong, Yangchon-gu, Seoul, 158-055, Korea; email: huiseok@. Permission to make digital/hard copy of part of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication, and its date of appear, and notice is given that copying is by permission of the ACM, Inc. To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee.
fluctuating processing time while maintaining a constant rate of output production. In short, latency can be tolerated to some extent in multimedia applications. One of the mosconsumption is to use a variable speed processor (VSP), which can vary its clock frequency in response to changes in the supply voltage, while still achieving the required performance. Reducing the power consumption of a VSP can be achieved by exploiting idle intervals. We identify two kinds of idle intervals, and denote them as worst-case slack time (WST) and workloadvariation slack time (VST) as defined by Lee and Sakurai [2000]. WST occurs because the utilization of a processor is usually less than 100%, even if all tasks exhibit their worst-case execution times. WST can be extracted from the scheduling result before task execution. VST comes from variations of execution time due to data-dependent computation, over-estimation of worst-case execution time, and so on. VST can only be known after actual task execution. Figure 1 illustrates these slack times for an example task. We focus on the fact that the more slack time we can utilize, the more energy saving can be achieved.