MSP430F5529测周法测量信号频率

MSP430F5529测量频率

-----测周法信号变换电路

过零比较器，lm393输出上拉电阻，两电阻分压

程序

#include

#include "stdio.h"

#include "math.h"

//测周法，在捕获过程中，定时溢出不能被检测出，选择时钟频率为低频时能测出低频，频率高能测出频率高的部分

/*

* main.c

*/

long long start=0;

//long long int stop=0;

double fre=0.0;

unsigned char i=0;

unsigned char over=0;

void SetVcoreUp (unsigned int level)

{

// Open PMM registers for write

PMMCTL0_H = PMMPW_H;

// Set SVS/SVM high side new level

SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;

// Set SVM low side to new level

SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;

// Wait till SVM is settled

while ((PMMIFG & SVSMLDL YIFG) == 0);

// Clear already set flags

PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);

// Set VCore to new level

PMMCTL0_L = PMMCOREV0 * level;

// Wait till new level reached

if ((PMMIFG & SVMLIFG))

while ((PMMIFG & SVMLVLRIFG) == 0);

// Set SVS/SVM low side to new level

SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;

// Lock PMM registers for write access

PMMCTL0_H = 0x00;

}

void init_clock()

{

SetVcoreUp (0x01);

SetVcoreUp (0x02);

SetVcoreUp (0x03);

UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO

UCSCTL4 |= SELA_2; // Set ACLK = REFO

__bis_SR_register(SCG0); // Disable the FLL control loop

UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx

UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation UCSCTL2 = FLLD_0 + 609; // Set DCO Multiplier for 25MHz

// (N + 1) * FLLRef = Fdco

// (762 + 1) * 32768 = 25MHz

// Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop

__delay_cycles(782000);

do

{

UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);

// Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags

}while (SFRIFG1&OFIFG); // Test oscillator fault flag

}

void send_char(char sc)

{

UCA0TXBUF=sc;

while(!(UCA0IFG&UCTXIFG));

void send_string(char *s)

{

while(*s!='\0')

{

send_char(*s++);

}

}

init_uart()

{

P3SEL |= BIT3+BIT4; // P3.3,4 = USCI_A0 TXD/RXD

UCA0CTL1 |= UCSWRST; // **Put state machine in reset**

UCA0CTL1 |= UCSSEL__SMCLK; // SMCLK

UCA0BR0 = 173; // 1MHz 115200 (see User's Guide)

UCA0BR1 = 0; // 1MHz 115200

UCA0MCTL |= UCBRS_5 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx=0 UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**

UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt

send_string("CLS(0);\r\n");

}

int main(void) {

char buf[60]="\0";

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

init_clock();

init_uart();

P1DIR &= ~BIT2; // P1.2 in

P1SEL |= BIT2; //捕获输入

TA0CTL = TASSEL_2 +ID__8 + MC_2 + TACLR+TAIE; // SMCLK, 连续mode, clear TAR 8分频下限可以测到8Hz。上限200K左右

TA0CCTL1 =CM_1 +SCS +CAP +CCIE;

__bis_SR_register( GIE); // Enter LPM0, enable interrupts

while(1)

{

sprintf(buf,"DS16(0,60,'频率：%1.1f',4);\r\n",fre);

send_string( buf);

__delay_cycles(314574);

}

}

//下限频率15，上限200K左右

#pragma vector=TIMER0_A1_VECTOR

__interrupt void TIMER0_A1_ISR(void)

{

switch(__even_in_range(TA0IV,14))

{

case 0: break; // No interrupt

case 2: //CCR1

{

i++;

if(i==1)

{ over=0;

TA0CTL |=TACLR;

}

if(i>=51)

{

i=0;

TA0CCTL0&=~CCIE;

start=over*65536+TA0CCR1;

fre=125000000/start;

TA0CTL |=TACLR;

}

}

break;

case 4: break; // CCR2 not used

case 6: break; // CCR3 not used

case 8: break; // CCR4 not used

case 10: break; // CCR5 not used

case 12: break; // CCR6 not used

case 14: over++;

break; //定时器溢出

default: break;

}

}