xilinx FPGA DNA 读取 verilog 源代码

/*
2011/11/18

40M Fosc

this time we will create one hz pulse
*/

module one_hz_dna(
clk,
en,

fout,
fout1,
fout2,
data8
);
///////////////////////////////////////dna define/////////////////////////////////////////
input en;

output [7:0] data8;

/* FSM define */

parameter s0 = 8'b00000001;
parameter s1 = 8'b00000010;
parameter s2 = 8'b00000100;
parameter s3 = 8'b00001000;
parameter s4 = 8'b00010000;
parameter s5 = 8'b00100000;
parameter s6 = 8'b01000000;
parameter s7 = 8'b10000000;

//parameter DNA_LEN = 56;
//parameter DNA = 56'b01010100_00111011_00101110_11011001_01111001_11010100_00110010;

parameter DNA_LEN = 60;
parameter DNA = 56'b0100_00111011_00101110_11011001_01111001_11010100_00110010_1111;


reg READ;
reg SHIFT;
reg DCLK;
wire DOUT;
wire DIN;

reg [7:0] state, next;
reg [5:0] shift_cnt;
reg [55:0] dna_reg;

///////////////////////////////////////one hz define//////////////////////////////////////
input clk;

output fout;
output fout1,fout2;

reg[25:0] t_cnt;
reg fout;
wire fout1,fout2;

parameter FOSC = 40000000;
//parameter FOSC = 4000;
parameter CNT_LEN = FOSC - 1;
/////////////////////////////////////////////////////////////////////////////////////////

// DNA_PORT : In order to incorporate this function into the design,
// Verilog : the following instance declaration needs to be placed
// instance : in the body of the design code. The instance name
// declaration : (DNA_PORT_inst) and/or the port declarations within the
// code : parenthesis may be changed to properly reference and
// : connect this function to the design. All inputs
// : and outputs must be connected.

// <-----Cut code below this line---->

// DNA_PORT: Access to the device-specific DNA value
// Spartan-3A, Virtex-6, Spartan-6
// Xilinx HDL Language Template, version 12.4

DNA_PORT #(
.SIM_DNA_VALUE(57'h000000000000000) // Specifies the unique DNA value
// for simulation test
) DNA_PORT_inst (

.DOUT(DOUT), // 1-bit DNA output data
.CLK(DCLK), // 1-bit clock input
.DIN(DIN), // 1-bit user data input pin
.READ(READ), // 1-bit input, active high load DNA, active low READ
.SHIFT(SHIFT) // 1-bit input, active high SHIFT enable
);

// End of DNA_PORT_inst instantiation


////////////////////////////////////////////////////////////////
always @(posedge clk)
begin
if(t_cnt < CNT_LEN)
t_cnt <= t_cnt + 1;
else
begin
t_cnt <= 0;
fout <= ~fout;
end
end

//assign fout1 = 1;
/

/assign fout2 = 0;
//////////////////////////////////////////////////////////////////////////////
always @(posedge clk or negedge en)
begin
if(!en)
state <= s0;
else
state <= next;
end

always @(state or en or shift_cnt)
begin
case(state)
s0:
begin
if(!en)
next = s0;
else
next = s1;
end
s1:
begin
next = s2;
end
s2:
begin
next = s3;
end
s3:
begin
next = s4;
end
s4:
begin
next = s5;
end
s5:
begin
next = s6;
end
s6:
begin
if(shift_cnt < DNA_LEN)
next = s5;
else
next = s7;
end
s7:
begin
next = s7;
end
default: next = s0;
endcase
end

always @(posedge clk)
begin
case(next)
s0:
begin
READ <= 0;
SHIFT <= 0;
DCLK <= 0;
shift_cnt <= 0;

dna_reg <= 56'h00_00_00_00_00_00_00;
end
s1:
begin
READ <= 1;
end
s2:
begin
DCLK <= 1;
end
s3:
begin
DCLK <= 0;
READ <= 0;
end
s4:
begin
SHIFT <= 1;
end
s5:
begin
DCLK <= 1;
end
s6:
begin
shift_cnt <= shift_cnt + 1;

DCLK <= 0;
// we should send the dout to dna_reg here!
dna_reg <= dna_reg << 1;
dna_reg[0] <= DOUT;
end
s7:
begin
READ <= 0;
SHIFT <= 0;
DCLK <= 0;
shift_cnt <= 0;
end
default:
begin
READ <= 0;
SHIFT <= 0;
DCLK <= 0;
shift_cnt <= 0;
end
endcase
end

assign DIN = 1;

assign fout1 = (dna_reg == DNA)? 0:fout;
assign fout2 = fout;

assign data8 = dna_reg[7:0];

endmodule