CPU报告

Computer Organization and Architecture

Course Design

CPU REPORT

04006628 邓睿 04006618 肖游龙 Time:

2009.04.08

Purpose

The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.

At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.

Instruction Set

Single-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code(opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing.

For simplicity, the size of memory is 256 16 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1

OPCODE [15..8]ADDRESS

[7..0]

Figure 1 the instruction format

Internal Registers and Memory

MAR (Memory Address Register)

MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.

MBR(Memory Buffer Register)

MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16

bits.

PC (Program Counter)

PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.

IR (Instruction Register)

IR contains the opcode part of an instruction. In our design, IR has 8 bits.

BR (Buffer Register)

BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has 16 bits.

ACC (Accumulator)

ACC holds one operand for ALU, and generally ACC holds the calculation result of ALU. In our design, ACC has 16 bits.

MR (Multiplier Register)

MR is used for implementing the MPY instruction, holding the multiplier at the beginning of the instruction. When the instruction is executed, it holds part of the product.

DR (Division Register)

DR is used for implementing the DIV instruction, you can define it according to your division algorithm.

LPM_RAM_DQ

LPM_RAM_DQ is a RAM with separate input and output ports, it works as memory, and its size is 256 16. Although it’s not an internal register of CPU, we need it to simulate and test the performance of CPU.

All the registers are positive-edge-triggered.

All the reset signals for the registers are synchronized to the clock signal.

ALU

ALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as follows

T able 1 ALU Operations

Operations Explanations

ADD (ACC)?(ACC)+(BR)

SUB (ACC)?(ACC)-(BR)

AND (ACC)?(ACC) and (BR)

OR (ACC)?(ACC) or (BR)

NOT (ACC)?Not (A CC)

SRL (ACC)?Shift (A CC) to Left 1 bit

SRR (ACC)?Shift (A CC) to Right 1 bit Microprogrammed Control Unit

We have learnt the knowledge of Microprogrammed control unit. Here, we only review some terms and basic structures.

In the Microprogrammed control, the microprogram consists of some microinstructions and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.

Sequencing Logic Control Address Register

Control Memory

Control Buffer Register

Figure 2 Control Unit Micro-architecture

Figure 2shows the key elements of such an implementation. The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in the figure is a sequencing unit that loads the control address register and issues a read command.

CPU Design

M

B

R

M A R

PC IR

ACC

ALU

Control

Unit

B

R

Control signals

Flags

Control

Signals

Figure 3 CPU data path and control signals

Figure 3indicates a simple CPU architecture and its use of a variety of internal data paths and control signals. Our CPU design should be based on this architecture. Example: LOAD instruction

MBR<=memory

IR<=MBR

MAR<=MBR

PC<=PC+1

MBR<=memory

BR<=MBR

ACC<=0

ACC<=ACC+BR

MAR<=PC

Figure 4 Control Flowchart of the LOAD instruction

T able 2 Some Control signals for the LOAD instruction

Bit in Control Memory Micro-operation Meaning

C0 CAR<=CA R+1 Control Address Increment

C1 CAR<=*** Control Address Redirection, depends on the position of microinstruction

C2 CAR<=0 Reset Control Address to zero position

C3 MBR<=memory Memory Content to MBR

C4 IR<=MBR[15..8] Copy MBR[15..8] to IR for OPCODE

C5 MAR<=MBR[7..0] Copy MBR[7..0] to MAR for address

C6 PC<=PC+1 Increment PC for indicating position

C7 BR<=MBR Copy MBR data to BR for buffer to A LU

C8 ACC<=0 Reset ACC register to zero

C9 ACC<=A CC+BR Add BR to A CC

C10 MAR<=PC Copy PC value to MAR for next address

……………

Then according to the control flowchart and the table, the microprogram and control signals of the LOAD instruction is:

T able 3 Microprogram for LOAD instruction

Microprogram Control signals

MBR<=memory, CAR<=CA R+1 C3, C0

IR<=MBR[15..8], CA R<=CAR+1 C4, C0

CAR<=*** (*** is determined by OPCODE) C1

MAR<=MBR[7..0], PC<=PC+1, CA R<=CAR+1 C5, C6, C0

MBR<=memory, CAR<=CA R+1 C3, C0

BR<=MBR, A CC<=0, CAR<=CA R+1 C7, C8, C0

ACC<=A CC+BR, CAR<=CA R+1 C9, C0

MAR<=PC, CA R<=0 C10,C2

Design description results

According to the introduction an requirements, we designed the micro operations as follows:

STORE X IRopcode←MBR,CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←ACC,CAR←CAR+1

memory←MBR,CAR←CAR+1 W

MAR←PC7-0,CAR←0

C17,C4

C5

C13,C19,C4

C16,C4

C14,C4

C12,C6

LOAD X MBR←memory,CAR←CAR+1 R

IRopcode←MBR,CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1 R

BR←MBR,ACC←0,CAR←CAR+1

ACC←ACC+BR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C24,C4

C22,C4

C12,C6

ADD X MBR←memory,CAR←CAR+1 R

IRopcode←MBR,CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1 R

BR←MBR,CAR←CAR+1

ACC←ACC+BR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C22,C4

C12,C6

SUB X MBR←memory,CAR←CAR+1 R

IRopcode←MBR,CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0,PC←PC+1,CAR←CAR+1

MBR←memory,CAR←CAR+1 R

BR←MBR,CAR←CAR+1

ACC←ACC-BR,CAR←CAR+1

MAR←PC,CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C23,C4

C12,C6

JMPGEZ X MBR←memory, CAR←CAR+1 R

IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

IF ACC≥0 THEN PC←MBR9-0, CAR←CAR+1

MAR←PC, CAR←0

ELSE PC←PC+1, CAR←CAR+1

MAR←PC, CAR←0

C15,C4

C17,C4

C5

C18,C4

C12,C6

C19,C4

C12,C6

HALT MBR←memory,CAR←CAR+1 R

IRopcode←MBR,CAR←CAR+1

(CAR←opcode)

PC←0, ACC←0, CAR←CAR+1

MAR←PC, CAR←0

C15,C4

C17,C4

C5

C20,C24,C4

C12,C6

MPY IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0, PC←PC+1, CAR←CAR+1

MBR←memory, CAR←CAR+1 R

QR←MBR, CAR←CAR+1

MBR←ACC, CAR←CAR+1

BR←MBR, CAR←CAR+1

0←ACC, CNT←16,CAR←CAR+1

IF multi_add =1 then ACC←ACC+BR, SHIFTR

ELSIF multi_sub=1 then ACC←ACC-BR, SHIFTR

ELSIF multi_shift=1 then SHIFTR

MAR←PC, CAR←0

C17,C4

C5

C13,C19,C4

C15,C4

C26,C4

C16,C4

C21,C4

C28,C26,C4

C27,C25,C22

C27,C25,C23

C27,C25

C12,C6

AND MBR←memory, CAR←CAR+1 R

IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0, PC←PC+1, CAR←CAR+1

MBR←memory, CAR←CAR+1 R

BR←MBR, CAR←CAR+1

ACC←ACC and BR, CAR←CAR+1

MAR←PC, CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C1,C4

C12,C6

OR MBR←memory, CAR←CAR+1 R

IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0, PC←PC+1, CAR←CAR+1

MBR←memory, CAR←CAR+1 R

BR←MBR, CAR←CAR+1

ACC←ACC or BR, CAR←CAR+1

MAR←PC, CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C2,C4

C12,C6

NOT MBR←memory, CAR←CAR+1 R

IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0, PC←PC+1, CAR←CAR+1

MBR←memory, CAR←CAR+1 R

BR←MBR, CAR←CAR+1

ACC←ACC not BR, CAR←CAR+1

MAR←PC, CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C4

C3,C4

C12,C6

SHIFTR IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0, PC←PC+1, CAR←CAR+1

MBR←memory, CAR←CAR+1 R

BR←MBR, ACC←0, CAR←CAR+1

ACC←ACC+BR, CAR←CAR+1

SHIFTR ACC, CAR←CAR+1

MAR←PC, CAR←0

C17,C4

C5

C13,C19,C4

C15,C4

C21,C24,C4

C22,C4

C25,C4

C12,C6

SHIFTL MBR←memory, CAR←CAR+1 R

IRopcode←MBR, CAR←CAR+1

(CAR←opcode)

MAR←MBR7-0, PC←PC+1, CAR←CAR+1

MBR←memory, CAR←CAR+1 R

BR←MBR, ACC←0, CAR←CAR+1

ACC←ACC+BR, CAR←CAR+1

SHIFTR ACC, CAR←CAR+1

MAR←PC, CAR←0

C15,C4

C17,C4

C5

C13,C19,C4

C15,C4

C21,C24,C4

C22,C4

C7,C4

C12,C6

The meaning of every bit of the control memory (ROM) according to your design.

The micro-instructions are stored in the control memory sequentially, starting from 00000000 (HEX). If a control signal is C12, the 12th bit in the control memory should be 1 and the others are all 0.

Bit in read-only control

memory (Bit of ROM)

Micro-operation Control signal name C12MAR←PC7-0PC_into_MA

C13MAR←MBR7-0MB_into_MA

C14memory←MBR ram_write

C15MBR←memory ram_read

C16MBR←ACC AC_into_MB

C17IRopcode←MBR15-12MB_into_IRopcode

C18PC←MBR9-0MB_into_PC

C19PC←PC+1 Increment_PC

C20PC←0 reset_PC

C21BR←MBR MB_into_BR

C22ACC←ACC+BR ADD

C23ACC←ACC-BR SUB

C24ACC←0 reset_ACC

C25shift ACC to right SHIFTR

C26QR←MBR MB_into_QR

C27shift QR to right shift_QR

C28cnt←MBR MB_into_cnt//a decrement count

C29cnt←cnt-1 downcnt

C30cnt←0 reset_cnt

C31

C1ACC←ACC and BR Logic_AND

C2ACC←ACC or BR Logic_OR

C3ACC←not BR Logic_NOT

C4CAR←CAR+1 add1

C6CAR←0 reset

C5CAR←opcode load

C7shift ACC to left SHIFTL

C8

C9

C10

C11

The contents in ROM

Location

control

memory (address, in HEX) contents (in HEX)

(control signals)

micro-program comments

00 00008010 MBR←memory, CAR←CAR+1 Fetch Data

01 00020010 IRopcode←MBR, CAR←CAR+1 Fetch Opcode

02 00000020 CAR←** JUMP

03 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 AND

04 00008010 MBR←memory, CAR←CAR+1

05 00200010 BR←MBR, CAR←CAR+1

06 00000012 ACC←ACC and BR, CAR←CAR+1

07 00001040 MAR←PC, CAR←0 End of AND

08 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 OR

09 00008010 MABR←memory, CAR←CAR+1

0A 00200010 BR←MBR, CAR←CAR+1

0B 00000014 ACC←ACC or BR, CAR←CAR+1

0C 00001040 MAR←PC, CAR←0 End of OR

0D 00000000

0E 00000000

0F 00000000

10 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 STORE

11 00010010 MBR←ACC, CAR←CAR+1

12 00004010 memory←MBR, CAR←CAR+1

13 00001040 MAR←PC, CAR←0 End of STORE

14 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 LOAD

15 00008010 MBR←memory, CAR←CAR+1

16 01200010 BR←MBR, ACC←0, CAR←CAR+1

17 00400010 ACC←ACC+BR, CAR←CAR+1

18 00001040 MAR←PC, CAR←0 End of LOAD

19 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 ADD

1A 00008010 MABR←memory, CAR←CAR+1

1B 00200010 BR←MBR, CAR←CAR+1

1C 00400010 ACC←ACC+BR, CAR←CAR+1

1D 00001040 MAR←PC, CAR←0 End of ADD 1E 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 SUB

1F 00008010 memory←MBR, CAR←CAR+1

20 00200010 BR←MBR, CAR←CAR+1

21 00800010 ACC←ACC－BR, CAR←CAR+1

22 00001040 MAR←PC, CAR←0 End of SUB

23 00040010 PC←MBR9-0, CAR←CAR+1 JMPGEZ

24 00001040 MAR←PC, CAR←0

25 00080010 PC←PC+1, CAR←CAR+1

26 00001040 MAR←PC, CAR←0 End of JMP

27 01100010 PC←0, ACC←0, CAR←CAR+1 HALT

28 00001040 MAR←PC, CAR←0 End of HALT

29 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 MPY

2A 00008010 MABR←memory, CAR←CAR+1

2B 04000010 QR←MBR, CAR←CAR+1

2C 00010010 MBR←ACC, CAR←CAR+1

2D 00200010 BR←MBR, CAR←CAR+1

2E 11000010 0←ACC, CNT←16,CAR←CAR+1

2F 00000000

30 00400010 ACC←ACC+BR, CAR←CAR+1 Multi_add

31 2A000000 Shift ACC QR to Right, CNT←CNT-1

32 00000000

33 00800010 ACC←ACC-BR, CAR←CAR+1 Multi_sub

34 2A000000 Shift ACC QR to Right, CNT←CNT-1

35 00000000

36 2A000000 Shift ACC QR to Right, CNT←CNT-1 Multi_shift

37 00000000

38 00001040 MAR←PC, CAR←0 End of MPY

39 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 NOT

3A 00008010 MABR←memory, CAR←CAR+1

3B 00200010 BR←MBR, CAR←CAR+1

3C 00000018 ACC←NOT BR, CAR←CAR+1

3D 00001040 MAR←PC, CAR←0 End of NOT 3E 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 SHIFTR

3F 00008010 MBR←memory, CAR←CAR+1

40 01200010 BR←MBR, ACC←0, CAR←CAR+1

41 00400010 ACC←ACC+BR, CAR←CAR+1

42 02000010 SHIFTR ACC, CAR←CAR+1

43 00001040 MAR←PC, CAR←0 End of SHIFTR

44 00082010 MAR←MBR7-0, PC←PC+1, CAR←CAR+1 SHIFTL

45 00008010 MBR←memory, CAR←CAR+1

46 01200010 BR←MBR, ACC←0, CAR←CAR+1

47 00400010 ACC←ACC+BR, CAR←CAR+1

48 00000090 SHIFTL ACC, CAR←CAR+1

49 00001040 MAR←PC, CAR←0 End of SHIFTL

Design description

The overall design

The whole design:

Appendix

The detailed design is shown in Verilog-HDL version (1)BR

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity br is

port

(

mbr_in : in std_logic_vector(15 downto 0);--from mbr clk : in std_logic;

cs : in std_logic_vector(31 downto 0);

br_out : out std_logic_vector(15 downto 0)

);

end br;

architecture behave of br is

begin

process(clk)

begin

if clk'event and clk='1' then

if cs(12)='1' then

br_out<=mbr_in;

end if;

end if;

end process;

end behave;

(2)MBR

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity mbr is

port

(

memery_in : in std_logic_vector(15 downto 0);--output from ram

acc : in std_logic_vector(15 downto 0);--output from acc of alu

clk : in std_logic;

cs : in std_logic_vector(31 downto 0);--output from cs

mbr_out : out std_logic_vector(15 downto 0) --to low and high

);

end;

architecture behar of mbr is

begin

process(clk)

begin

if (rising_edge(clk)) then

if (cs(7)='1') then

mbr_out<=memery_in;

elsif (cs(8)='1') then

mbr_out<=acc;

end if;

end if;

end process;

end;

(3)IR

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY IR IS

PORT

( mbr_in : IN std_logic_vector(7 downto 0); --MBR[15..8] accept-opcode

cs : in std_logic_vector(31 downto 0);

clk : IN std_logic;

ir_out : out std_logic_vector(7 downto 0)

);

END IR;

ARCHITECTURE behave OF IR IS

BEGIN

PROCESS(clk)

BEGIN

IF rising_edge(clk) THEN

if cs(5)='1' then

ir_out<=mbr_in;

end if;

END IF;

END PROCESS;

END behave;

(4)PC

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY PC IS

PORT

( mbr_in : IN std_logic_vector(7 downto 0); --MBR[15..0]

cs : IN std_logic_vector(31 downto 0);

clk : IN std_logic;

pc_out : OUT std_logic_vector(7 downto 0)

);

END PC;

ARCHITECTURE behave OF PC IS

BEGIN

PROCESS(clk)

variable temp:std_logic_vector(7 downto 0);

BEGIN

if (rising_edge(clk)) then

if cs(10)='1' THEN --reset

temp:="00000000";

elsif cs(9)='1' then --MBR to PC

temp:=mbr_in;

elsif cs(11)='1' then --increment

temp:=temp+1;

end if;

pc_out<=temp;

END IF;

END PROCESS;

END behave;

(6)ALU

entity alu is

port(

clk: in std_logic;

reset:in std_logic;

con_to_alu:in std_logic_vector(31 downto 0);

br_to_alu:in std_logic_vector(7 downto 0);

alu_to_acc:out std_logic_vector(7 downto 0);

acc_to_alu:in std_logic_vector(7 downto 0)

);

end alu;

architecture arc_alu of alu is

begin

process(clk,reset)

begin

if reset='1' then

alu_to_acc<="00000000";

elsif (clk'event and clk='1') then

if con_to_alu(22)='1' then

alu_to_acc<=br_to_alu+acc_to_alu;--add elsif con_to_alu(23)='1' then

alu_to_acc<=acc_to_alu-br_to_alu;--sub elsif con_to_alu(1)='1' then

alu_to_acc<=acc_to_alu and br_to_alu;--and elsif con_to_alu(2)='1' then

alu_to_acc<=acc_to_alu or br_to_alu;--or

elsif con_to_alu(3)='1' then

alu_to_acc<=not br_to_alu;--not

elsif con_to_alu(25)='1' then

alu_to_acc<='0' & acc_to_alu(7 downto 1);--shiftr elsif con_to_alu(7)='1' then

alu_to_acc<=acc_to_alu(6 downto 0) & '0';--shiftl end if;

end if;

end process;

end arc_alu;

(7)control_unit

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

ENTITY control_unit IS

PORT

( clk : in std_logic;

flag : in std_logic; --ACC is 0 or not

cs : in std_logic_vector(31 downto 0);--from accis of acc

IR_out : in std_logic_vector(7 downto 0);

address_out : out std_logic_vector(7 downto 0) --to the rom

);

END control_unit ;

ARCHITECTURE behave OF control_unit IS

BEGIN

PROCESS (clk)

variable address : std_logic_vector(7 downto 0);

BEGIN

IF (rising_edge(clk)) THEN

if cs(1)='1' then --Increament car

address:=address+1;

elsif cs(0)='1' then --reset car

address:="00000000"; --32bits hex

elsif cs(2)='1' then --load

case IR_out is

when "00000001"=> --ADD 01

address:="00000100";

when "00000010"=> --SUB 02

address:="00001011";

when "00000011"=> --AND 03

address:="00010010";

when "00000100"=> --OR 04

address:="00011001";

when "00001010"=> --NOT 0a

address:="00100000";

when "00001011"=> --SHIFTR 0b address:="00100111";

when "00001100"=> --SHIFTL 0c address:="00101111";

when "00001101"=> --STORE 0d address:="01000001";

when "00001110"=> --LOAD 0e

address:="01000111";

when "00001000"=> --JUMP 08 address:="01001110";

when "00000101"=> --jmpegz 05 if flag='0' then

address:="00111011";

else address:="00111101";

end if;

when "00000111"=> --HALT 07

address:="00110111";

when others=>null;

end case;

end if;

address_out<=address;

END IF;

END PROCESS;

END behave;

Above all,we must use it to do something.

As shows:

Then let's do an easy problem to show how we use the cpu: A example:

Problem:1+2+3+4+……..+100

1.C language program with the instructions

Program with c Program

with

instructions Contents of memory in HEX Address Contents

Sum=0; LOAD 20 00 0E20

STORE 24 01 0D24 Temp=100; LOAD 21 02 0E21

STORE 23 03

0D23

Loop:sum=sum+temp ; LOOP:LOAD 24 04 0E24 ADD 23 05 0123 STORE 24 06 0D24

Temp=temp-1; LOAD 23 07 0E23

SUB 22 08 0222

STORE 23 09 0D23 If temp>=0 goto loop JMPGEZ LOOP 0A 0504 Sum＝sum+1 LOAD 24 0B 0124

ADD 24 0C 0C24

STORE 24 0D 0D24 end HAL T 10 0700 2. Initialize memory: