FL1001 主控芯片

Design Guide

FL1100

PCI Express to USB 3.0 Host Controller

Revision 0.3

October 15, 2013

? Fresco Logic 2011

Revision History

Revision Date Comment

0.2 Aug. 24, 2011 Preliminary Release

0.3 Dec. 29, 2011 Modify SS USB Trace Length Suggestion

0.4 Oct. 10, 2013 USB3.0 connector placement Suggestion

Table of Contents

1.Introduction (5)

1.1USB (6)

1.2PCI Express (6)

2.Scope (7)

3.Schematic Guidelines (7)

3.1Power (7)

3.1.1Power Rail (7)

3.1.2Ripple Require (7)

3.2PCIE (7)

3.2.1PCIe Interface (7)

3.3USB 3.0 (8)

3.3.1USB3 Interface (8)

3.4Over-Current (9)

3.4.1Over-Current Circuit (9)

3.4.2Over-Current Action (10)

3.5Voltage Drop (10)

3.5.1Worse-case Voltage Drop Topology (10)

3.5.2Voltage Define (10)

https://www.360docs.net/doc/bc14204059.html,yout Guideline (11)

4.1Key Considerations of High-speed PCB Design (11)

4.2Printed Circuit Board (PCB) (11)

4.2.1Material (11)

4.2.2Stack up (12)

4.2.3Characteristic Impedance (12)

4.3General Routing and Placement Routing Rules (13)

4.4Power Integrity (16)

4.4.1Decoupling Recommendation (16)

4.4.2Power Routing Rules (17)

4.5Layout Guidelines (17)

4.5.1USB 3.0 Layout Guidelines (17)

4.5.2PCIe Routing Guide on Motherboard (18)

4.5.3PCIe Routing Guide on Adapter Card (19)

4.5.4PCIe Clock Routing Guides (19)

4.6 USB3.0 connector Placement Suggestion (20)

4.6.1USB 3.0 Radiation Noise (20)

4.6.2Improving shielding on the USB3.0 connector (20)

4.6.3USB3.0 connector placement located (20)

5.Conclusion (21)

List of Figures

F IGURE 3.1PCI E I NTERFACE (8)

F IGURE 3.2USB3I NTERFACE (9)

F IGURE 3.3O VER-C URRENT C IRCUIT (9)

F IGURE 3.4W ORSE-CASE V OLTAGE D ROP T OPOLOGY (10)

F IGURE 4.1S TACK UP (12)

F IGURE 4.2D IFFERENTIAL P AIR R OUTING D IAGRAM (13)

F IGURE 4.3T RACE B END (14)

F IGURE 4.4C ONTINUOUS R EFERENCE G ROUND P LANE (14)

F IGURE 4.5A VOID D ISCONTINUATION R EFERENCE P LANE (14)

F IGURE 4.6G ROUND I SLAND FOR C HANGE L AYER (15)

F IGURE 4.7D IFFERENTIAL T RACE AND VIA S YMMETRIC R OUTING (15)

F IGURE 4.8AC C OUPLING C APACITOR P LACEMENT (16)

F IGURE 4.9USB2.0D IFFERENTIAL P AIR R OUTING (16)

List of Tables

T ABLE 3.1P OWER R AIL (7)

T ABLE 3.2R IPPLE R EQUIRE (7)

T ABLE 3.3O VER-C URRENT C IRCUIT (10)

T ABLE 4.1PCB M ATERIAL (11)

T ABLE 4.2USB3.0L AYOUT G UIDELINES (17)

T ABLE 4.3PCI E L AYOUT G UIDE FOR M OTHERBOARD T OPOLOGY (18)

T ABLE 4.4L AYOUT G UIDE FOR ON A DAPTER C ARD (19)

T ABLE 4.5PCI E CLOCK ROUTING GUILDES (20)

1.Introduction

This document provides a general design guideline for USB 3.0 host chips by Fresco Logic. The information described in this document is based on the lab experiments and the simulations. It is desirable that the specific topologies, stack-up, and other parameters to the particular design are taken into consideration. For a

complicated design, the simulation is required.

1.1USB

USB is a serial differential point-to-point interconnection. For more information on the USB standard, please refer to the Universal Serial Bus specification, at https://www.360docs.net/doc/bc14204059.html,.

1.2PCI Express

PCI Express Base Specification 2.0 and the PCI Express Card Electromechanical Specification, revision 2.0 can be found from the website: https://www.360docs.net/doc/bc14204059.html,. The PCI Express was designed to support 10 inches between

components with standard FR4.

2.Scope

This document provides guidelines for designing the layout and schematic of FL1100. The material covered can be separated two main categories: schematic guideline and layout guideline.

3.Schematic Guidelines

Acknowledge following guidelines for schematic design is important. This section includes notices of Power, PCIE, USB, Over-Current, Voltage Drop and others.

3.1Power

3.1.1Power Rail

Table 3.1 Power Rail

Description Typical Torrance Current

DVCC33Digital power 3.3V ±10%

DVCC10Digital power 1.05V ±5%

AVCC10Analog Power 1.05V ±5%

AVCC33Analog Power 3.3V ±5%

AVCC12Analog Power 1.2V ±5%

3.1.2Ripple Require

Table 3.2 Ripple Require

Power DVCC33DVCC10AVCC10AVCC33AVCC12 Ripple(p-p) 100mV 50mV 50mV 50mV 50mV

3.2PCIE

3.2.1PCIe Interface

Here are notices:

AC coupling capacitors are placed in the transmitter side of the PCI Express device on the add-in card. The AC coupling capacitors should be placed at the same location along the differential traces. The capacitance value is 0.1uF and its body size should be less than or equal to 0603 (0402 is best).

The PCIETXP/N pair of FL1100 shall be connected to the PCI Express receiver differential pair of the system board root IC or PCI Express edge of add-in card. The PCIERXP/N pair of FL1100 shall be connected to the PCI Express transmitter differential pair of the system board root IC or PCI Express edge of add-in card.

The “P” and “N” connections can be reversed for easy to layout and trace routing.

Add-in cards must strap PRSNT1n with PRSNT2n signal.

The resistor value of Pin “PCIEREXT” is 12K? (+/- 1%)

The capacitor value of Pin “PCIECAP” is 100nF.

Figure 3.1 PCIe Interface

3.3USB 3.0

3.3.1USB3 Interface

Here are notices:

The AC coupling capacitors is required on SSTX pair and should be placed close to the USB connector. The AC coupling capacitors should be placed at the same location along the differential traces. The capacitance value is 0.1uF and its body size should be less than or equal to 0603 (0402 is recommended).

The crystal specification is 12MHz ±30ppm.

Place a large capacitor (100uF/16V) for VBUS and need close to USB3 connector.

Figure 3.2 USB3 Interface 3.4Over-Current

3.4.1Over-Current Circuit

Figure 3.3 Over-Current Circuit

3.4.2Over-Current Action

Pin B28 “PPWRCTRL connect 4.7Kohm to GND to disable this function. (O) : Output pin from FL1100

(I) : Input pin of FL1100

Table 3.3 Over-Current Circuit

Over-Current Circuit Status IN OUT PPWR0/PPWR1/PPWR2/PPWR3

(O)

OVCN0/OVCN1/OVCN2/OVCN3

(I)

Enable Normal

Over-Current 5V

5V

5V

0V

High

Low

High

Low

Disable Don’t Care 5V 5V High / Low High 3.5Voltage Drop

3.5.1Worse-case Voltage Drop T opology

Figure 3.4 Worse-case Voltage Drop Topology

3.5.2Voltage Define

Normal voltage source is 5V ± 5% (4.75V to 5.25V)

Voltage supplied at connector (host) should be 4.45V to 5.25V

The maximum current is 900mA

The maximum drop voltage for connector is 27mV

The maximum drop voltage for cable is 171mV.

https://www.360docs.net/doc/bc14204059.html,yout Guideline

The following factors should be examined to determine whether or not the timing and signal quality requirements are both satisfied.

Pre-layout analysis:

Trace impedance

Shape of Vias and trace routes

Properties of connectors and cables

Post-layout analysis:

Eye patterns of all topologies

Crosstalk between circuit traces

4.1Key Considerations of High-speed PCB Design This section provides a design guideline based on the following key considerations:

1. Maintain the trace impedance (Differential and single-ended)

2. Avoid crosstalk into differential pairs from nearby signals

3. Minimize the skew between traces within a differential pair

4. Provide clean power for differential pair drivers and receivers

The references and requirements discussed in this document will help users understand what an effective design is. Some design details, such as the board size and component layout will depend on the restrictions, these references offer additional useful information on good design practices that are applicable to a general PCB design.

4.2Printed Circuit Board (PCB)

4.2.1Material

The typical board material is FR4. Table shows the characteristics of FR4. Please note that even though the same material may be used throughout a PCB, it is not necessarily uniform in its characteristics.

Table 4.1 PCB Material

Grade FR4

Permittivity dielectric constant,1 GHz 4.2 ~ 4.5

Dielectric tangent,1 GHz 0.021 ~ 0.025

4.2.2Stack up

FL1100 based system can be designed with a 4-layer board. The stack-up is in the sequence of component layer, ground layer, power layer and solder layer. Note that routing any signal on either power or ground layer is not permitted. Based on 5 mils trace width and 50Ω±10% trace impedance.

Figure 4.1 Stack up

4.2.3Characteristic Impedance

Stack up, trace width, and spacing between the traces of each pair should be determined in achieving differential impedance. Differential impedance can be calculated by using a 2-D field solver. However, it is strongly recommended to confirm the actual differential impedance with the board manufacturer.

The higher the single-ended impedance becomes, the narrower the gap spacing between a pair of traces must be to meet the desired differential impedance. This leads to an increased coupling intensity and higher density of routing a pair of traces. The impedance control for a high single-ended impedance becomes more difficult.

4.3General Routing and Placement Routing Rules

Following general routing and placement guidelines when laying out a new design can help to minimize EMI problems and improve signal integrity.

1. Route differential pairs first with the minimum trace lengths. Maintain the maximum possible distance

between the high-speed clocks/periodic signals to differential pairs and any connector leaving the PCB

(i.e., I/O connectors, control and signal headers, or power connectors).

2. Differential pairs should be referred to a complete plane.

3. Route differential pairs without Via and corners as possible to reduces reflections and impedance issue

4. Do not route differential pairs traces under crystals, oscillators, clock synthesizers, magnetic devices, or

ICs that use and/or duplicate clocks.

5. Keep the differential pair signals clear of the core logic set. High current transients are produced during

internal state transitions and may be very difficult to filter out.

6. The edge-to-edge spacing of adjacent pairs should be at least greater than 40 mils or 2.5 times of h. The

traces of differential pair should be at least 20 mils away from the edges of the GND plane (trace) and Via.

And at least 50mils away from the high speed signal, clock, signal traces or Power trace.

Figure 4.2 Differential Pair Routing Diagram

7. Length matching among differential pairs.

The total trace skew should be less than 5 mils (Recommended value) among differential pairs. The skew between the bonding wires inside the package also affects the total skew, as does skew between the PCB traces. When designing the differential PCB traces, users should take the differences of lengths at the bonding wires into consideration.

8. Stubs on the high-speed USB signals should be avoided, as stubs will cause the signal reflections and

affect the signal integrity.

9. When it is necessary to turn 90°, use two 45° tu rns or round bend to instead of making a single 90° turn.

This reduces reflections on the signal by minimizing the impedance discontinuities.

Figure 4.3 Trace Bend

10. The differential pair traces and clock signal must be kept in outer layer, and must have a continual full

ground plane at neighboring layer for reference, with no interruptions. A differential pair should avoid discontinuation in the reference plane, such as splits and voids. Crossing over splits plane increases inductance and radiation levels by forcing a greater loop area.

Figure 4.4 Continuous Reference Ground Plane

Figure 4.5 Avoid Discontinuation Reference Plane

11. Likewise, avoid changing layers with USB differential pair traces as much as practical. When a signal

needs to change layers, it must keep the same reference plane and the ground stitching via should be

placed close by the signal via. A minimum of 2 stitching via per pair of signals is recommended. Please do not route a trace result that it straddles a place split.

Figure 4.6 Ground Island for Change Layer

12. The routing of a differential pair must be kept as same length; same width, same layer and fixed space

gap, and please keep as symmetric as possible. When vias are used, they should always be placed in the same location and be symmetric to each other.

Figure 4.7 Differential Trace and via Symmetric Routing

13. Separate signal traces into similar categories and route similar signal traces together (Such as routing

differential pairs together).

14. Recommended spacing rule between traces of adjacent pairs:

The differential pair needs to keep the width 2.5 times distance or at least 20 mils to other signal.

15. AC coupling capacitors need to be symmetric placement, which is recommended.

Figure 4.8 AC Coupling Capacitor Placement

16. The wiring around the oscillator shall be wrapped with GND, since it might interfere with other signals. As

for the oscillator wiring, both wires should be parallel and symmetric, allowing better oscillation undulation and EMI effects.

17. The DP/DM must use symmetric routing to keep its impedance.

Figure 4.9 USB2.0 Differential Pair Routing

4.4Power Integrity

4.4.1Decoupling Recommendation

This section describes the preliminary decoupling recommendations for USB 3.0 power. Please note that the recommendations provide the total minimum capacitance of each voltage plane. The recommended decoupling capacitance, ESR and ESL, of each voltage plane is the minimum aggregate value that can be achieved by adding multiple decoupling capacitors in parallel.

Each decoupling capacitor should be placed with a one or two Vias to a voltage plane (Or plane fill area) and solid ground plane, so that the copper loss and inductance between the capacitor and nearby ball Via are negligible. Distribute the capacitors so that the entire power ball Via have decoupled nearby. It is recommended that the distance from the ball Via to decoupling be minimized.

4.4.2Power Routing Rules

Allow the minimum spacing of 20 mils between the power trace and other signal traces or GND.

Sensitive signal traces should not stride over the split needed for power-island separation.

Place the bypass capacitors as close to the USB chip as possible for every pair of VDD and VSS pins

The Via form power plane to bypass capacitor is located close to the bypass capacitor.

Place the bulk capacitor near the power source.

4.5Layout Guidelines

4.5.1USB 3.0 Layout Guidelines

Table 4.2 USB 3.0 Layout Guidelines

Parameter Routing Guideline Comment

Differential signal group 1. SSTX+/-

2. SSRX+/-

3. D+/-

Reference plane Routing over an unbroken ground plane is preferred. If an unbroken

ground plane is not available, route over an unbroken voltage plane. Characteristic trace

impedance

Differential mode: 90 ? nominal ±10%

Differential pair spacing Spacing from other groups or signal > 40 mil or 2.5 times for the

minimum pair width from edge to edge

Pair width is (Trace +

Space + Trace)

Total length Back Panel (Differential trace) 6 inch within 4 vias

7 inch within 3 vias

8 inch within 2 vias

9 inch within 1 vias

< 10 inch (Max.) without any via

IC pad to USB

connector through hold

Total length Front Panel (Differential trace) 3 inch within 2 vias

4 inch within 1 vias

IC pad to USB 19-pin

connector through hold

and with 52cm Cable

Length matching requirement Total allowable among a pair (Length skew between + and - signals of the pair) is 5 mils.

AVCC13SA, AVCC13SB Capacitance of 3.3 μF with low

Equivalent Series Resistance (ESR) is

Parameter Routing Guideline Comment

required

The max route length is ≧150 mils

with one via.

Trace width is 5 mils.

AC Coupling AC coupling capacitors must be

located at the transmitter side.

Capacitance of 0.1 μF with low

Equivalent Series Inductance (ESL) is

recommended

Place AC coupling capacitors as close

as possible to the chip. The second

option is to place the AC coupling

capacitors as close as possible to the

USB connector.

4.5.2PCIe Routing Guide on Motherboard

Table 4.3 PCIe Layout Guide for Motherboard Topology

Parameter Routing Guide

Reference plane Routing over the unbroken ground plane is preferred. If unbroken ground plane is not available, routing over the unbroken voltage plane.

Characteristic trace impedance Single-ended: 50 ? ± 15% Differential: 85 ? nominal ±15%

Microstrip trace width 5 mils

Microstrip trace spacing Between edge-to-edge intra-pair (Between + (P) and - (N) pair): 8.75 mils (Please refer to

Note 2)

Between other pairs: > 25 mils edge to edge

Transmit and receive pairs should be interleaved. If interleaving is not possible, then the

spacing between inter-pairs should be increased to > 45 mils from edge to edge. The

edge-to-edge inter-pair is defined from the positive edge of one pair to the negative edge of

next pair, or vice versa

Stripline trace width 5 mils

Stripline trace spacing Between + (P) and - (N) of pair: 8.75 mils, edge to edge

Between other pairs: > 25 mils, edge to edge

Transmit and receive pair should be interleaved. If interleaving is not possible, then the inter

pair spacing should be increased to 45 mils from edge to edge.

The edge-to-edge inter-pair is defined form the positive edge of one pair to the negative edge

of next pair, or vice versa

Group spacing Minimum edge-to-edge spacing from other groups: > 25 mils

AC coupling The AC coupling capacitors must be located at the transmitter. The required value range is from 75 nF to 200 nF.

Total trace length 1.0” (Min.) ~ 14.0” (Max.)

For transmitter and receiver. The define of trace length is from the device signal pin to the AC

coupling capacitor and from the AC coupling capacitor to the PCI Express device pin

Length Matching Requirements Total allowable between pair (Length skew between + and - signals of a pair) length mismatch on a system board must not exceed 25 mils.

Length should be matched on a segment-by-segment basis.

Each routing segment to be matched should be as close as possible.

Total skew across all lanes must be less than 20 ns.

Number of vias 4 (Max.)

4.5.3PCIe Routing Guide on Adapter Card

Table 4.4 Layout Guide for on Adapter Card

Parameter Routing Guide

Reference plane Routing over unbroken ground plane is preferred. If unbroken ground plane is not available, route over unbroken voltage plane.

Characteristic trace impedance adapter card Single-ended: 50 ? ± 15% Differential: 85 ? nominal ±15%

Microstrip trace width 5 mils(Please refer to Note2)

Microstrip trace spacing Intra pair: 8.75 mils edge to edge (Please refer to Note1)

Between other pairs > 25 mils edge to edge

Transmit and receive pair should be interleaved. If interleaving is not possible, the inter pair

spacing should be increased to 50 mils from center to center. The center-to-center inter-pair is

defined from the positive center of one pair to the negative center of next pair, or vice versa. Group spacing Spacing from other groups: > 25 mils

Minimum spacing from edge to edge

Trace length of received

differential pair

1.0” (Min.) ~ 14” (Max.)

Trace length from the

device signal ball to the

AC coupling capacitor of

the transmit differential

pair

0.25” (Min.) ~ 4” (Max.)

Trace length MB2 from

the AC coupling

capacitor to the

connector pins

1.0” (Min.) ~ 10.0” (Max.)

Length of matching requirements Total allowable between pair (Length skew between + and - signals of a pair) length mismatch on a system board must not exceed 60

mils.

Length should be matched on a segment-by-segment basis.

Each routing segment to be matched should be as close as possible.

Number of vias 4 vias per signal between the device package ball and the connector

pin

Reducing the number of vias

Impedance controlled vias (85 ±15%) preferred

4.5.4PCIe Clock Routing Guides