[DC]逻辑综合

Logic Synthesis Review Material

For 10-1,2,3,4

2012-12 1．Key Iterm 重点项目

1.Synthesis（综合）

Synthesis is the transformation of an idea into a manufacturable device to carry out an intend function.

2.Hold time(维持时间),

3.wire load model(线负载模型6.15）,

A wire load model is an estimate of a net's RC parasitics based on the net's fanout:

`Model is created by your vendor

`Estimates are based on statistics form other designs the vendor has fabricated using this process

4.Constraint（约束）

5.Critical path（关键路径）

6.Clock skew（时间偏移）

7.Jitter（抖动）

8.STA（静态时序分析）

Design Compiler uses Static Timing Analysis(STA) to calculate the timing of paths in the design,

Static Timing Analysis can determine if a circuit meets timing constraints without dynamic simulation .

This involves three main steps:

*Design is broken down into sets of timing paths

*The dely of each path is calculated

*All path delays are checked to see if timing constraints have been met.

9.Setup time准备时间建立时间;

10.TCL工具命令语言,

11.BDD行为驱动开发;

12.SOLD, Timing path时序路径8.8,

13.PVT，Operating condition6——11

2．Explanation 解释说明

1.Synthesis=?+?+?

Synthesis=Translation+Optimization+Mapping

2.design object

Module TOP (A,B,C,D,CLK,OUT1);

Input A,B,C,D,CLK;

Output [1:0] OUT1;

Wire INV1,INV0,bus1,bus0;

ENCODER U1 (.AIN(A),.....Q1(bus1));

INV U2(.A(BUS0),.Z(INV0)),

U3(.A(BUS1),.Z(INV1)),

REGFILE U4 (.D0(INV0),.D1(INV1),.CLK(CLK));

endmodule

3.levels of circuit abstraction(抽象),

Idea-Functional-Behavioral-Register Transfer-Gate Level-Physical Device

4.Synopsys_dc.setup,

5.Libraries in the file Synopsys_dc.setup,

6.3 to 8 decoders(3-8译码器);

7.writing verilog code;

8.HDL Synthesis Process

3. True or False

1). The following two always blocks will be synthesized to the same circuit:

always @(d or r1 or r2) begin

r1 = d;

r2 = r1;

end

always @(d or r1 or r2) begin

r2 = r1;

r1 = d;

end

2). The following two always blocks will be synthesized to the same circuit:

always @(posedge clock) begin

r1 = d;

r2 = r1;

end

always @(posedge clock) begin

r2 = r1;

r1 = d;

end

3). The following two always blocks will be synthesized to the same circuit:

always @(posedge clock) begin

r1 <= d;

r2 <= r1;

end

always @(posedge clock) begin

r2 <= r1;

r1 <= d;

End

4.Given the following Verilog HDL code, draw a gate level

synthesized schematics

1).

module mycode (clock, r1, r2);

input clock;

output r1, r2;

reg r1, r2;

always @(posedge clock) begin r1 <= r2;

r2 <= r1;

end

endmodule

2).

module p1 (a, b, x);

input a, b;

output x; reg x;

always @(a or b) begin

if (a)

x = b;

end

endmodule

3).

module p2 (a, b, x);

input a, b;

output x; reg x;

always @(a or b) begin

x = func(a, b);

end

function func;

input a, b;

if (a)

func = b;

endfunction

endmodule

4).

module AOI(A,B,C,D,F); //)

input A,B,C,D; //

output F; //

wire A,B,C,D,F; //

assign F= ~((A&B)|(C&D)); //

endmodule

5).

module count(out,data,load,reset,clk);

output[7:0] out;

input[7:0] data;

input load,clk,reset;

reg[7:0] out;

always @(posedge clk) //clk 上升沿触发begin

if (!reset) out = 8'h00; //同步清0，低电平有效else if (load) out = data; //同步预置

else out = out + 1; //计数

end

endmodule

6).

module mux4_1d(out,in1,in2,in3,in4,cntrl1,cntrl2); output out;

input in1,in2,in3,in4,cntrl1,cntrl2;

assign out=cntrl1 ? (cntrl2 ? in4:in3):(cntrl2 ? in2:in1); endmodule