Design of current limiting circuit in low dropout linear voltage regulator
Design of Current Limiting Circuit in Low Dropout Linear Voltage Regulator
LIN Chuan, FENG Quan-yuan
Microelectronics Institute, Southwest Jiaotong University, Chengdu, 610031, China
Email: lin_langai@https://www.360docs.net/doc/7d6420597.html,; TEL: 028-********, 028-********
Abstract- A current limiting circuit applied in low dropout linear voltage regulator is designed and simulated. It can limit the maximum output current and the output short current of the regulator within 320mA and 30mA, respectively, and well realize the purpose of overcurrent protection. Prototype of the circuit can be fabricated using the 0.5μm CMOS process.
Index Term s- Current Limiting; Foldback; LDO; Linear Voltage Regulator
1. I NTRODUCTION
Nowadays, LDO (Low Drop-out) linear voltage regulator has been widely used in portable equipments.In order to prevent damage to the IC when an overload is placed or the output of the regulator is shorted, current limiting circuits are usually included in LDO linear voltage regulator [1~3].So far, there are few papers published about the design of current limiting circuit, especially foldback current limiting circuits in LDO linear voltage regulator. It is, however, discussed in many patents [4~5].A current limiting circuit used in LDO linear voltage regulator is designed and simulated in this paper. This circuit can be fabricated using 0.5μm CMOS process and can be easily adjusted. The simulation results show that the circuit can well realize the purpose of overcurrent protection. It can limit the maximum rated output current and the output short current within 320mA and 30mA, respectively.
2. D ESIGN OF CURRENT LIMITING CIRCUIT
2.1 Design Requirement of Current Limiting Circuit
A current limiting circuit used in LDO linear voltage regulator should at least meet the requirements as follows:
This work was supported by National Science Foundation of P. R. China. Grant No. 603710171.When overcurrent hasn’t taken place, the voltage
regulator should regulate the output voltage U O normally, and the current limiting circuit should have little effect on it.
2. A current limiting circuit should first include output
current detecting devices or block to detect if output current I O has exceeded the maximum rated value.
3.After the current limiting circuit starts up, it should cut
off the negative feedback loop of the regulator. Then the regulator cannot regulate the output voltage any more.
4.After foldback current limiting circuit starts up, I O will
decrease as U O decreases. As the output is shorted, I O will be limited to a value much less than the maximum rated value.
Besides, a good current limiting circuit should take some other factors into consideration, such as: low quiescent current and power consumption, few devices, low cost, and so on.
2.2 Design Principle of Current Limiting Circuit
The current limiting circuit presented in the paper is showed in Fig. 1. It comprises output current sampling circuit, constant current limiting circuit and foldback current limiting circuit. Signals VB1 and VB2 are generated by the self-biasing circuit of the error amplifier (We only give the second stage of the amplifier in Fig. 1). The potential of VB2 is constant, and V SG_MP3＝VDD－VB1 holds constant as well. MN1 and MP2 make up of the second stage of the error amplifier.AO1 is its input as well as the output of the first stage and AMP_OUT is its output as well as the output of the error amplifier. MPW is pass element. LCE is the enable control signal. When it is at high potential, MP1 is off and the circuit works normally.
0-7803-9433-X/05/$20.00 ?2005 IEEE. APMC2005 Proceedings
Fig 1 A current limiting circuit in a LDO linear voltage regulator
2.2.1 Output Current Sampling Circuit
Output current I O is sampled by MP5, whose source and gate are connected with source and gate of the pass element, respectively. In addition, we have V D_MP5=V SG_MP7+V OUT . If the W/L rate of MP7 is designed to be quite large, then V SG_MP7≈V th_MP7，and less difference of V D_MP5 and V OUT will reduce the effect of channel modulation and enable MP5 to sample output current accurately. The relation of the sampling current I S and I O is as follows:
5
(/)(/)S MP O MPW
I W L I W L = (1) Therefore, if we make the rate of W/L of MP5 very small, we
can obtain a small current I S which is proportional to I O . 2.2.2 Constant Current Limiting Circuit
Suppose when the output current is at its maximal rated value, the corresponding V G_MN2 is V 0G_MN2 and the sampling current is I 0S . MN2 and MP3 compose an inverting amplifier, whose input and output are the gate of MN2 and INVO, respectively. When output current is under maximal rated value, sampling current I S < I 0S , V G_MN2< V 0G_MN2. At this time, INVO is at high potential and MP4 is off, so constant current limiting circuit has no control on the gate of the pass element. When the output current exceeds the maximal rated value, I S > I 0S , V G_MN2> V 0G_MN2, INVO is at relatively low potential, and MP4 is on, which lifts V AMP_OUT up and hence reduces output current I O . So I O is limited to a constant value. As load resistor
decreases, U O drops, and the sampling voltage fed from the output to the error amplifier is less than the reference voltage any more. Thus the output of the first stage of the amplifier AO1 is at high potential, and MP2 is cut off, so the negative feedback in the linear voltage regulator is cut off and the regulator cannot regulate the output normally any longer. 2.2.3 Foldback Current Limiting Circuit
According to the relationship of output current I D and V GS of a MOS transistor, we have:
_4_321/23_323I 2I (I GS MN GS MN S O S MN th MN S O
ox MN V V R U L
V R U C W μ=
+?=++? (2) Make
5
10I (/)I (/)S M P M P W
W L k W L =
=,1/213232(
MN ox MN k L k C W μ= and we get ：
1/2_42_312I I GS MN O th MN O O V k V k R U =++? (3)
1/2_42_312I I GS MN O th MN O L O V k V k R R I =++? (4)
If MN4 is on, as V GS_MN4 increases, I MN4 and V SG_MP6= I MN4R 1 will increase as well. If MP6 is on, V AMP_OUT will be lifted up, which causes I O to decrease. So I O is a degressive function of V GS_MN4 as long as MN4 and MP6 are on. It can be simply expressed as:
_6_4_4()()()O SG MP GS MN GS MN I f V f g V h V ===o (5)
When output current is under its maximal rated value, V GS_MN4< V TH_MN4, MN4 is off, I MN4=0, V G_MP6=VDD, so MP6 is off and foldback current limiting circuit has no control on the gate of the pass element. When overcurrent takes place, constant current limiting circuit works first and limits I O to a constant value. As load R L decreases, U O will also decrease. From equation (3), we know that MN4 will become on when U O drops to some value, and as U O drops further, I MN4 will increase further. When V SG_MP6= I MN4R 1> V TH_MP6, MP6 is on, then foldback current limiting circuit starts to work and lifts V AMP_OUT up, which causes I O to decrease. Then INVO is at high potential and MP4 is off again. If R L decreases further, according to equation (4), V GS_MN4 will increase and cause I O to decrease. And at last, equation (4) and (5) will be in balance. In a word, I O will decrease as R L and U O decreases, so we achieve the purpose of foldback current limiting. When the output is shorted, the value of I O is minimal.
3. S IMULA TION RESULTS AND DISCUSSION
The designed current limiting circuit is applied in a LDO linear voltage regulator, for which the regulated output voltage is 1.8V , the maximal rated value of I O is 320mA and the output short current is 30mA. The simulation results by HSPICE are showed in Fig. 2 and Fig. 3.
Fig. 2 The relationship of output voltage and output current
Fig. 3 The relationship of quiescent current and output current
Fig. 2 shows the relationship of U O and I O in LDO linear regulator. From Fig. 2, we can see that when overcurrent takes place, constant current limiting circuit works first and limits I O to 320mA. Then U O drops as R L decreases. As U O drops to about 1.4V , foldback current limiting circuit starts up and reduces I O further. The short output current is 30mA. Fig. 3 shows the relationship of quiescent current I q of the current limiting circuit and output current I O . The circuit has only two current limbs which are both proportional to sampling current I S . So very low I q which is proportional to I O is achieved. We can see from Fig. 3 that I q is less than 8.5μA when I O is less than 200mA. Besides, the circuit has some extra advantages as follows:
1. Few devices and low cost. The current limiting circuit
comprises only 8 MOS transistor and 2 resistors, which can reduce the size of the chip and hence reduce the cost.
2. The circuit is easy to adjust. By adjusting W/L rate of
MN2, MN3 and MP3, the maximal rated output current can be adjusted; by adjusting W/L rate of MN3, MN4, MP6 and R1, R2, output short current can be easily adjusted.
4. C ONCLUSION
The circuit designed in the paper has solved some critical techniques in current limiting circuit. When used in a LDO linear regulator, it can well realize the purpose of overcurrent protection.
R EFERENCES
[1] Bang S. Lee, “Understanding the Terms and Definitions of LDO Voltage Regulators,” Texas Instruments Application Report ，Oct. 1999
[2] Bang S. Lee, “Technical Review of Low Dropout Voltage Regulator Operation and Performance,” Texas Instruments Application Report，Aug. 1999
[3] Chester Simpson, “Linear and Switching Voltage Regulator Fundamentals,” National Semiconductor Application Note. 1999
[4] Wen Li Luo, “Current Limit Protection Circuit for a Voltage Regulator,” United States Patent, 6466422 B2, Oct.15, 2002
[5] Robert M. Paterno. “Booster circuit for foldback current limited power supplies,” United States Patent, 5994884, Nov.30, 1999