LTPS tech introduce

LTPS Process Issue IntroductionNT/INTK.H. ChenK H ChIntroduction Advantages of LTPS TFT-LCD•Devices–high TFT’s mobility •Peripheral Driving Circuits–stability–light/heat insensitive –self-scanning –data line driver–CMOS devices–reduction in feature size–few bonding pad •Displaysp y–high pixel density oraperture ratio–lower dynamic voltageshiftLTPS R i tLTPS Requirement★High mobility★Low V th-------NMOS ~ 2V; PMOS ~ -2V ★Low I off-------< 10 pA★Uniform V th---------±0.2V ~ 0.3V★Stability & reliability of V th★Process with stability & uniformity & repeatableC i LTPS ith Si Comparison LTPS with a-SiAmorphous -Si vs. Poly-SiGlass substrateElectron mobility is more thanGlass substrateandElectron mobility100X greaterSmall grain structure, randomly configuredLarge and more uniform grain structurePeripheral Circuits on Array1. Buffer-Layer/ a-Si Precursor2. Dehydrogenation 1.P31for N-TFT Channel Doping(Mask 2)P--P--P--P--1.B11doping of P-TFT channeld i1.Gate oxide dep. & Gate metaldep. & pattern (Mask 3)B--B--B--B--doping 2. Densification/Hydrogenation1.ELA crystallization1.P31for N-TFT LDD Doping (Blanket by GateSelf Alignment)P-P-P-P-1Pol island pattern(Mask11.P31for N-TFT S/D Doping1.Poly-island pattern (Mask 1)(Mask 4)P+P+P+P+1.B11for P-TFT S/D doping ofMask51.Passivation (SiOx / SiNx/PC403) deposition & pattern (Mask 8)(Mask 5)2. ActivationB+B+B+B+1.interlayer deposition 1ITO deposition&pattern(Mask92.via hole (Mask 6)1.ITO deposition & pattern (Mask 9) 1.S/D deposition & pattern ( Mask 7)LTPS Process Flow (precursor layer demand)1. Undercoat Material (Buffer -Layer)A K ISID 99 p-2 “Back-Channel Effects on the ThresholdVoltage of Low-Temperature Poly-Si TFTs with SiNx/SiO2D l U d L "T hib LCD R&D C tA. Key Issue:1.Block Na Diffusion From Glass Substrate: SiNx Better than SiO 2Dual Under Layer" Toshiba LCD R&D Center 2.Threshold Voltage(V th ) Requirement : SiO 2Better Than SiNx(1500nm)/precursor -Si(50nm)Poly-Si SiNx(50nm)/SiO 2(1500 nm)/precursor αSi(50nm)SiNxSiO 2GlassPurpose:SiN/SiOx double layers block up LTPS Process Flow (precursor layer demand)y p sodium penetration from glass substrateBuffer layer thickness ?Could inhibit Buffer layer thickness ? Could inhibit ion (B; Na;K)from glass substrateThe fixed charges in PECVD-SiOx of buffer layer affected Vth significantly. Impurities nitrogen in the SiOx caused h Th d ti f th it charges. The reduction of the nitrogen could stabilize Vth affected by the fluctuations of deposition conditions.Ref: SID 1999 p.456E cimer Laser Annealing The Process LTPS Process Flow (Re -crystallize)Excimer Laser Annealing: The Process• A line-shaped andhomogenized excimer laser homogenized excimer laser beam is scanned across the surface •The excimer light is very efficiently absorbed in a thin ya-Si surface layer without heating and damaging the underlying substrate underlying substrate •Within the laser pulse duration th Si l i idl h t d the a-Si layer is rapidly heated and melted. As it cools down the re-crystallization into p-Si occursB P fil f A liBeam Profile for TFT Annealing Beam Profile for TFT Annealing •Line Beam OpticsOptics•Long Axis: Top Hat Profile •Short Axis:Nearly GaußShort Axis: Nearly GaußProfile•Inhomogenity afterTransformation:<5%(2Transformation: < 5% (2σ)i L A li Th PE cimer Laser Annealing The Process Excimer Laser Annealing: The Process •Advantages:•Inexpensive glass instead of quartz dueto no thermal effects on the Variable panel size•High throughput due to high power excimer lasers E !excimer lasers•High electron mobility•Laser requirements ⇒Economy!q•The ELA process stringent demands onlaser performance P l t bilit•Pulse energy stability •Homogeneity of the applied laser light •Highest reliabilityHighest reliabilitya-Si precursor thicknessSi precursor thickness 影響?a-Si 太薄則ELA時熱散太快. a-Si 太厚則ELA時上下熔化會不均--------good uniformity of a-Si filmRef:JAP861999p5556Ref: JAP,86, 1999 p.5556 Ref: IDW97, 1997 p.231(Sanyo)S rface Ro ghness Iss eSurface Roughness Issuef R h IB.The Relationship between TFT Characteristics and Interface Roughnessby SimulationAMLCD 99 TFT4-1 “Device Simulation of Interface roughnessy pin Laser Crystallized p-Si TFTs”SEIKO-EPSONInterface Roughnessg yId degradation was more sensitive by H variation.g gReduce roughness using HF treatmenteduce oug ess us e e Ref: SID 00’ p.534i t f b t Si d SiOinterface between Si and SiOx NMOS:Vt=V fb + φsi + φox = V fb + 2φB + Q B /C oxVt = V fb + 2φB +(2εsi qN A 2φB )1/2/C ox Vt = V fb + ( 1+ 6 t ox / W d )2φB = V fb + ( 1 + 2C si /C ox ) 2φBPMOS:Vt=V fb + φsi + φox = V fb + 2φB -Q B /C oxVt =+2Vt = V fb + 2φB -(2εsi qN A 2φB )1/2/C ox Vt = V fb + ( 1+ 6 t ox / W d )2φB = V fb + ( 1 + 2C si /C ox ) 2φB=V fb φms -Q ox /C oxLow charge &low flat-band voltage shift Oxide film Ref: SID 1999 p.172(Toshiba)Low charge & low flat-band voltage shift Oxide filmSSM C V D S l R ltSSM C -V Demo Sample Result HF C-V ComparisonfterH pF orw ardC -VA fter H eatu p F ard CV 1.2D O E0.81D OE +An n ea l ST DC lea n + STD 1. The Positive C-V CurveShift for Anneal Sample.(Reduce Oxide Charge Neff 040.6C /C 0ST D +A n n e al(Reduce Oxide Charge Neff,Interface Charge Dit) 2. Sample Clean before 0.20.4Oxide Deposition Show better Vfb Characteristics than Standard Sample.0-40-30-20-100102030V gLTPS Process Flow (Interface Treatment)Device Anneal ProcessSample C4 W/L = 10/6< 450C Anneal1.00E-051.00E-041.00E-071.00E-0600051.00E-091.00E-08I d1.00E-111.00E-10Before Ann eal1.00E-131.00E-12Before Ann After 1'st Ann eal After 2'nd Ann eal-20-15-10-55101520253035VgDevice Anneal Process in CVDLTPS Process Flow (Interface Treatment)Device Anneal Process in CVD l Vt Improvement by AnnealMobility Improvement by AnnealA n n e a l 前後比較12B efo re A n n e al A fte r 1'st A n n e a l r2'n dA n n ea lA n n e a l 前後比較160180B e fore A n n e a l A fte r 1's t A n n e a l A fte r 2'n d A n n e al810eA fte r 2n d A 1201406T h r e s h o l d V o l t a g 80100M o b i l i t y242040600W /L = 10/2W /L = 10/3W /L = 10/4W /L = 10/5W /L = 10/6W /L = 10/10W /L = 10/20W /L = 10/50W /L = 4/6W /L = 6/6W /L = 10/6W /L = 50/6W /L = 100/6W /L = 500/60W /L = 10/2W /L = 10/3W /L = 10/4W /L = 10/5W /L = 10/6W /L = 10/10W /L = 10/20W /L = 10/50W /L = 4/6W /L = 6/6W /L = 10/6W /L = 50/6W /L = 100/6W /L = 500/6D e v ic e S iz e D e v ic e S iz eSSM C -V Demo Sample Result LTPS Process Flow (Interface Treatment)SSM C -V Demo Sample ResultV Demo Sample Result Q_V Result Dit v.s. En ergy Band GapDOE 100E+151.00E+16DOE+Anneal STD STD+An neal1.00E+141.00E+151.00E+13D i t1.00E+111.00E+12-0.200.000.200.400.600.80 1.00E(eV)Ev EcFrom the QV result, the Dit v.s. Ev show very high interface trap of our sample in mid-gap and near conduction band,but all measurement stop before conduction band energy(Ec = 1.13eV), did this due to measurement limit,or sample condition.and why sample #6(STD) Dit distribution will under valence band(all sample stop at Ev = 0)?LTPS Process Flow (Interface Treatment)K 7 S a m p le A fte r F in a l A n n e a lSam ple C41.00E-03DOE Oxide Sample STD Oxide Sample 1.00E -051.00E -041.00E-051.00E-04100E081.00E -071.00E -06100E 081.00E-071.00E-061.00E -101.00E -091.0E -0I d 1.00E-101.00E-091.00E-08I d1.00E -121.00E -11W /L = 4/6W /L = 10/101.00E-121.00E-11W /L = 4/6W /L = 10/101.00E -13-20-1010203040V g1.00E-13-20-1010203040V gSample K5 : ELA + NH3Treatment + Oxide Dep. + N2/H2 Treatment Sample K6 : ELA + N2O Treatment + Oxide Dep. + N2/H2 Treatment.S l K5S l K5Sample K8 : ELA + Oxide Dep.(Without any Treatment)W/L = 4/6 Vg = 15V Vd=Vs=0V Stress 88.5Sample K5Sample K6Sample K8W/L = 10/10 Vg = 15V Vd=Vs=0V Stress 859Sam ple K5Sam ple K6Sam ple K86.577.5t6577.588.5t4555.56V 4555.566.5V 44.5025050075010001250Stress Time (s)44.5025050075010001250Stress Time (s)()Stress Time (s)The device owned the better performance by NH3 pre-oxide treatment.S l K5S l K5W/L = 4/6 Vg = 15V Vd=Vs=0V Stress2.5Sample K5Sample K6Sample K8W/L = 10/10 Vg = 15V Vd=Vs=0V Stress2.5Sam ple K5Sam ple K6Sam ple K81.52S1.52S0.51S 0.51S 0025050075010001250Stress Time (s)0025050075010001250Stress Time (s)Stress Time (s)Stress Time (s)100E 04100E-1.00E-051.E-pre gate oxidespecial cleaning1.00E-081.00E-071.E 06E8-4c K8-5b Id p g 1.00E-101.00E-09E8-6d E8-9b E8-7ad(A)w/o pre gate oxidecleaning1.00E-121.00E-11Lower Ioff1.00E-13-20-1010203040Vg(V)(i)It has lower Ioff.(ii)Chemical oxide that undergo manyprocess has negative effect on Vt process has negative effect on Vt and mobility.Th ff t f h Vt d bilitW /L=10/3•Rms,center : 67ÅThe effect of roughness on Vt and mobility 16.114.2 6.110.412.619.05.9 5.3 6.111.113.611.05.4 5.9 5.210.011.012.3Rms, edge : 78Å•The difference of roughness on center Å6.9 4.0 5.010.211.313.55.3 5.7 4.810.810.312.16.6 4.85.38.78.912.1and edge is roughly 11Å, it doesn’t affect the Vt and mobility.W /L =10/3168180695469405139V 1V 216.818.069.546.940.513.941.164.970.152.746.948.762.063.779.357.952.146.334.250.476.555.654.441.7V 3V 46.5 -7.06.0 -6.5 5.5 -6.0 5.0 -5.54.5 -5.0 4.0 -4.570.773.681.755.057.948.163.766.080.560.862.649.8H 1H 2H 3V 5V 6With Cl With t Cl With Clean Without CleanI i l t ti ditiLTPS Process Flow (Ion Implantation)t ho x i d eb esu .S u Ion implantation condition:h r o u g h o a r e su b . S r fac eS /D P ( 5E 14 ~5E 15/ c m 3)40~80 k e v10~20 k e v (5145E 15/c 3)0k 10k e v B ( 5E ~/ c m 20~40 k e v 5~0 k L D D P (5E 12~5E 13/c m 3)40~80 k e v 10~20 k e v C h a n n e l B (2E 11~1E 12/c m 3)20~40 k e v5~10 k e vRef: Mistui dataActivation method The optimum doseActivation method @ Oven/ Furnace @RTP The optimum dose content is different foreach activation method@ RTP @ ELAn +/ p +& LDD sheet resistancen + / p +p-Si sheet resistance ≦2 k Ω/ □affected by activation Ref: Ion Implantation Technology, 2000 p.316(Sanyo)Ref: AMLCD 98( 1998 ),p5 (Toshiba)LDD sheet resistance: 6E4 ≦LDD ≦1E5 Ω/ □activation methodCurrentVG VS V DR R c cIgnore the Rc effect:Id ∝(LS ρsource+Lρchannel+LDρdrain)-1×VDSLet LS = LD= LN; ρsource= ρdrain= ρNId ∝{L[2(LN /L)ρN+ ρchannel]} -1×VDS8 μm Change distance fromvia to S/D metal edge8 μm3 μmN-TFT in L-1N-TFT in L-1 N TFT in L1Ch l R i t St dChannel Resistance StudyAMLCDs ‘95 “Electrical Performanceof Top-Gate Amorphous Silicon TFT”f T G t A h Sili TFT”the intersection of the extrapolatedline at different Vg give us total seriesline at different Vg give us total seriesresistance Rs.Channel Resistance Study Channel Resistance StudyRs =~ 200K ΩIoff current in LTPSI ff t i LTPSDosing range and length will be the y p g y pkey parameter for lightly dopedrain(LDD) process。