CY7C1361C-117BGC中文资料
CY7C1412AV18中文资料
PRELIMINARY36-Mbit QDR-II™ SRAM 2-WordBurst ArchitectureCY7C1425AV18CY7C1412AV18CY7C1414AV18Features•Separate Independent Read and Write data ports —Supports concurrent transactions •200-MHz clock for high bandwidth •2-Word Burst on all accesses•Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 400 MHz) @ 200 MHz •Two input clocks (K and K) for precise DDR timing —SRAM uses rising edges only•Two output clocks (C and C) accounts for clock skew and flight time mismatching•Echo clocks (CQ and CQ) simplify data capture in high-speed systems•Single multiplexed address input bus latches address inputs for both Read and Write ports •Separate Port Selects for depth expansion •Synchronous internally self-timed writes •Available in x8, x9, x18, and x36 configurations •Full data coherency, providing most current data •CoreV DD = 1.8V (±0.1V); I/O V DDQ = 1.4V to V DD•15 × 17 × 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix)•Variable drive HSTL output buffers •JTAG 1149.1 compatible test access port•Delay Lock Loop (DLL) for accurate data placementConfigurationsCY7C1410AV18 – 4M x 8CY7C1425AV18 – 4M x 9CY7C1412AV18 – 2M x 18CY7C1414AV18 – 1M x 36Functional DescriptionThe CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array.The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1410AV18) or 9-bit words (CY7C1425AV18) or 18-bit words (CY7C1412AV18) or 36-bit words (CY7C1414AV18)that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.”Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.Selection Guide250 MHz200 MHz 167 MHz Unit Maximum Operating Frequency 250200167MHz Maximum Operating CurrentTBDTBDTBDmAShaded areas contain advance information.Please contact your local Cypress Sales representative for availability of these parts.PRELIMINARYCY7C1412AV18CY7C1414AV18Logic Block Diagram (CY7C1410AV18)CLK A (20:0)Gen.KK Control LogicAddress RegisterD [7:0]R e a d A d d . D e c o d eRead Data Reg.RPS WPS Q [7:0]Control LogicAddress RegisterReg.Reg.Reg.8218168NWS [1:0]V REF W r i t e A d d . D e c o d e8A (20:0)21CC 82M x 8 Array2M x 8 ArrayWrite Reg Write Reg CQCQ 8DOFFLogic Block Diagram (CY7C1425AV18)CLK A (20:0)Gen.KK Control LogicAddress RegisterD [8:0]R e a d A d d . D e c o d eRead Data Reg.RPS WPS Q[8:0]Control LogicAddress RegisterReg.Reg.Reg.9219189BWS [0]V REF W r i t e A d d . D e c o d e9A (20:0)21CC 92M x 9 Array2M x 9 ArrayWrite Reg Write Reg CQCQ 9DOFFPRELIMINARYCY7C1412AV18CY7C1414AV18Logic Block Diagram (CY7C1412AV18)CLK A (19:0)Gen.KK Control LogicAddress RegisterD [17:0]R e a d A d d . D e c o d eRead Data Reg.RPS WPS Q [17:0]Control LogicAddress RegisterReg.Reg.Reg.1820183618BWS [1:0]V REF W r i t e A d d . D e c o d e18A (19:0)20CC 181M x 18 Array1M x 18 ArrayWrite Reg Write Reg CQCQ 18DOFFLogic Block Diagram (CY7C1414AV18)CLK A (18:0)Gen.KK Control LogicAddress RegisterD [35:0]R e a d A d d . D e c o d eRead Data Reg.RPS WPS Q [35:0]Control LogicAddress RegisterReg.Reg.Reg.3619367236BWS [3:0]V REF W r i t e A d d . D e c o d e36A (18:0)19CC 36512K x 36 Array512K x 36 ArrayWrite Reg Write Reg CQCQ 36DOFFPRELIMINARY CY7C1412AV18 CY7C1414AV18Pin ConfigurationsCY7C1410AV18 (4M × 8) – 15 × 17 FBGA2345671ABCDEFGHJKLMNP RACQNCNCNCNCDOFFNCNC/72M A NWS1KWPS NC/144MNC NCNCNCNCTDONCNCD5NCNCNCTCKNCNCA NC/288M K NWS0V SS A A ANC V SSV SS V SSV SSV DDAV SSV SSV SSV DDQ4NCV DDQNCNCNCNCQ7AV DDQ V SSV DDQ V DD V DDQ5V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AAD4V SSNC V SSNCNCV REFV SSV DDV SSV SSAV SSCNCQ6NCD7D6V DDA891011NCA ARPS CQA NC NC Q3V SS NC NC D3NCV SS NCQ2NCNCNCV REFNCNCV DDQ NCV DDQ NC NCV DDQV DDQV DDQD1V DDQ NC Q1NCV DDQV DDQ NCV SS NC D0NCTDITMSV SSA NCANCD2NCZQNCQ0NCNCNCNCACY7C1425AV18 (4M × 9)–11 × 15 Balls (15 × 17 FBGA)2345671A B C D E F G H J K L M NP RACQNCNCNCNCDOFFNCNC/72M A NC KWPS NC/144MNC NCNCNCNCTDONCNCD6NCNCNCTCKNCNCA NC/288M K BWS0V SS A A ANC V SSV SS V SSV SSV DDAV SSV SSV SSV DDQ5NCV DDQNCNCNCNCQ8AV DDQ V SSV DDQ V DD V DDQ6V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AAD5V SSNC V SSNCNCV REFV SSV DDV SSV SSAV SSCNCQ7NCD8D7V DDA891011Q0A ARPS CQA NC NC Q4V SS NC NC D4NCV SS NCQ3NCNCNCV REFNCNCV DDQ NCV DDQ NC NCV DDQV DDQV DDQD2V DDQ NC Q2NCV DDQV DDQ NCV SS NC D1NCTDITMSV SSA NCANCD3NCZQNCQ1NCNCD0NCAPRELIMINARY CY7C1412AV18 CY7C1414AV18Pin Configurations (continued)CY7C1412AV18 (2M × 18) – 15 × 17 FBGA2345671ABCDEFGHJKLMNP RACQNCNCNCNCDOFFNCNC/144M A BWS1KWPS NC/288MQ9D9NCNCNCTDONCNCD13NCNCNCTCKNCD10A NC K BWS0V SS A A AQ10V SSV SS V SSV SSV DDAV SSV SSV SSV DDQ11D12V DDQD14Q14D16Q16Q17AV DDQ V SSV DDQ V DD V DDQ13V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AAD11V SSNC V SSQ12NCV REFV SSV DDV SSV SSAV SSCNCQ15NCD17D15V DDA891011Q0A NC/72MRPS CQA NC NC Q8V SS NC Q7D8NCV SS NCQ6D5NCNCV REFNCQ3V DDQ NCV DDQ NC Q5V DDQV DDQV DDQD4V DDQ NC Q4NCV DDQV DDQ NCV SS NC D2NCTDITMSV SSA NCAD7D6NCZQD3Q2D1Q1D0NCA2345671A B C D E F G H J K L M NP RACQQ27D27D28D34DOFFQ33NC/288M NC/72M BWS2KWPS BWS1Q18D18Q30D31D33TDOQ28D29D22D32Q34Q31TCKD35D19A BWS3K BWS0V SS A A AQ19V SSV SS V SSV SSV DDAV SSV SSV SSV DDQ20D21V DDQD23Q23D25Q25Q26AV DDQ V SSV DDQ V DD V DDQ22V DDQV DDV DDQV DDV DDQ V DD V SSV DDV DDQV DDQ V SSV SS V SS V SSAACV SSA AAD20V SSQ29V SSQ21D30V REFV SSV DDV SSV SSAV SSCQ32Q24Q35D26D24V DDA891011Q0A NC/144MRPS CQA D17Q17Q8V SS D16Q7D8Q16V SS D15Q6D5D9Q14V REFQ11Q3V DDQ Q15V DDQ D14Q5V DDQVDDQV DDQD4V DDQ D12Q4Q12V DDQV DDQ D11V SS D10D2Q10TDITMSV SSA Q9AD7D6D13ZQD3Q2D1Q1D0Q13ACY7C1414AV18 (1M × 36) – 15 × 17 FBGAPRELIMINARY CY7C1412AV18 CY7C1414AV18Pin DefinitionsPin Name I/O Pin DescriptionD[x:0]Input-Synchronous Data input signals, sampled on the rising edge of K and K clocks during valid write operations.CY7C1410AV18 - D[7:0]CY7C1425AV18 - D[8:0]CY7C1412AV18 - D[17:0]CY7C1414AV18 - D[35:0]WPS Input-Synchronous Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored.NWS0,NWS1Nibble Write Select 0, 1 − active LOW. (CY7C1410AV18 Only) Sampled on the risingedge of the K and K clocks during Write operations. Used to select which nibble is writteninto the device during the current portion of the Write operations.Nibbles not writtenremain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All Nibble Write Selectsare sampled on the same edge as the data. Deselecting a Nibble Write Select will causethe corresponding nibble of data to be ignored and not written into the device.BWS0, BWS1, BWS2, BWS3Input-SynchronousByte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K andK clocks during Write operations. Used to select which byte is written into the deviceduring the current portion of the Write operations. Bytes not written remain unaltered.CY7C1425AV18 − BWS0 controls D[8:0]CY7C1412AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9].CY7C1414AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18]and BWS3 controls D[35:27].All the Byte Write Selects are sampled on the same edge as the data. Deselecting a ByteWrite Select will cause the corresponding byte of data to be ignored and not written intothe device.A Input-Synchronous Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) clocks during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1410AV18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1425AV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1412AV18 and 1M x 36 (2 arrays each of 512K x 36) for CY7C1414AV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1410AV18 and CY7C1425AV18, 20 address inputs for CY7C1412AV18 and 19 address inputs for CY7C1414AV18. These inputs are ignored when the appropriate port is deselected.Q[x:0]Outputs-Synchronous Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated.CY7C1410AV18 − Q[7:0]CY7C1425AV18 − Q[8:0]CY7C1412AV18 − Q[17:0]CY7C1414AV18 − Q[35:0]RPS Input-Synchronous Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers.C Input-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.C Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read datafrom the device. C and C can be used together to deskew the flight times of variousdevices on the board back to the controller. See application example for further details. K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputsto the device and to drive out data through Q[x:0] when in single clock mode. All accessesare initiated on the rising edge of K.PRELIMINARYCY7C1412AV18CY7C1414AV18Functional OverviewThe CY7C1410AV18, CY7C1425AV18, CY7C1412AV18 and CY7C1414AV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 8-bit data transfers in the case of CY7C1410AV18, two 9-bit data transfers in the case of CY7C1425AV18,two 18-bit data transfers in the case of CY7C1412AV18 and two 36-bit data transfers in the case of CY7C1414AV18, in one clock cycle.Accesses for both ports are initiated on the rising edge of the positive Input Clock (K). All synchronous input timings are referenced from the rising edge of the input clocks (K and K)and all output timings are referenced to the rising edge of output clocks (C and C or K and K when in single clock mode).All synchronous data inputs (D [x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q [x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode).All synchronous control (RPS, WPS, BWS [x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K).CY7C1412AV18 is described in the following sections. The same basic descriptions apply to CY7C1410AV18CY7C1425AV18 and CY7C1414AV18. Read OperationsThe CY7C1412AV18 is organized internally as 2 arrays of 1Mx18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K).The address is latched on the rising edge of the K Clock. The address presented to Address inputs is stored in the ReadK Input-Clock Negative Input Clock Input . K is used to capture synchronous inputs being presented to the device and to drive out data through Q [x:0] when in single clock mode.CQEcho ClockCQ is referenced with respect to C . This is a free running clock and is synchronized to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.CQ Echo ClockCQ is referenced with respect to C . This is a free running clock and is synchronized to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.ZQ InputOutput Impedance Matching Input . This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q [x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DD , which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.DOFF InputDLL Turn Off, active LOW . Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, “DLL Operation in the QDR-II.”TDO Output TDO for JTAG .TCK Input TCK pin for JTAG .TDI Input TDI pin for JTAG .TMS Input TMS pin for JTAG .NC N/A Not connected to the die . Can be tied to any voltage level.NC/72M N/A Not connected to the die . Can be tied to any voltage level.NC/144M N/A Not connected to the die . Can be tied to any voltage level.NC/288M N/A Not connected to the die . Can be tied to any voltage level.V REF Input-Reference Reference Voltage Input . Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points.V DD Power Supply Power supply inputs to the core of the device . V SS Ground Ground for the device .V DDQPower SupplyPower supply inputs for the outputs of the device .Pin Definitions (continued)Pin Name I/O Pin DescriptionPRELIMINARY CY7C1412AV18 CY7C1414AV18address register. Following the next K clock rise the corre-sponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subse-quent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode).Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the Output Clocks (C/C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.Write OperationsWrite operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the same K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the address is latched and the infor-mation presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed.Byte Write OperationsByte Write operations are supported by the CY7C1412AV18.A Write operation is initiated as described in the Write Opera-tions section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write opera-tions to a Byte Write operation.Single Clock ModeThe CY7C1412AV18 can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.Concurrent TransactionsThe Read and Write ports on the CY7C1412AV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the trans-action on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent infor-mation associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise.Depth ExpansionThe CY7C1412AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.Programmable ImpedanceAn external resistor, RQ, must be connected between the ZQ pin on the SRAM and V SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with V DDQ=1.5V.The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.Echo ClocksEcho clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock (C/C) of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLLThese chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. The DLL can also be reset by slowing the cycle time of input clocks K and K to greater than 30 ns.PRELIMINARYCY7C1412AV18CY7C1414AV18Application Example [1]Truth Table [2, 3, 4, 5, 6, 7]OperationK RPS WPS DQDQWrite Cycle:Load address on the rising edge of K clock; input write data on K and K rising edges.L-HXLD(A + 0)at K(t) ↑D(A + 1) at K(t) ↑Read Cycle:Load address on the rising edge of K clock; wait one and a half cycle; read data on C and C rising edges.L-H L X Q(A + 0) at C(t + 1)↑Q(A + 1) at C(t + 2) ↑NOP: No Operation L-H H H D = XQ = High-Z D = XQ = High-Z Standby: Clock StoppedStoppedXXPrevious StatePrevious StateWrite Cycle Descriptions (CY7C1410A V18 and CY7C1412A V18)[2, 8]BWS 0/NWS 0BWS 1 / NWS 1K K CommentsLLL-H–During the Data portion of a Write sequence :CY7C1410AV18 − both nibbles (D [7:0]) are written into the device, CY7C1412AV18 − both bytes (D [17:0]) are written into the device.L L –L-H During the Data portion of a Write sequence :CY7C1410AV18 − both nibbles (D [7:0]) are written into the device, CY7C1412AV18 − both bytes (D [17:0]) are written into the device.L H L-H–During the Data portion of a Write sequence :CY7C1410AV18 − only the lower nibble (D [3:0]) is written into the device. D [7:4] will remain unaltered,CY7C1412AV18 − only the lower byte (D [8:0]) is written into the device. D [17:9] will remain unaltered.Notes:1.The above application shows four QDR-II being used.2.X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.3.Device will power-up deselected and the outputs in a three-state condition.4.“A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.5.“t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.6.Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.7.charging symmetrically.8.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS 0, NWS 1, BWS 0, BWS 1, BWS 2 and BWS 3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.PRELIMINARYCY7C1412AV18CY7C1414AV18LH–L-H During the Data portion of a Write sequence :CY7C1410AV18 − only the lower nibble (D [3:0]) is written into the device. D [7:4] will remain unaltered,CY7C1412AV18 − only the lower byte (D [8:0]) is written into the device. D [17:9] will remain unaltered.H L L-H–During the Data portion of a Write sequence :CY7C1410AV18 − only the upper nibble (D [7:4]) is written into the device. D [3:0] will remain unaltered,CY7C1412AV18 − only the upper byte (D [17:9]) is written into the device. D [8:0] will remain unaltered.H L –L-H During the Data portion of a Write sequence :CY7C1410AV18 − only the upper nibble (D [7:4]) is written into the device. D [3:0] will remain unaltered,CY7C1412AV18 − only the upper byte (D [17:9]) is written into the device. D [8:0] will remain unaltered.H H L-H –No data is written into the devices during this portion of a Write operation. HH–L-H No data is written into the devices during this portion of a Write operation.Write Cycle Descriptions (CY7C1414A V18) [2, 8]BWS 0BWS 1BWS 2BWS 3K K CommentsL L L L L-H -During the Data portion of a Write sequence, all four bytes (D [35:0]) are written into the device.L L L L -L-H During the Data portion of a Write sequence, all four bytes (D [35:0]) are writteninto the device.L H H H L-H -During the Data portion of a Write sequence, only the lower byte (D [8:0]) is written into the device. D [35:9] will remain unaltered.L H H H -L-H During the Data portion of a Write sequence, only the lower byte (D [8:0]) is writteninto the device. D [35:9] will remain unaltered.H L H H L-H -During the Data portion of a Write sequence, only the byte (D [17:9]) is written into the device. D [8:0] and D [35:18] will remain unaltered.H L H H -L-H During the Data portion of a Write sequence, only the byte (D [17:9]) is written intothe device. D [8:0] and D [35:18] will remain unaltered.H H L H L-H -During the Data portion of a Write sequence, only the byte (D [26:18]) is written into the device. D [17:0] and D [35:27] will remain unaltered.H H L H -L-H During the Data portion of a Write sequence, only the byte (D [26:18]) is written intothe device. D [17:0] and D [35:27] will remain unaltered.H H H L L-H During the Data portion of a Write sequence, only the byte (D [35:27]) is written into the device. D [26:0] will remain unaltered.H H H L -L-H During the Data portion of a Write sequence, only the byte (D [35:27]) is written intothe device. D [26:0] will remain unaltered.H H H H L-H -No data is written into the device during this portion of a Write operation. HHHH-L-H No data is written into the device during this portion of a Write operation.Write Cycle Descriptions (CY7C1425A V18)BWS 0K K CommentsL L-H –During the Data portion of a Write sequence :CY7C1425AV18 − the single byte (D [8:0]) is written into the device L –L-H During the Data portion of a Write sequence :CY7C1425AV18 − the single byte (D [8:0]) is written into the device, H L-H –No data is written into the devices during this portion of a Write operation. H–L-HNo data is written into the devices during this portion of a Write operation.Write Cycle Descriptions (CY7C1410A V18 and CY7C1412A V18) (continued)[2, 8]BWS 0/NWS 0BWS 1 / NWS 1K KComments。
CY7C1472V33-167AXC资料
PRELIMINARY72-Mbit (2M x 36/4M x 18/1M x 72) PipelinedSRAM with NoBL™ ArchitectureCY7C1470V33CY7C1472V33CY7C1474V33Features•Pin-compatible and functionally equivalent to ZBT™ •Supports 250-MHz bus operations with zero wait states —Available speed grades are 250, 200, and 167 MHz •Internally self-timed output buffer control to eliminate the need to use asynchronous OE•Fully registered (inputs and outputs) for pipelined operation•Byte Write capability •Single 3.3V power supply •3.3V/2.5V I/O power supply •Fast clock-to-output time —3.0 ns (for 250-MHz device)—3.0 ns (for 200-MHz device)—3.4 ns (for 167-MHz device)•Clock Enable (CEN) pin to suspend operation •Synchronous self-timed writes•CY7C1470V33 and CY7C1472V33 available in lead-free 100 TQFP , and 165-ball fBGA packages. CY7C1474V33 available in 209-ball fBGA package•IEEE 1149.1 JTAG Boundary Scan compatible •Burst capability—linear or interleaved burst order •“ZZ” Sleep Mode option and Stop Clock optionFunctional DescriptionThe CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL ™) logic, respectively.They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being trans-ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33, CY7C1472V33,and CY7C1474V33 are pin compatible and functionally equiv-alent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal,which when deasserted suspends operation and extends the previous clock cycle.Write operations are controlled by the Byte Write Selects (BW a –BW h for CY7C1474V33, BW a –BW d for CY7C1470V33and BW a –BW b for CY7C1472V33) and a Write Enable (WE)input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE 1, CE 2, CE 3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.Logic Block Diagram-CY7C1470V33 (2M x 36)元器件交易网Logic Block Diagram-CY7C1474V33 (1M x 72)Selection GuideCY7C1470V33-250CY7C1472V33-250CY7C1474V33-250CY7C1470V33-200CY7C1472V33-200CY7C1474V33-200CY7C1470V33-167CY7C1472V33-167CY7C1474V33-167Unit Maximum Access Time3.0 3.0 3.4ns Maximum Operating Current500500450mA Maximum CMOS Standby Current120120120mAShaded areas contain advance information.Please contact your local Cypress sales representative for availability of these parts.Pin ConfigurationsA A A A A 1A 0V S SV D DA A A A A AV DDQV SS DQb DQb DQb V SSV DDQDQb DQb V SSNCV DDDQaDQa V DDQV SSDQa DQa V SS V DDQ V DDQV SS DQc DQc V SS V DDQ DQc V DD V SS DQd DQd V DDQ V SS DQd DQd DQd V SS V DDQ A A C E 1C E 2B W aC E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZCY7C1470V33100-pin TQFP PackagesA A A A A 1A 0V S SV D DA A A A A AA NC NC V DDQ V SS NC DQPa DQa DQa V SS V DDQ DQa DQa V SS NC V DD DQa DQa V DDQ V SS DQa DQa NC NC V SS V DDQ NC NC NCNC NC NC V DDQ V SSNC NC DQb DQbV SS V DDQ DQb DQbV DD V SS DQb DQbV DDQ V SS DQb DQb DQPbNC V SS V DDQNC NC NCA A C E 1C E 2N C N C B W b B W a C E 3V D DV S SC L K W E C E N O E A A123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495080797877767574737271706968676665646362616059585756555453525110099989796959493929190898887868584838281A AA D V /L D ZZ M O D E CY7C1472V33B W d M O D E B W c DQc DQc DQc DQc DQPc DQd DQd DQd DQPbDQbDQa DQaDQa DQaDQPa DQbDQb(2M × 36)(4M × 18)B W b NC NC NC DQc NC E (288)E (144)A E (288)E (144)DQPdA A A A APin Configurations (continued)234567 1ABCDEFGHJKLMNP RTDOE(288)NCDQP cDQ cDQP dNCDQ dA CE1BW b CE3BW c CENA CE2DQ cDQ dDQ dMODENCDQ cDQ cDQ dDQ dDQ dAV DDQBW d BW a CLK WEV SS V SS V SS V SSV DDQ V SSV DD V SSV SSV SSNCV SSV SSV SSV SSV DDQV DDQNCV DDQV DDQV DDQV DDQAAV DD V SSV DD V SS V SSV DDQ V DDV SSV DDV SSV DD V SS V SSV SSV DDV DD V SSV DD V SS V SSNCTCKA0V SSTDIAADQ c V SSDQ c V SSDQ cDQ cNCV SSV SSV SSV SSNCV SSA1DQ dDQ dNCNCV DDQV SSTMS891011NCA AADV/LD NCOE A A E(144)V SS V DDQ NC DQP bV DDQV DD DQ bDQ bDQ bNCDQ bNCDQ aDQ aV DD V DDQV DD V DDQ DQ bV DDNCV DDDQ aV DD V DDQ DQ aV DDQV DDV DD V DDQV DD V DDQ DQ aV DDQAAV SSAAADQ bDQ bDQ bZZDQ aDQ aDQP aDQ aAV DDQA2345671A B C D E F G H J K L M NP RTDOE(288)NCNCNCDQP bNCDQ bA CE1CE3BW b CENA CE2NCDQ bDQ bMODENCDQ bDQ bNCNCNCAV DDQBW a CLK WEV SS V SS V SS V SSV DDQ V SSV DD V SSV SSV SSNCV SSV SSV SSV SSV DDQV DDQNCV DDQV DDQV DDQV DDQAAV DD V SSV DD V SS V SSV DDQ V DDV SSV DDV SSV DD V SS V SSV SSV DDV DD V SSV DD V SS V SSNCTCKA0V SSTDIAADQ b V SSNC V SSDQ bNCNCV SSV SSV SSV SSNCV SSA1DQ bNCNCNCV DDQV SSTMS891011NCA AADV/LD AOE A A E(144)V SS V DDQ NC DQP aV DDQV DD NCDQ aDQ aNCNCNCDQ aNCV DD V DDQV DD V DDQ DQ aV DDNCV DDNCV DD V DDQ DQ aV DDQV DDV DD V DDQV DD V DDQ NCV DDQAAV SSAAADQ aNCNCZZDQ aNCNCDQ aAV DDQACY7C1472V33 (4M × 18)CY7C1470V33 (2M × 36)165-Ball fBGA PinoutAANCNCPin Configurations (continued)A B C D E F G H J K L M N P R T U V W1234567891110DQgDQgDQgDQgDQgDQgDQgDQgDQcDQcDQcDQcNCDQPgDQhDQhDQhDQhDQdDQdDQdDQdDQPdDQPcDQcDQcDQcDQcNCDQhDQhDQhDQhDQPhDQdDQdDQdDQdDQbDQbDQbDQbDQbDQbDQbDQbDQfDQfDQfDQfNCDQPfDQaDQaDQaDQaDQeDQeDQeDQeDQPaDQPbDQfDQfDQfDQfNCDQaDQaDQaDQaDQPeDQeDQeDQeDQeA A A ANC NCNC A A NCA A AA A A A1A0A A AA AANCNCNCNC NCNCBWS b BWS fBWS e BWS aBWS c BWS gBWS dBWS hTMS TDI TDO TCKNCNC MODE NCCEN V SSNCCLK NC V SSV DD V DD V DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV DDV SS V SSV SSV SSV SSV SS V SSV SSNCV DDNCOECE3CE1CE2ADV/LDWEV SSV SSV SSV SS V SS V SS V SSZZV SS V SS V SS V SSNCV DDQV SSV SS NC V SS V SSQV SS V SS VSSV SSNCV SSV DDQ V DDQ V DDQ V DDQV DDQ NC V DDQ VDDQV DDQ V DDQ NC V DDQ V DDQV DDQ V DDQ NC V DDQ VDDQV DDQV DDQV DDQ V DDQV DDQ VDDQV DDQ V DDQ209-ball PBGACY7C1474V33 (1M X 72)Pin DefinitionsPin Name I/O Type Pin DescriptionA0 A1 AInput-SynchronousAddress Inputs used to select one of the address locations. Sampled at the rising edge ofthe CLK.BW a BW b BW c BW d BW e BW f BW g BW hInput-SynchronousByte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.Sampled on the rising edge of CLK. BW a controls DQ a and DQP a, BW b controls DQ b and DQP b,BW c controls DQ c and DQP c, BW d controls DQ d and DQP d, BW e controls DQ e and DQP e, BW fcontrols DQ f and DQP f, BW g controls DQ g and DQP g, BW h controls DQ h and DQP h.WE Input-Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.ADV/LD Input-Synchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address.CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.CE1Input-Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.CE2Input-Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.CE3Input-Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.OE Input-Asynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.CEN Input-Synchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.DQ S I/O-Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a–DQ d are placed in a tri-state condition. The outputs are automat-ically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQP X I/O-Synchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ X. During write sequences, DQP a is controlled by BW a, DQP b is controlled by BW b, DQP c is controlled by BW c, and DQP d is controlled by BW d, DQP e is controlled by BW e, DQP f is controlled by BW f, DQP g is controlled by BW g, DQP h is controlled by BW h.MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.Pulled LOW selects the linear burst order. MODE should not change states during operation.When left floating MODE will default HIGH, to an interleaved burst order.TDO JTAG SerialOutputSynchronousSerial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.TDI JTAG Serial InputSynchronousSerial data-In to the JTAG circuit. Sampled on the rising edge of TCK.Functional OverviewThe CY7C1470V33, CY7C1472V33, and CY7C1474V33 are synchronous-pipelined Burst NoBL SRAMs designed specifi-cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 3.0 ns (225-MHz device).Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). BW[x] can be used to conduct Byte Write operations.Write operations are qualified by the Write Enable (WE). All Writes are simplified with on-chip synchronous self-timed write circuitry.Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.Single Read AccessesA read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.0 ns (225-MHz device) provided OE is active LOW. After the first clock of the Read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise.Burst Read AccessesThe CY7C1470V33/CY7C1472V33/CY7C1474V33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incre-mented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.Single Write AccessesWrite accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the Write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block.On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DQP (DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,b,c,d/DQP a,b,c,d for CY7C1470V33 and DQ a,b/DQP a,b for CY7C1472V33). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).On the next clock rise the data presented to DQ and DQP (DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,b,c,d/DQP a,b,c,d for CY7C1470V33 & DQ a,b/DQP a,b for CY7C1472V33) (or a subset for byte write operations, seeTMS Test Mode SelectSynchronousThis pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. TCK JTAG Clock Clock input to the JTAG circuitry.V DD Power Supply Power supply inputs to the core of the device.V DDQ I/O Power Supply Power supply for the I/O circuitry.V SS Ground Ground for the device. Should be connected to ground of the system.NC–No connects. This pin is not connected to the die.E(144, 288)–These pins are not connected. They will be used for expansion to the 144M and 288M densities.ZZ Input-Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating.Pin Definitions (continued)Pin Name I/O Type Pin DescriptionWrite Cycle Description table for details) inputs is latched into the device and the write is complete.The data written during the Write operation is controlled by BW (BW a,b,c,d,e,f,g,h for CY7C1474V33, BW a,b,c,d for CY7C1470V33 and BW a,b for CY7C1472V33) signals. The CY7C1470V33/CY7C1472V33/CY7C1474V33 provides Byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple Byte Write operations.Because the CY7C1470V33/CY7C1472V33/CY7C1474V33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DQP (DQ a,b,c,d,e,f,g,h/DQP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,b,c,d/DQP a,b,c,d for CY7C1470V33 and DQ a,b/DQP a,b for CY7C1472V33) inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ and DQP (DQ a,b,c,d,e,f,g,h/ DQP a,b,c,d,e,f,g,h for CY7C1474V33, DQ a,b,c,d/ DQP a,b,c,d for CY7C1470V33 and DQ a,b/DQP a,b for CY7C1472V33) are automatically tri-stated during the data portion of a Write cycle, regardless of the state of OE.Burst Write AccessesThe CY7C1470V33/CY7C1472V33/CY7C1474V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BW a,b,c,d,e,f,g,h for CY7C1474V33, BW a,b,c,d for CY7C1470V33 and BW a,b for CY7C1472V33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.Sleep ModeThe ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep”mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of t ZZREC after the ZZ input returns LOW. Interleaved Burst Address Table(MODE = Floating or V DD)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011010011101011000111100100Linear Burst Address Table(MODE = GND)FirstAddressSecondAddressThirdAddressFourthAddress A1,A0A1,A0A1,A0A1,A000011011011011001011000111000110ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min.Max Unit I DDZZ Sleep mode standby current ZZ > V DD − 0.2V120mA t ZZS Device operation to ZZ ZZ > V DD− 0.2V2t CYC ns t ZZREC ZZ recovery time ZZ < 0.2V2t CYC ns t ZZI ZZ active to sleep current This parameter is sampled2t CYC ns t RZZI ZZ Inactive to exit sleep current This parameter is sampled0nsNotes:1.X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.2.[a:d]. See Write Cycle Description table for details.3.When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.4.The DQ and DQP pins are controlled by the current cycle and the OE signal.5.6.Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.7.OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ s and DQP [a:d] = Tri-state when OE is inactive or when the device is deselected, and DQ s = data when OE is active.Truth Table [1, 2, 3, 4, 5, 6, 7]Operation Address Used CE ZZ ADV/LDWE BW x OE CENCLK DQ Deselect Cycle None H L L X X X L L-H Tri-State ContinueDeselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst)External L L L H X L L L-H Data Out (Q)Read Cycle(Continue Burst)Next X L H X X L L L-H Data Out (Q)NOP/Dummy Read (Begin Burst)External L L L H X H L L-H Tri-State Dummy Read (Continue Burst)Next X L H X X H L L-H Tri-State Write Cycle (Begin Burst)External L L L L L X L L-H Data In (D)Write Cycle(Continue Burst)Next X L H X L X L L-H Data In (D)NOP/Write Abort (Begin Burst)None L L L L H X L L-H Tri-State Write Abort(Continue Burst)Next X L H X H X L L-H Tri-StateIgnore Clock Edge (Stall)Current X L X X X X H L-H -Sleep ModeNoneXHXXXXX XTri-StatePartial Write Cycle Description[1, 2, 3, 8]Function (CY7C1470V33)WE BW d BW c BW b BW a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ a and DQP a)L H H H L Write Byte b – (DQ b and DQP b)L H H L H Write Bytes b, a L H H L L Write Byte c – (DQ c and DQP c)L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQ d and DQP d)L L H H H Write Bytes d, a L L H H L Write Bytes d,b L L H L H Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L LFunction (CY7C1472V33)WE BW b BW a Read H x xWrite – No Bytes Written L H HWrite Byte a – (DQ a and DQP a)L H LWrite Byte b – (DQ b and DQP b)L L HWrite Both Bytes L L LFunction (CY7C1474V33)WE BW x Read H xWrite – No Bytes Written L HWrite Byte X − (DQ x and DQP x)L LWrite All Bytes L All BW = L Note:8.[a:d] is valid. Appropriate Write will be done based on which Byte Write isactive.IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1470V33/CY7C1472V33/CY7C1474V33 incorpo-rates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1470V33/CY7C1472V33/CY7C1474V33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.Disabling the JTAG FeatureIt is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V SS) to prevent clocking of the device. TDI and TMS are inter-nally pulled up and may be unconnected. They may alternately be connected to V DD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.TAP Controller State DiagramThe 0/1 next to each state represents the value of TMS at the rising edge of TCK.Test Access Port (TAP)Test Clock (TCK)The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.Test MODE SELECT (TMS)The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.Test Data-In (TDI)The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.)Test Data-Out (TDO)The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block DiagramPerforming a TAP ResetA RESET is performed by forcing TMS HIGH (V DD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating.At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.TAP RegistersRegisters are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.。
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■ 8 位或 16 位外部数据接口
■ 可生成智能介质标准错误校正码 ECC
■ 通用可编程接口 (General Programmable Interface， GPIF) ❐ 可与大多数并行接口直接连接 ❐ 由可编程波形描述符和配置寄存器定义波形 ❐ 支持多个 Ready (RDY) 输入和 Control (CTL) 输出
4 KB8/16源自FIFO丰富的 I/O 接口包含 两个 USART
通用可编程 I/F 符合 ASIC/DSP 或 总线标准，例如 ATAPI、 EPP 等
高达 96 MB/s 突发速率
增强型 USB 核 简化 8051 代码
“软配置”容易 进行固件更换
FIFO 和端点存储器 （主控端或从属端操作）
1.1 特色 （仅限 CY7C68013A/14A）
片上 PLL 可根据收发器 /PHY 的需要将 24 MHz 振荡器倍频到 480 MHz，而内部计数器可将其分频以用作 8051 时钟。默认的 8051 时钟频率是 12 MHz。 8051 的时钟频率可以由 8051 通过 CPUCS 寄存器动态更改。
USB控制芯片cy7c68013中文手册
3.1 USB 信号传输速度 FX2LP 按照 2000 年 4 月 27 日发布的 《USB 规范修订版 2.0》 中定义的三种速率中的两种运行：
■ 全速，信号传输比特率为 12 Mbps ■ 高速，信号传输比特率为 480 Mbps FX2LP 不支持 1.5 Mbps 的低速信号发射模式。
■ 有商业和工业温度等级供选择 （除 VFBGA 外的所有封装）
Cypress Semiconductor Corporation • 198 Champion Court 文件编号：001-50431 修订版 **
• San Jose, CA 95134-1709 • 408-943-2600
修订时间 2008 年 12 月 11 日
[+] Feedback
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
逻辑方框图
24 MHz 外部 XTAL
FX2LP
高性能微型 使用标准工具 具有低功耗选项
数据 (8)
地址 (16)
/0.5 VCC x20 /1.0
PLL /2.0
1.5k 连接后可 实现全速
3.3 I2C 总线
FX2LP 仅支持在 100/400 KHz 下将 I2C 总线用作主控端。 SCL 和 SDA 引脚具有开漏输出和滞后输入。即使未连接 I2C 设备，这 些信号也必须上拉至 3.3V。
3.4 总线
所有封装 （8 位或 16 位 “FIFO” 双向数据总线）均在 IO 端口 B 和 D 上多路复用。 128 引脚封装：添加仅 16 位输出 8051 地址 总线和 8 位双向数据总线。
■ 16 K 字节片上代码/数据 RAM
CY7C961中文资料
Low Cost VMEbus InterfaceController Familyfax id: 5603CY7C960CY7C961Features•80-Mbyte-per-second block transfer rates•All VME64 transactions provided, including A64/D64, A40/MD32 transfers •Auto Slot ID •CR/CSR space•All standard (Rev C) VMEbus transactions implemented •VMEbus Interrupter •No local CPU required•Programmable from VMEbus, serial PROM, or local bus •DRAM controller, including refresh •On-chip DMA controller •Local I/O controller•Flexible VMEbus address scheme •User-configured VMEbus response •64-pin TQFP, 10x10mm (CY7C960)•100-pin TQFP, 14x14mm (CY7C961)Functional DescriptionThe CY7C960 Slave VMEbus Interface Controller provides the board designer with an integrated, full-featured VME64 inter-face. This 64-pin device can be programmed to handle every transaction defined in the VME64 specification. The CY7C961is based upon the CY7C960: additional features include Re-mote Master capability whereby the CY7C961 can be com-manded to move data as a VMEbus master. The CY7C961 is packaged in a 100-pin outline.The CY7C960 contains all the circuitry needed to control large DRAM arrays and local I/O circuitry without the intervention of a local CPU. There are no registers to read or write, no com-plex command blocks to be constructed in memory. The CY7C960 simply fetches its own configuration parameters during the power-on reset period. After reset the CY7C960responds appropriately to VMEbus activity and controls local circuitry transparently.VME CONTROL INTERF ACECY7C960Logic Block Diagramc960–1REGION/AM TABLE CY7C964CONTROLLERPOWER-ON RESET GENERATORAM [5:0]SYSRESET*AS*DS0*DS1*DTACK*WRITE*CLK REGION [3:0]IRQ*IACK*IACKIN*IACKOUT*LOCAL ADDRESS CONTROLLERCHIP SELECT OUTPUT PATTERNTABLEDATA BYTE ENABLE CONTROLLERDATABYTE LANE DECODERLOCAL CONTROL CIRCUITDRAMCONTROLLERREFRESHCONTROLLERTIMING GENERATORVME INTERRUPT INTERF ACECS[5:0]DBE [3:0]LACK*LDEN*PREN*SWDEN*R/WR A S *C A S *R O W C O LL I R Q *D 64S T R O BE D E N O *D E N I N *D E N I N 1*L A D I L A E N L E D I L E D O A B E N *L D SLA [7:1]LWORD元器件交易网REGION/AMTABLE CY7C964CONTROLLERPOWER-ON RESET GENERATORAM[5:0]SYSRESET*AS*DS0*DS1*DTACK*WRITE*BR*BBSY*BERR*BGIN*BGOUT*CLK REGION [3:0]IRQ*IACK*IACKIN*IACKOUT*DATA BYTE ENABLE CONTROLLER DATABYTELANEDECODERLOCAL CONTROL CIRCUITDRAMCONTROLLERREFRESH CONTROLLERTIMING GENERATORVME CONTROL INTERF ACEVME INTERRUPT INTERF ACECS [5:0]DBE [3:0]LACK*LBERR*LDEN*PREN*SWDEN*R/WR A S *C A S *R O W C O LL I R Q *D 64S T R O BE D E N O *D E N I N *D E N I N 1*L A D I L A E N L E D I L E D O A B E N *L D S M W B *B L T L A D OF C 1L A E N 321V M E C N TLA [7:1]LWORDLOCAL ADDRESS CONTROLLERCHIP SELECT OUTPUTPATTERN TABLELD [7:0]DMA CHANNEL REGISTERSDMACONTROLLERLOCKCONTROLLERTop ViewTQFP c960–26463616260231323334121315141645313059581791087611181921202223262527282924403937383635414243484647454453525051495756LA7A M 1G N DR /WS W D E N *R A S */C S 4C A S */C S 5A M 2R O W /C S 2P R E N *LA6LA5LA4IRQ*LA3LA1AM5VCC DS1*LWORD LAENLA2D T A C K *D 64L E D O L E D II A C K O U T *I A C K I N *I A C K *A S *L A D I D E N O *LACK*LIRQ*LDEN*CS0CS1AM3GND REGION1REGION0DENIN*REGION25455C O L /C S 3GND A M 0V C C D B E 1D B E 2D B E 3D B E 0S T R O B EA B E N *G N D D S 0*V C C LDSDENIN1*VCC WRITE*REGION3/CS2AM4CY7C960Pin ConfigurationCY7C961Logic Block Diagramc960–3S Y S R E S E T *CLK SELECTLMFunctional Description (continued)The CY7C960 controls a bridge between the VMEbus and lo-cal DRAM and I/O. Once programmed, the CY7C960 provides activities such as DRAM refresh and local I/O handshaking in a manner that requires no additional local circuitry. The VME-bus control signals are connected directly to the CY7C960.The VMEbus address and data signals are connected to com-panion address/data transceivers which are controlled by the CY7C960. The CY7C964 VMEbus Interface Logic Circuit is an ideal companion device: the CY7C964 provides a slice of data and address logic that has been optimized for VME64 trans-actions. In addition to providing the specified drive strength and timing for VME64 transactions, the CY7C964 contains all the circuitry needed to multiplex the address/data bus for mul-tiplexed VMEbus transactions. It contains counters and latch-es needed during BL T operations; and it also contains address comparators which can be used in the board’s Slave Address Decoder. For a 6U or 9U application, four CY7C964 devices are controlled by a single CY7C960. For 3U applications, the CY7C960 controls two CY7C964 devices and an address latch.The design of the CY7C960 makes it unnecessary to know the details of the VMEbus transaction timing and protocol. The complex VMEbus activities are translated by CY7C960 to sim-ple local cycles involving a few familiar control signals. Similar-ly, it is not necessary to understand the operation of the com-panion device, CY7C964: all control sequences for the part are generated automatically by the CY7C960 in response to VME-bus or local activity. If more information is desired, consult the CY7C964 chapter in the VIC64 Design Notes (available sepa-rately).VMEbus transactions supported by the CY7C960 include D8,D16, D32 (incl. UA T), MD32, D64, A16, A24, A32, A40, A64single-cycle and block-transfer reads and writes, Read-Modi-fy-Write cycles (incl. multiplexed), and Address-only (with or without Handshake). The CY7C960 functions as a VMEbus Interrupter, and supports the new Auto Slot ID standard and CR/CSR space. The CY7C960 also handles LOCK cycles, al-though full LOCK support is not possible within the constraints of the CY7C960 pinout. Full LOCK support is provided by the CY7C961.On the local side, no CPU is needed to program the CY7C960,nor to manage transactions. All programmable parameters are initialized through the use of either the VMEbus, a serial PROM, or some other local circuit. As the CY7C960 incorporates a reliable power-on reset circuit, parameters are self-loaded by the device at power-up or after a system reset. If the VMEbus is used to provide parameters, a VMEbus Master provides the programming informa-tion using a protocol, described in the User’s Guide, which is com-pliant with the Auto Slot ID protocol from the new VME64 specifica-tion.Top ViewTQFP 1009997989623142415960611213151416454039959417269108761127283029313235343637383367666465636268697075737472718988868785939284LA7A M 2N CD BE 0A M 0S W D E N *R A S */C S 4L D 3C A S */C S 5L D 4P R E N *LA6LA5LD7LA4SELECTLM*LAEN321IRQ*LA3GND AM5VCC LA1NC N C D T A C K *G N D N CD S 0*I A C K O U T *I A C K I N *B G O U T *I A C K *M W B *D E N O *LACK*LIRQ*LDEN*LD1CS0VCC AM3AM4BERR*GND VMECNT REGION2REGION3/CS29091N C LBERR*L D 5C O L /C S 3A M 1G N D B R *R O W /C S 2N CA S *L A D I S T R OB E B G I N *LA2BBSY*NC VCCLD2CS1NC DS1*NCLWORD FC1LDSDENIN1*LAENN C V C C L D 6D B E 1G N DD BE 2D B E 3R /WLD0CLK NC WRITE*NC REGION1REGION0DENIN*N C V C C B L T S Y S R E S E T *L A D O D 64L E D O18192021222324258382818079787776585756555453525143444546474849L E D I50c960–4CY7C961Pin ConfigurationA B E N *T o assist in generating the configuration file, a Win-dows™-based program is available which guides the user through the process of selecting appropriate options. Contact your Sales Office for further details.The CY7C961 is a true superset of the CY7C960. Signal pins have been added to control CY7C964 DMA functions. Existing VMEbus input pins have been changed to bidirectional and augmented to complete a master interface. A data port and chip select signal (SELECTLM*) complete the pin additions.As a VMEbus Slave, the CY7C961 behaves in every respect like the CY7C960. It simply has more pins, a master block transfer facility, and (because of the addition of the BBSY* con-nection) full lock cycle support.From a system perspective, the CY7C961 master block trans-fer capability can be viewed as a DMA channel that resides on the slave card, but is controlled over the VMEbus by one or more VMEbus masters or programmed from the local bus.The CY7C961 master block facility provides “block transfer on demand” capability for slave cards built around the Cypress CY7C961/CY7C964 chipset. This facility allows one or many VMEbus masters to write short series of commands to the slave card, telling it how much data to move, where to get it from, where to put it, and what transfer protocol to use while moving it. Blocks can be moved over the VMEbus as indivisible single cycles or BLTs. The protocol menu includes D8, D16,D32, MD32, or D64. A16, A24, A32, A40, and A64 address spaces can be specified. Burst lengths from 16 bytes to 8megabytes can be requested. Eight registers accessible from the VMEbus make the facility simple to configure and simple to control. The facility has a busy semaphore, a VMEbus Inter-rupt on completion feature with a programmable Status/ID byte, and a built in requester and bus grant daisychain.System Diagram Using the CY7C960SWDEN RWDBE[3:0],RWLACK*RAS*,CAS*,ROW,COLLA [31:0]D [31:16]SWAP BUFFERL D [15:0]LA [31:0]CY7C964DRAMMEMORYI/OLIRQ*DECODERREGIONLA [7:1,LWORD]A [31:1],LWORD*VME INTERRUPT BUSVME ADDRESS BUS VMEDATABUS CY7C964CY7C964CY7C964CY7C960CS[2:0]I R Q *I A C K *I A C K I N *I A C K O U T *D S 1/0*D T A C K W R I T E *S Y S R E S E T *D[31:0]A M [5:0]A S *D [7:0]D [15:8]A [7:1],L W O R D *A [15:8]D [23:16]A [23:16]D [31:24]A [31:24]c960–5VCOMPDC Specifications - VMEbus Signals AS*, DS1*, DS0*, DTACK*, BBSYParameter Description Test Conditions Comm.Industrial Military Units V IH Minimum High-LevelInput Voltage2.0 2.0 2.0VV IL Maximum Low-LevelInput Voltage0.80.80.8VV OH Minimum High-LevelOutput Voltage V CC = Min.,I OH =2.4–16 mA2.4–10 mA2.4–9 mAVV OL Maximum Low-LevelOutput Voltage V CC = Min.,I OL =0.664 mA0.660 mA0.652 mAVI L Maximum InputLeakage Current V CC = Max.,GND < V IN < V CC±5±5±5µAV IK Input Clamp Voltage V CC = Min., I IN = –18 mA–1.2–1.2–1.2VI OZ Maximum OutputLeakage Current V CC = Max.GND < V OUT < V CCOutputs Disabled±10±10±10µADC Specifications - VMEbus Signals AM5, AM4, AM3, AM2, AM1, AM0, IRQ*, BERR*, Write, BR[1] Parameter Description Test Conditions Comm.Industrial Military Units V IH Maximum High-LevelInput Voltage2.0 2.0 2.0VV IL Maximum Low-LevelInput Voltage0.80.80.8VV OH Minimum High-LevelOutput Voltage V CC = Min.,I OH =2.4–16 mA2.4–10 mA2.4–9 mAVV OL Minimum Low-LevelOutput Voltage V CC = Min.,I OL =0.648 mA0.644 mA0.638 mAVI L Maximum InputLeakage Current V CC = Max.,GND < V IN < V CC±5±5±5µAV IK Input Clamp Voltage V CC = Min., I IN = –18 mA–1.2–1.2–1.2VI OZ Maximum OutputLeakage Current V CC = Max.GND < V OUT < V CCOutputs Disabled±5±5±10µADC Specifications - All Other Output Signals[2]Parameter Description Test Conditions Comm.Industrial Military Units V IH Maximum High-LevelInput Voltage2.0 2.0 2.0VV IL Maximum Low-LevelInput Voltage0.80.80.8VV OH Minimum High-LevelOutput Voltage V CC = Min.,I OH =2.4–16 mA2.4–10 mA2.4–9 mAVV OL Minimum Low-LevelOutput Voltage V CC = Min.,I OL =0.620 mA0.618 mA0.616 mAVI L Maximum InputLeakage Current V CC = Max.,GND < V IN < VCC±5±5±5µAV IK Input Clamp Voltage V CC = Min., I IN = –18 mA–1.2–1.2–1.2VI OZ Maximum OutputLeakage Current V CC = Max.GND < V OUT < V CCOutputs Disabled±5±5±10µANotes:1.The BERR* signal has an on-chip pull-up resistor. For this signal the I OZ value is modified by Pullup/Pulldown Current.2.Some signals have an on-chip pull-up or pull-down resistors. For these signals I OZ value is modified.Related DocumentsVMEBus Interface HandbookCapacitance - All SignalsParametersDescriptionTest ConditionsMax.Units C IN Input Capacitance T A = 25°C, f = 1 MHz,V CC = 5.0V15pF C OUTOutput Capacitance15pFPullup/Pulldown Current - All SignalsParametersDescriptionTest ConditionsTyp.Max.I PU Input Pullup Current T A = –55°C, V CC = 5.5V V IN = GND100 µA 250 µA I PUInput Pullup CurrentT A = –55°C, V CC = 5.5V V IN = V CC100 µA250 µAOperating Current (CY7C960/CY7C961)ParametersDescription Test ConditionsMax.Units I DDMaximum Operating Current No external DC load100mAOrdering InformationOrdering Code Package Name Package TypeOperating Range CY7C960-ASC A6410x10 mm body 64-Lead Plastic Thin Quad Flatpack CommercialCY7C960-NC N6514x14 mm body 64-Lead Plastic Thin Quad Flatpack CY7C960-UM U6514x14 mm body 64 lead Ceramic Quad Flatpack Military CY7C960-UMB U6514x14 mm body 64 lead Ceramic Quad FlatpackOrdering Code Package Name Package TypeOperating Range CY7C961-NCA10014x14 mm body 100-Lead Plastic Thin Quad Flatpack CommercialWindows is a trademark of Microsoft Corporation.Document #: 38-00250-DPackage Diagrams64-Pin Thin Quad Flatpack A64Package Diagrams (continued)100-Pin Thin Quad Flatpack A100Package Diagrams (continued)64-Lead Plastic Thin Quad Flatpack N65Package Diagrams (continued)64-Lead Ceramic Quad Flatpack(Cavity Up)U65© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress。
CY7C63723-PC中文资料
元器件交易网CY7C63743CY7C63722/23CY7C63743enCoRe™ USBCombination Low-Speed USB & PS/2Peripheral ControllerTABLE OF CONTENTS1.0 FEATURES (5)2.0 FUNCTIONAL OVERVIEW (6)2.1 enCoRe USB - The New USB Standard (6)3.0 LOGIC BLOCK DIAGRAM (7)4.0 PIN CONFIGURATIONS (7)5.0 PIN ASSIGNMENTS (7)6.0 PROGRAMMING MODEL (8)6.1 Program Counter (PC) (8)6.2 8-bit Accumulator (A) (8)6.3 8-bit Index Register (X) (8)6.4 8-bit Program Stack Pointer (PSP) (8)6.5 8-bit Data Stack Pointer (DSP) (9)6.6 Address Modes (9)6.6.1 Data (9)6.6.2 Direct (9)6.6.3 Indexed (9)7.0 INSTRUCTION SET SUMMARY (10)8.0 MEMORY ORGANIZATION (11)8.1 Program Memory Organization (11)8.2 Data Memory Organization (12)8.3 I/O Register Summary (13)9.0 CLOCKING (14)9.1 Internal/External Oscillator Operation (15)9.2 External Oscillator (16)10.0 RESET (16)10.1 Low-voltage Reset (LVR) (16)10.2 Brown Out Reset (BOR) (16)10.3 Watchdog Reset (WDR) (17)11.0 SUSPEND MODE (17)11.1 Clocking Mode on Wake-up from Suspend (18)11.2 Wake-up Timer (18)12.0 GENERAL PURPOSE I/O PORTS (18)12.1 Auxiliary Input Port (21)13.0 USB SERIAL INTERFACE ENGINE (SIE) (22)13.1 USB Enumeration (22)13.2 USB Port Status and Control (22)14.0 USB DEVICE (24)14.1 USB Address Register (24)14.2 USB Control Endpoint (24)14.3 USB Non-control Endpoints (25)14.4 USB Endpoint Counter Registers (26)15.0 USB REGULATOR OUTPUT (27)16.0 PS/2 OPERATION (27)17.0 SERIAL PERIPHERAL INTERFACE (SPI) (28)17.1 Operation as an SPI Master (29)17.2 Master SCK Selection (29)17.3 Operation as an SPI Slave (29)17.4 SPI Status and Control (30)17.5 SPI Interrupt (31)17.6 SPI Modes for GPIO Pins (31)18.0 12-BIT FREE-RUNNING TIMER (31)19.0 TIMER CAPTURE REGISTERS (32)20.0 PROCESSOR STATUS AND CONTROL REGISTER (35)21.0 INTERRUPTS (36)21.1 Interrupt Vectors (37)21.2 Interrupt Latency (37)21.3 Interrupt Sources (37)22.0 USB MODE TABLES (42)23.0 REGISTER SUMMARY (47)24.0 ABSOLUTE MAXIMUM RATINGS (48)25.0 DC CHARACTERISTICS (48)26.0 SWITCHING CHARACTERISTICS (50)27.0 ORDERING INFORMATION (55)28.0 PACKAGE DIAGRAMS (55)LIST OF FIGURESFigure 8-1. Program Memory Space with Interrupt Vector Table (11)Figure 8-2. Data Memory Organization (12)Figure 9-1. Clock Oscillator On-chip Circuit (14)Figure 9-2. Clock Configuration Register (Address 0xF8) (14)Figure 10-1. Watchdog Reset (WDR, Address 0x26) (17)Figure 12-1. Block Diagram of GPIO Port (one pin shown) (19)Figure 12-2. Port 0 Data (Address 0x00) (19)Figure 12-3. Port 1 Data (Address 0x01) (19)Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A) (20)Figure 12-5. GPIO Port 0 Mode1 Register (Address 0x0B) (20)Figure 12-6. GPIO Port 1 Mode0 Register (Address 0x0C) (20)Figure 12-7. GPIO Port 1 Mode1 Register (Address 0x0D) (20)Figure 12-8. Port 2 Data Register (Address 0x02) (21)Figure 13-1. USB Status and Control Register (Address 0x1F) (23)Figure 14-1. USB Device Address Register (Address 0x10) (24)Figure 14-2. Endpoint 0 Mode Register (Address 0x12) (25)Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14 and 0x16) (26)Figure 14-4. Endpoint 0,1,2 Counter Registers (Addresses 0x11, 0x13 and 0x15) (26)Figure 17-1. SPI Block Diagram (28)Figure 16-1. Diagram of USB-PS/2 System Connections (28)Figure 17-2. SPI Data Register (Address 0x60) (29)Figure 17-3. SPI Control Register (Address 0x61) (30)Figure 17-4. SPI Data Timing (31)Figure 18-1. Timer LSB Register (Address 0x24) (31)Figure 18-2. Timer MSB Register (Address 0x25) (32)Figure 18-3. Timer Block Diagram (32)Figure 19-1. Capture Timers Block Diagram (33)Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) (33)Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) (34)Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) (34)Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) (34)Figure 19-6. Capture Timer Status Register (Address 0x45) (34)Figure 19-7. Capture Timer Configuration Register (Address 0x44) (34)Figure 20-1. Processor Status and Control Register (Address 0xFF) (35)Figure 21-1. Global Interrupt Enable Register (Address 0x20) (38)Figure 21-2. Endpoint Interrupt Enable Register (Address 0x21) (39)Figure 21-3. Interrupt Controller Logic Block Diagram (40)Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) (40)Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) (40)Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) (41)Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) (41)Figure 21-8. GPIO Interrupt Diagram (41)Figure 26-1. Clock Timing (51)Figure 26-2. USB Data Signal Timing (51)Figure 26-3. Receiver Jitter Tolerance (52)Figure 26-4. Differential to EOP Transition Skew and EOP Width (52)Figure 26-5. Differential Data Jitter (52)Figure 26-7. SPI Slave Timing, CPHA = 0 (53)Figure 26-6. SPI Master Timing, CPHA = 0 (53)Figure 26-8. SPI Master Timing, CPHA = 1 (54)Figure 26-9. SPI Slave Timing, CPHA = 1 (54)LIST OF TABLESTable 8-1. I/O Register Summary (13)Table 11-1. Wake-up Timer Adjust Settings (18)Table 12-1. Ports 0 and 1 Output Control Truth Table (21)Table 13-1. Control Modes to Force D+/D– Outputs (24)Table 17-1. SPI Pin Assignments (31)Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) (35)Table 21-1. Interrupt Vector Assignments (37)Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints (42)Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” (44)Table 22-3. Details of Modes for Differing Traffic Conditions (45)Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) (57)1.0 Features•enCoRe™ USB - enhanced Component Reduction—Internal oscillator eliminates the need for an external crystal or resonator—Interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes (no GPIO pins needed to manage dual mode capability)—Internal 3.3V regulator for USB pull-up resistor—Configurable GPIO for real-world interface without external components•Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads, joysticks, and many others.•USB Specification Compliance—Conforms to USB Specification, Version 2.0—Conforms to USB HID Specification, Version 1.1—Supports 1 Low-Speed USB device address and 3 data endpoints—Integrated USB transceiver—3.3V regulated output for USB pull-up resistor•8-bit RISC microcontroller—Harvard architecture—6-MHz external ceramic resonator or internal clock mode—12-MHz internal CPU clock—Internal memory—256 bytes of RAM—8 Kbytes of EPROM—Interface can auto-configure to operate as PS/2 or USB—No external components for switching between PS/2 and USB modes—No GPIO pins needed to manage dual mode capability•I/O ports—Up to 16 versatile General Purpose I/O (GPIO) pins, individually configurable—High current drive on any GPIO pin: 50 mA/pin current sink—Each GPIO pin supports high-impedance inputs, internal pull-ups, open drain outputs or traditional CMOS outputs —Maskable interrupts on all I/O pins•SPI serial communication block—Master or slave operation—2 Mbit/s transfers•Four 8-bit Input Capture registers—Two registers each for two input pins—Capture timer setting with 5 prescaler settings—Separate registers for rising and falling edge capture—Simplifies interface to RF inputs for wireless applications•Internal low-power wake-up timer during suspend mode—Periodic wake-up with no external components•Optional 6-MHz internal oscillator mode—Allows fast start-up from suspend mode•Watchdog Reset (WDR)•Low-voltage Reset at 3.75V•Internal brown-out reset for suspend mode•Improved output drivers to reduce EMI•Operating voltage from 4.0V to 5.5VDC•Operating temperature from 0 to 70 degrees Celsius•CY7C63723 available in 18-pin SOIC, 18-pin PDIP•CY7C63743 available in 24-pin SOIC, 24-pin PDIP•CY7C63722 available in DIE form•Industry standard programmer support2.0 Functional Overview2.1enCoRe USB - The New USB StandardCypress has re-invented its leadership position in the low-speed USB market with a new family of innovative microcontrollers. Introducing...enCoRe USB—“enhanced Component Reduction.” Cypress has leveraged its design expertise in USB solutions to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a minimum number of components. At the heart of the enCoRe USB technology is the breakthrough design of a crystal-less oscillator. By integrating the oscillator into our chip, an external crystal or resonator is no longer needed. We have also integrated other external components commonly found in low-speed USB applications such as pull-up resistors, wake-up circuitry, and a 3.3V regulator. All of this adds up to a lower system cost.The CY7C637xx is an 8-bit RISC One Time Programmable (OTP) microcontroller. The instruction set has been optimized specif-ically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The CY7C637xx features up to 16 general purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into two ports (Port 0 to 1) where each pin can be individually configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs with programmable drive strength of up to 50 mA output drive. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C637xx microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (6 MHz ±1.5%). Optionally, an external 6-MHz ceramic resonator can be used to provide a higher precision reference for USB operation. This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that remain internal to the microcontroller.The CY7C637xx has 8 Kbytes of EPROM and 256 bytes of data RAM for stack space, user variables, and USB FIFOs.These parts include low-voltage reset logic, a watchdog timer, a vectored interrupt controller, a 12-bit free-running timer, and capture timers. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V CC drops below the operating voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms. The microcontroller supports 10 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus-Reset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, two capture timers, an internal wake-up timer and the GPIO ports. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. The GPIO ports have a level of masking to select which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each GPIO pin. The interrupt polarity can be either rising or falling edge.The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources as noted above (128 µs and 1.024 ms). The timer can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event, and subtracting the two values. The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1).The CY7C637xx includes an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V regulated output pin provides a pull-up source for the external USB resistor on the D– pin.The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and SDATA, the ability to disable the regulator output pin, and an interrupt to signal the start of PS/2 activity. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. Slow edge rates operate in both modes to reduce EMI.3.0 Logic Block Diagram4.0 Pin Configurations5.0 Pin AssignmentsNameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-Pad D–/SDATA,D+/SCLK I/O 121315161617USB differential data lines (D– and D+), or PS/2 clock and data signals (SDATA and SCLK)P0[7:0]I/O1, 2, 3, 4,15, 16, 17, 181, 2, 3, 4,21, 22, 23, 241, 2, 3, 4,22, 23, 24, 25GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current.Can also source 2 mA current, provide a resistive pull-up, or serve as a high-impedance input. P0.0 and P0.1 provide inputs to Capture Timers A and B, respec-tively.P1[7:0]I/O5, 145, 6, 7, 8,17, 18, 19, 205, 6, 7, 8,18, 19, 20, 21IO Port 1 capable of sinking up to 50 mA/pin, or sinking controlled low or high programmable current. Can alsosource 2 mA current, provide a resistive pull-up, or serve as a high-impedance input.Wake-Up 12-bit Timer USB &D+,D–P1.0–P1.7Interrupt ControllerPort 0P0.0–P0.7GPIO8-bit RISC Xtal RAM 256 Byte EPROM 8K ByteCoreBrown-out Reset XcvrWatch Timer Dog 3.3V Port 1GPIO Capture TimersUSB Engine PS/2Internal Oscillator Oscillator Low ResetVoltage RegulatorTimerSPIXTALOUTXTALIN/P2.1VREG/P2.01234569111516171819202221P0.0P0.1P0.2P0.3P1.0P1.2VSS VREG/P2.0P0.6P1.5P1.1P1.3D+/SCLK P1.7D–/SDATA VCC14P0.710VPPXTALIN/P2.1XTALOUT121378P1.4P1.62423P0.4P0.524-pin SOIC/PDIPCY7C6374312346781011121315161817P0.0P0.1P0.2P0.3VSS VREG/P2.0P0.4P0.6P0.7D+/SCLK D–/SDATA VCC18-pin SOIC/PDIPP0.59VPPXTALIN/P2.1XTALOUTCY7C63723514P1.0P1.1Top View4 5 6 7 8 93 P 0.21 P 0.0 2 P 0.125 P 0.4 24 P 0.523 P 0.622 21 20 19 1811121314151617P0.3P1.0P1.2P1.4P1.6 VSS VSS V P P X T A L I N /P 2.1V R E G X T A L O U T V C C D -/S D A T A D+/SCLK P0.7P1.1P1.3P1.5P1.7CY7C63722-XCDIE106.0 Programming ModelRefer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xx microcontrollers.6.1Program Counter (PC)The 14-bit program counter (PC) allows access for up to 8 Kbytes of EPROM using the CY7C637xx architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This instruction is typically a jump instruction to a reset handler that initializes the application.The lower 8 bits of the program counter are incremented as instructions are loaded and executed. The upper 6 bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE for correct execution.The program counter of the next instruction to be executed, carry flag, and zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack only during a RETI instruction.Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.6.28-bit Accumulator (A)The accumulator is the general-purpose, do everything register in the architecture where results are usually calculated.6.38-bit Index Register (X)The index register “X” is available to the firmware as an auxiliary accumulator. The X register also allows the processor to perform indexed operations by loading an index value into X.6.48-bit Program Stack Pointer (PSP)During a reset, the program stack pointer (PSP) is set to zero. This means the program “stack” starts at RAM address 0x00 and “grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV PSP ,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware control.During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again. The net effect is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory addressed by the PSP . The program stack pointer is decremented again and the first byte is restored from memory addressed by the PSP . After the program counter and flags have been restored from stack, the interrupts are enabled. The effect is to restore the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.The call subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by two.XTALIN/P2.1IN 912136-MHz ceramic resonator or external clock input, or P2.1 inputXTALOUT OUT1013146-MHz ceramic resonator return pin or internal oscillator outputV PP 71011Programming voltage supply, ground for normal operation V CC111415Voltage supplyVREG/P2.0 81112Voltage supply for 1.3-k Ω USB pull-up resistor (3.3V nominal). Also serves as P2.0 input.V SS699, 10Ground5.0 Pin Assignments (continued)NameI/O CY7C63723CY7C63743CY7C63722Description18-Pin 24-Pin 25-PadThe return from subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decrements the PSP by two.Note that there are restrictions in using the JMP, CALL, and INDEX instructions across the 4-KB boundary of the program memory. Refer to the CYASM Assembler User’s Guide for a detailed description.6.58-bit Data Stack Pointer (DSP)The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction will pre-decrement the DSP, then write data to the memory location addressed by the DSP. A POP instruction will read data from the memory location addressed by the DSP, then post-increment the DSP.During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB applications, this works fine and is not a problem.For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to set the DSP to 20h (giving 32 bytes for program and data stack combined) are shown below:MOV A,20h; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)SWAP A,DSP; swap accumulator value into DSP register6.6Address ModesThe CY7C637xx microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.6.6.1DataThe “Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0x30:•MOV A, 30hThis instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:•DSPINIT: EQU 30h•MOV A,DSPINIT6.6.2Direct“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10h:•MOV A, [10h]In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:•buttons: EQU 10h•MOV A,[buttons]6.6.3Indexed“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the “base” address of an array of data and the X register will contain an index that indicates which element of the array is actually addressed:•array: EQU 10h•MOV X,3•MOV A,[x+array]This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth element would be at address 0x13h.7.0 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for detailed information on these instructions. Note that conditional jump instructions (i.e., JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.MNEMONIC Operand Opcode Cycles MNEMONIC Operand Opcode Cycles HALT 007NOP 204ADD A,expr data014INC A acc214ADD A,[expr] direct026INC X x224ADD A,[X+expr] index037INC [expr] direct237ADC A,expr data044INC [X+expr] index248ADC A,[expr] direct056DEC A acc254ADC A,[X+expr] index067DEC X x264SUB A,expr data074DEC [expr] direct277SUB A,[expr] direct086DEC [X+expr] index288SUB A,[X+expr] index097IORD expr address295SBB A,expr data0A4IOWR expr address2A5SBB A,[expr] direct0B6POP A2B4SBB A,[X+expr] index0C7POP X2C4OR A,expr data0D4PUSH A2D5OR A,[expr] direct0E6PUSH X2E5OR A,[X+expr] index0F7SWAP A,X2F5AND A,expr data104SWAP A,DSP305AND A,[expr] direct116MOV [expr],A direct315AND A,[X+expr] index127MOV [X+expr],A index326XOR A,expr data134OR [expr],A direct337XOR A,[expr] direct146OR [X+expr],A index348XOR A,[X+expr] index157AND [expr],A direct357CMP A,expr data165AND [X+expr],A index368CMP A,[expr] direct177XOR [expr],A direct377CMP A,[X+expr] index188XOR [X+expr],A index388MOV A,expr data194IOWX [X+expr] index396MOV A,[expr] direct1A5CPL 3A4MOV A,[X+expr] index1B6ASL 3B4MOV X,expr data1C4ASR 3C4MOV X,[expr] direct1D5RLC 3D4reserved 1E RRC 3E4XPAGE 1F4RET 3F8MOV A,X404DI 704MOV X,A414EI 724MOV PSP,A604RETI 738CALL addr50 - 5F10JMP addr80-8F5JC addr C0-CF 5 (or 4) CALL addr90-9F10JNC addr D0-DF 5 (or 4)JZ addr A0-AF 5 (or 4)JACC addr E0-EF7JNZ addr B0-BF 5 (or 4)INDEX addr F0-FF148.0 Memory Organization8.1Program Memory Organization[1]After reset Address14 -bit PC0x0000Program execution begins here after a reset.0x0002USB Bus Reset interrupt vector0x0004128-µs timer interrupt vector0x0006 1.024-ms timer interrupt vector0x0008USB endpoint 0 interrupt vector0x000A USB endpoint 1 interrupt vector0x000C USB endpoint 2 interrupt vector0x000E SPI interrupt vector0x0010Capture timer A interrupt Vector0x0012Capture timer B interrupt vector0x0014GPIO interrupt vector0x0016Wake-up interrupt vector0x0018Program Memory begins here0x1FDF8 KB PROM ends here (8K - 32 bytes). See Note below Figure 8-1. Program Memory Space with Interrupt Vector TableNote:1.The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this space.8.2Data Memory OrganizationThe CY7C637xx microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below:After reset Address8-bit DSP8-bit PSP0x00Program Stack Growth(User’s firmware movesDSP)8-bit DSP User Selected Data Stack GrowthUser Variables0xE8USB FIFO for Address A endpoint 20xF0USB FIFO for Address A endpoint 10xF8USB FIFO for Address A endpoint 0Top of RAM Memory0xFFFigure 8-2. Data Memory Organization8.3I/O Register SummaryI/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.Note:All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure20-1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be written as 0 and be treated as undefined by reads.Table 8-1. I/O Register SummaryRegister Name I/O Address Read/Write Function Fig. Port 0 Data0x00R/W GPIO Port 012-2 Port 1 Data0x01R/W GPIO Port 112-3 Port 2 Data0x02R Auxiliary input register for D+, D–, VREG, XTALIN 12-8 Port 0 Interrupt Enable0x04W Interrupt enable for pins in Port 021-4 Port 1 Interrupt Enable0x05W Interrupt enable for pins in Port 121-5 Port 0 Interrupt Polarity 0x06W Interrupt polarity for pins in Port 021-6 Port 1 Interrupt Polarity 0x07W Interrupt polarity for pins in Port 121-7 Port 0 Mode0 0x0A W Controls output configuration for Port 012-4 Port 0 Mode10x0B W12-5 Port 1 Mode00x0C W Controls output configuration for Port 112-6 Port 1 Mode10x0D W12-7 USB Device Address0x10R/W USB Device Address register14-1 EP0 Counter Register0x11R/W USB Endpoint 0 counter register14-4 EP0 Mode Register0x12R/W USB Endpoint 0 configuration register14-2 EP1 Counter Register0x13R/W USB Endpoint 1 counter register14-4 EP1 Mode Register0x14R/W USB Endpoint 1 configuration register14-3 EP2 Counter Register0x15R/W USB Endpoint 2 counter register14-4 EP2 Mode Register0x16R/W USB Endpoint 2 configuration register14-3 USB Status & Control0x1F R/W USB status and control register13-1 Global Interrupt Enable0x20R/W Global interrupt enable register21-1 Endpoint Interrupt Enable0x21R/W USB endpoint interrupt enables21-2 Timer (LSB)0x24R Lower 8 bits of free-running timer (1 MHz)18-1 Timer (MSB)0x25R Upper 4 bits of free-running timer18-2 WDR Clear0x26W Watchdog Reset clear-Capture Timer A Rising0x40R Rising edge Capture Timer A data register19-2 Capture Timer A Falling0x41R Falling edge Capture Timer A data register19-3 Capture Timer B Rising0x42R Rising edge Capture Timer B data register19-4 Capture Timer B Falling0x43R Falling edge Capture Timer B data register19-5 Capture TImer Configuration0x44R/W Capture Timer configuration register19-7 Capture Timer Status0x45R Capture Timer status register19-6 SPI Data0x60R/W SPI read and write data register17-2 SPI Control0x61R/W SPI status and control register17-3 Clock Configuration0xF8R/W Internal / External Clock configuration register9-2 Processor Status & Control0xFF R/W Processor status and control20-1。
CY7C1411AV18资料
Errata Revision: *CMay 02, 2007RAM9 QDR-I/DDR-I/QDR-II/DDR- II ErrataCY7C129*DV18/CY7C130*DV25CY7C130*BV18/CY7C130*BV25/CY7C132*BV25CY7C131*BV18 / CY7C132*BV18/CY7C139*BV18CY7C191*BV18/CY7C141*AV18 / CY7C142*AV18/CY7C151*V18 /CY7C152*V18This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for QDRI/DDRI/QDRII/DDRII. Details include trigger conditions, possible workarounds and silicon revision applicability.This document should be used to compare to the respective datasheet for the devices to fully describe the device functionality.Please contact your local Cypress Sales Representative for availability of the fixed devices and any other questions.Devices AffectedTable 1. List of Affected devicesProduct StatusAll of the above densities and revisions are available in sample as well as production quantities.QDR/DDR DOFF Pin, Output Buffer and JTAG Issues Errata SummaryThe following table defines the issues and the fix status for the different devices which are affected.Density & Revision Part Numbers Architecture 9Mb - Ram9(90 nm)CY7C130*DV25QDRI/DDRI 9Mb - Ram9(90 nm)CY7C129*DV18QDRII 18Mb - Ram9(90nm)CY7C130*BV18CY7C130*BV25CY7C132*BV25QDRI/DDRI18Mb - Ram9(90nm)CY7C131*BV18CY7C132*BV18CY7C139*BV18CY7C191*BV18QDRII/DDRII36Mb - Ram9(90nm)CY7C141*AV18CY7C142*AV18QDRII/DDRII 72Mb -Ram9(90nm)CY7C151*V18CY7C152*V18QDRII/DDRIIItemIssueDeviceFix Status1.DOFF pin is used for enabling/dis-abling the DLL circuitry within the SRAM. To enable the DLL circuitry, DOFF pin must be externally tied HIGH. The QDR-II/DDR-II devices have an internal pull down resistor of ~5K . The value of the external pull-up resistor should be 500 or less in order to ensure DLL is enabled.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-II/DDR-II DevicesThe fix involved removing the in-ternal pull-down resistor on the DOFF pin. The fix has been im-plemented on the new revision and is now available.ΩΩTable 2.Issue Definition and fix status for different devices1. DOFF Pin Issue•ISSUE DEFINITIONThis issue involves the DLL not turning ON properly if a large resistor is used (eg:-10K ) as an external pullup resistor to enable the DLL. If a 10K or higher pullup resistor is used externally, the voltage on DOFF is not high enough to enable the DLL.•PARAMETERS AFFECTEDThe functionality of the device will be affected because of the DLL is not turning ON properly. When the DLL is enabled, all AC and DC parameters on the datasheet are met. •TRIGGER CONDITION(S)Having a 10K or higher external pullup resistor for disabling the DOFF pin.•SCOPE OF IMPACTThis issue will alter the normal functionality of the QDRII/DDRII devices when the DLL is disabled.•EXPLANATION OF ISSUEFigure 1 shows the DOFF pin circuit with an internal 5K internal resistor. The fix planned is to disable the internal 5K leaker.•WORKAROUND2.O/P Buffer enters a locked up unde-fined state after controls or clocks are left floating. No proper read/write access can be done on the device until a dummy read is performed.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II Devices The fix has been implemented onthe new revision and is now avail-able.3.The EXTEST function in the JTAG test fails when input K clock is floating in the JTAG mode.9Mb - “D” Rev - Ram918Mb - “B” Rev - Ram936Mb - “A” Rev - Ram972Mb - Ram9QDR-I/DDR-I/QDR-II/DDR-II DevicesThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuit-ry by the JTAG signal. The fix has been implemented on the new re-vision and is now available.Figure 1.DOFF pin with the 5K internal resistorItemIssueDeviceFix StatusΩΩΩΩΩΩThe workaround is to have a low value of external pullup resistor for the DOFF pin (recommended value is <500). When DOFF pins from multiple QDR devices are connected through the same pull-up resistors on the board, it is recommended that this DOFF pin be directly connected to Vdd due to the lower effective resistance since the "leakers" are in parallel.Figure 2 shows the proposed workaround and the fix planned.•FIXSTATUSFix involved removing the internal pull-down resistor on the DOFF pin. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. The following table lists the devices affected, current revision and the new revision after the fix.Table 3.List of Affected Devices and the new revison2.Output Buffer IssueFigure 2.Proposed workaround with the 500 external pullupCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ΩΩ•ISSUE DEFINITIONThis issue involves the output buffer entering an unidentified state when the input signals (only Control signals or Clocks) are floating during reset or initialization of the memory controller after power up. •PARAMETERS AFFECTEDNo timing parameters are affected. The device may drive the outputs even though the read operation is not enabled. A dummy read is performed to clear this condition.•TRIGGER CONDITION(S)Input signals(namely RPS# for QDR-I/QDRII , WE# and LD# for DDR-I/DDRII) or Clocks (K/K# and/or C/C#) are floating during reset or initialization of the memory controller after power up.•SCOPE OF IMPACTThis issue will jeopardize any number of writes or reads which take place after the controls or clock are left floating. This can occur anywhere in the SRAM access ( all the way from power up of the memory device to transitions taking place for read/write accesses to the memory device) if the above trigger conditions are met.•EXPLANATION OF ISSUEFigure 3 shows the output register Reset circuit with an SR Latch circled. This latch has two inputs with one of them coming from some logic affected by the clock and RPS#(QDR) or WE# and LD#(DDR).The issue happens when clocks are glitching/toggling with controls floating. This will cause the SR latch to be taken into an unidentified state. The SR Latch will need to be reset by a dummy read operation if this happens. Array•WORKAROUNDThis is viable only if the customer has the trigger conditions met during reset or initialization of the memory controller after power up. In order for the workaround to perform properly, Cypress recommends the insertion of a minimum of 16 “dummy” READ operations to every SRAM device on the board prior to writing any meaningful data into the SRAM. After this one “dummy” READ operation, the device will perform properly.“Dummy” READ is defined as a read operation to the device that is not meant to retrieve required data. The “dummy” READ can be to any address location in the SRAM. Refer to Figure 4 for the dummy read implemen-tation.In systems where multiple SRAMs with multiple RPS# lines are used, a dummy read operation will have to be performed on every SRAM on the board. Below is an example sequence of events that can be performed before valid access can be performed on the SRAM.1) Initialize the Memory Controller2) Assert RPS# Low for each of the memory devicesNote:For all devices with x9 bus configuration, the following sequence needs to be performed:1) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 low respectively and perform dummyread.2) For the 72M / 36M / 18M x9 devices drive address pin A2 / A10 / A3 high respectively and perform dummyread.If the customer has the trigger conditions met during normal access to the memory then there is no workaround at this point.•FIX STATUSThe fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix.3. JTAG Mode Issue•ISSUE DEFINITIONIf the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on this input can be interpreted by the device as valid clocks. This could cause the impedance matching circuitry (ZQ) on the QDR/DDR devices to periodically load itself with incorrect values. These incorrect values in the ZQ register could force the outputs into a High-Impedance state. The ZQ circuitry requires at least 1000 valid K clock cycles to drive the outputs from high impedance to low impedance levels.•PARAMETERS AFFECTEDThis issue only affects the EXTEST command when the device is in the JTAG mode. The normal functionality of the device will not be affected.•TRIGGER CONDITION(S)EXTEST command executed immediately after power-up without providing any K clock cycles.•SCOPE OF IMPACTThis issue only impacts the EXTEST command when device is tested in the JTAG mode. Normal functionality of the device is not affected. •EXPLANATION OF ISSUEImpedance matching circuitry (ZQ) is present on the QDR/DDR devices to set the desired impedance on the outputs. This ZQ circuitry is updated every 1000 clock cycles of K clock to ensure that the impedance of the O/P is set to valid state. However, when the device is operated in the JTAG mode immediately after power-up, high frequency noise on the input K clock can be treated by the ZQ circuitry as valid clocks thereby setting the outputs in to a high-impedance mode. If a minimum of 1000 valid K clocks are applied before performing the JTAG test, this should clear the ZQ circuitry and ensure that the outputs are driven to valid impedance levels.•WORKAROUNDElimination of the issue: After power-up, before any valid operations are performed on the device, insert a minimum of 1000 valid clocks on K input.•FIX STATUSThe fix involved bypassing the ZQ circuitry in JTAG mode. This was done by overriding the ZQ circuitry by the JTAG signal. The fix has been implemented on the new revision and is now available. The new revision is an increment of the existing revision. Please refer to Table 4 for the list of devices affected, current revision and the new revision after the fix..Table 4.List of Affected devices and the new revisionCurrent Revision New Revision after the FixCY7C129*DV18CY7C129*EV18CY7C130*DV25CY7C130*EV25CY7C130*BV18CY7C130*CV18CY7C130*BV25CY7C130*CV25CY7C132*BV25CY7C132*CV25CY7C131*BV18CY7C131*CV18CY7C132*BV18CY7C132*CV18CY7C139*BV18CY7C139*CV18CY7C191*BV18CY7C191*CV18CY7C141*AV18CY7C141*BV18CY7C142*AV18CY7C142*BV18CY7C151*V18CY7C151*AV18CY7C152*V18CY7C152*AV18ReferencesAll 90nm QDRI/DDRI/QDRII/DDRII datasheets:-Table 5.List of Datasheet spec# for the Affected devicesSpec#Part#DensityArchitecture38-05628CY7C1304DV259-MBIT QDR(TM) SRAM 4-WORD BURST 38-05632CY7C1308DV259-MBIT DDR-I SRAM 4-WORD BURST 001-00350CY7C1292DV18/1294DV189-MBIT QDR- II(TM) SRAM 2-WORD BURST 38-05621CY7C1316BV18/1916BV18/1318BV18/1320BV1818-MBIT DDR-II SRAM 2-WORD BURST 38-05622CY7C1317BV18/1917BV18/1319BV18/1321BV1818-MBIT DDR-II SRAM 4-WORD BURST 38-05623CY7C1392BV18/1393BV18/1394BV1818-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05631CY7C1323BV2518-MBIT DDR-I SRAM 4-WORD BURST 38-05630CY7C1305BV25/1307BV2518-MBIT QDR(TM) SRAM 4-WORD BURST 38-05627CY7C1303BV25/1306BV2518-MBIT QDR(TM) SRAM 2-WORD BURST 38-05629CY7C1305BV18/1307BV1818-MBIT QDR(TM) SRAM 4-WORD BURST 38-05626CY7C1303BV18/1306BV1818-MBIT QDR(TM) SRAM 2-WORD BURST 38-05619CY7C1310BV18/1910BV18/1312BV18/1314BV1818-MBIT QDR - II (TM) SRAM 2-WORD BURST 38-05620CY7C1311BV18/1911BV18/1313BV18/1315BV1818-MBIT QDR - II SRAM 4-WORD BURST 38-05615CY7C1410AV18/1425AV18/1412AV18/1414AV1836-MBIT QDR-II(TM) SRAM 2-WORD BURST 38-05614CY7C1411AV18/1426AV18/1413AV18/1415AV1836-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05616CY7C1416AV18/1427AV18/1418AV18/1420AV1836-MBIT DDR-II SRAM 2-WORD BURST 38-05618CY7C1417AV18/1428AV18/1419AV18/1421AV1836-MBIT DDR-II SRAM 4-WORD BURST 38-05617CY7C1422AV18/1429AV18/1423AV18/1424AV1836-MBIT DDR-II SIO SRAM 2-WORD BURST 38-05489CY7C1510V18/1525V18/1512V18/1514V1872-MBIT QDR-II SRAM 2-WORD BURST 38-05363CY7C1511V18/1526V18/1513V18/1515V1872-MBIT QDR(TM)-II SRAM 4-WORD BURST 38-05563CY7C1516V18/1527V18/1518V18/1520V1872-MBIT DDR-II SRAM 2-WORD BURST 38-05565CY7C1517V18/1528V18/1519V18/1521V1872-MBIT DDR-II SRAM 4-WORD BURST 38-05564CY7C1522V18/1529V18/1523V18/1524V1872-MBITDDR-II SIO SRAM 2-WORD BURSTDocument History PageDocument Title: RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata Document #: 001-06217 Rev. *CREV.ECN NO.IssueDateOrig. ofChange Description of Change**419849See ECN REF New errata for Ram9 QDR2/DDR2 SRAMs.*A493936See ECN QKS Added Output buffer and JTAG mode issues, Item#2 and #3Added 9Mb QDR-II Burst of 2 and QDR-1/DDR-I part numbers.*B733176See ECN NJY Added missing part numbers in the title for Spec#’s 38-05615,38-05614,38-05363,38-05563 on Table 5 on page 7.*C1030020 See ECN TBE Updated the fix status of the three issues, and modified the description forthe Output Buffer workaround for x9 devices on page 5.。
CY7C144AV资料
IDT70V05, 70V06, and 70V07.
R/WR
CER
OER
[1]
8/9
I/O0L–I/O7/8L
I/O Control
Pin Configurations (continued)
68-Pin PLCC Top View
CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV
CY7C007AV/017AV
L
A9L A8L A7L A6L
NC VCC A12L A11L A10L
NC
SEM CEL
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
A5L A4L A3L A2L A1L A0L INTL BUSYL GND
M/S BUSYR
INTR A0R
A1R A2R
A3R A4R
I/O7R NC [4]
M/S
Notes:
1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices; 3. BUSY is an output in master mode and an input in slave mode.
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BWC
MEMORY ARRAY
SENSE AMPS
OUTPUT BUFFERS
DQs DQPA DQPB DQPC DQPD
ENABLE REGISTER
INPUT REGISTERS
ZZ
SLEEP CONTROL
1
Logic Block Diagram – CY7C1363C (512K x 18)
PRELIMINARY
Logic Block Diagram – CY7C1361C (256K x 36)
A0, A1, A
CY7C1361C CY7C1363C
ADDRESS REGISTER A[1:0]
MODE
ADV CLK
BURST Q1 COUNTER AND LOGIC Q0 CLR
ADSC ADSP DQD, DQPD BWD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BYTE WRITE REGISTER DQA, DQPA BWA BWE GW CE1 CE2 CE3 OE DQA, DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BWB BYTE WRITE REGISTER
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Cypress Semiconductor Corporation Document #: 38-05541 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
• 408-943-2600 Revised October 5, 2004
元器件交易网
A0,A1,A MODE
ADDRESS REGISTER
A[1:0]
ADV CLK
BURST Q1 COUNTER AND LOGIC CLR Q0
ADSC
ADSP DQB,DQPB WRITE REGISTER DQB,DQPB WRITE DRIVER
BWB
MEMORY ARRAY
SENSE AMPS
Page 2 of 30
元器件交易网
PRELIMINARY
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables) (A version)
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB VSS/DNU VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 250 30 117 MHz 7.5 220 30 100 MHz 8.5 180 30 Unit ns mA mA
Functional Description[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1361C/CY7C1363C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1361C/CY7C1363C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on . 2. CE3 is for A version of TQFP ( 3 Chip Enable Option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
元器件交易网
PRELIMINARY
CY7C1361C CY7C1363C
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Features
• Supports 133-MHz bus operations • 256K × 36/512K × 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.5 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Available in Lead-Free 100 TQFP,119 BGA and 165 fBGA packages Both 2 and 3 Chip Enable Options for TQFP • IEEE 1149.1 compatible JTAG Boundary Scan for BGA and fBGA packages •“ZZ” Sleep Mode option