CAT5113PI-10MSOP中文资料
SPMC65P2204A_2202A_数据手册_V1.1

SPMC65P2204A/2202A
目录
頁次
1. 总述.............................................................................................................................................................................................................. 4 2. 特性.............................................................................................................................................................................................................. 4 3. 芯片结构概览 ............................................................................................................................................................................................... 5 4. 信号描述....................................................................................................................................................................................................... 6
NCP511SN33资料

NCP511150 mA CMOS Low Iq Low-Dropout Voltage RegulatorThe NCP511 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent current. The NCP511 series features an ultra–low quiescent current of 40 m A. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits.The NCP511 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 m F. The device is housed in the micro–miniature TSOP–5 surface mount package. Standard voltage versions are 1.5, 1.8, 2.7, 2.8, 3.0, 3.3, and 5.0 V . Other voltages are available in 100 mV steps.Features•Low Quiescent Current of 40 m A Typical •Low Dropout V oltage of 100 mV at 100 mA •Excellent Line and Load Regulation •Maximum Operating V oltage of 6.0 V •Low Output V oltage Option•High Accuracy Output V oltage of 2.0%•Industrial Temperature Range of –40°C to 85°C Typical Applications•Cellular Phones•Battery Powered Instruments •Hand–Held Instruments •Camcorders and CamerasV inV outEnable OFFON Figure 1. Representative Block DiagramThis device contains 82 active transistorsSee detailed ordering and shipping information in the packagedimensions section on page 11 of this data sheet.ORDERING INFORMATIONMAXIMUM RATINGSHuman Body Model 2000 V per MIL–STD–883, Method 3015 Machine Model Method 200 Vtch up capability (85°C) "100 mA DC with trigger voltage.ELECTRICAL CHARACTERISTICS (V in = V out(nom.) + 1.0 V, V enable = V in, C in = 1.0 m F, C out = 1.0 m F, T J = 25°C, unless otherwise noted.)PD+T J(max)*T AR q JA4.Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.32150453540302520I Q , Q U I E S C E N T C U R R E N T (m A )V in , INPUT VOLTAGE (V)G R O U N D P I N C U R R E N T (m A )43215656418016014012010080400D R O P O U T V O L T A GE (m V )2060V in , INPUT VOLTAGE (V)Figure 6. Ground Pin Current vs. Input Voltage Figure 7. Current Limit vs. Input VoltageV i n , I N P U T V O L T A G E (V )O U T P U T V O L T A G E D E V I A T I O N (m V )I o u t , O U T P U T C U R R E N T (m A )10TIME (m s)Figure 11. Load Transient ResponseFigure 12. Load Transient Response–10020O U T P U T V O L T A G E D E V I A T I O N (m V )150TIME (m s)Figure 14. Output Noise Density f, FREQUENCY (kHz)0.01101001.00.11000O U T P U T N O I S E D E N S I T Y (m V /ǠH Z )Figure 15. Ripple Rejection vs. Frequencyf, FREQUENCY (Hz)100100 k1 M10 k1 kDEFINITIONSLoad RegulationThe change in output voltage for a change in output current at a constant temperature.Dropout VoltageThe input/output differential at which the regulator output no longer maintains regulation against further reductions in input voltage. Measured when the output drops 3.0% below its nominal. The junction temperature, load current, and minimum input supply requirements affect the dropout level. Maximum Power DissipationThe maximum total dissipation for which the regulator will operate within its specifications.Quiescent CurrentThe quiescent current is the current which flows through the ground when the LDO operates without a load on its output: internal IC operation, bias, etc. When the LDO becomes loaded, this term is called the Ground current. It is actually the difference between the input current (measured through the LDO input pin) and the output current.Line RegulationThe change in output voltage for a change in input voltage. The measurement is made under conditions of low dissipation or by using pulse technique such that the average chip temperature is not significantly affected.Line Transient ResponseTypical over and undershoot response when input voltage is excited with a given slope.Thermal ProtectionInternal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated at typically 160°C, the regulator turns off. This feature is provided to prevent failures from accidental overheating.Maximum Package Power DissipationThe maximum power package dissipation is the power dissipation level at which the junction temperature reaches its maximum operating value, i.e. 125°C. Depending on the ambient power dissipation and thus the maximum available output current.APPLICATIONS INFORMATIONA typical application circuit for the NCP511 series is shown in Figure 16.Input Decoupling (C1)A 1.0 m F capacitor either ceramic or tantalum is recommended and should be connected close to the NCP511package. Higher values and lower ESR will improve the overall line transient response.Output Decoupling (C2)The NCP511 is a stable Regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few m W up to 3.0 W can thus safely be used. The minimum decoupling value is 1.0 m F and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger values improve noise rejection and load regulation transient response.Enable OperationThe enable pin will turn on or off the regulator. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to V in .HintsPlease be sure the Vin and Gnd lines are sufficiently wide.When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction.Set external components, especially the output capacitor,as close as possible to the circuit, and make leads a short as possible.ThermalAs power across the NCP511 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material and also the ambient temperature effect the rate of temperature rise for the part.This is stating that when the NCP511 has good thermal conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications.The maximum dissipation the package can handle is given by:PD +T J(max)*T A R q JAIf junction temperature is not allowed above the maximum 125°C, then the NCP511 can dissipate up to 400 mW @ 25°C.The power dissipated by the NCP511 can be calculated from the following equation:P tot +[V in *I gnd (I out )])[V in *V out ]*I outorV inMAX +P tot)V out *I outI gnd )I outIf a 150 mA output current is needed then the ground current from the data sheet is 40 m A. For an NCP511SN30T1(3.0 V), the maximum input voltage will then be 5.6 V .Figure 16. Typical Application CircuitBattery or Unregulated VoltageOFFON I O , OUTPUT CURRENT (mA)Figure 17. Output Capacitor vs. OutputCurrentAPPLICATION CIRCUITSInput Input R1Figure 22. Input Voltages Greater than 6.0 VA regulated output can be achieved with input voltages thatexceed the 6.0 V maximum rating of the NCP511 series withthe addition of a simple pre–regulator circuit. Care must betaken to prevent Q1 from overheating when the regulatedoutput (V out) is shorted to G nd.MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONSSurface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.TSOP–5(Footprint Compatible with SOT–23–5)ORDERING INFORMATION11PACKAGE DIMENSIONSTSOP–5(SOT23–5, SC59–5)SN SUFFIX PLASTIC PACKAGE CASE 483–01ISSUE BNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.DIM MIN MAX MIN MAX INCHESMILLIMETERS A 2.90 3.100.11420.1220B 1.30 1.700.05120.0669C 0.90 1.100.03540.0433D 0.250.500.00980.0197G 0.85 1.050.03350.0413H 0.0130.1000.00050.0040J 0.100.260.00400.0102K 0.200.600.00790.0236L 1.25 1.550.04930.0610M 0 10 0 10 S2.503.000.09850.1181____ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.PUBLICATION ORDERING INFORMATIONJAPAN : ON Semiconductor, Japan Customer Focus Center 2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051Phone : 81–3–5773–3850Email : r14525@。
三菱电机 第4代大型DIPIPM 应用手册

三菱电机株式会社和三菱电机机电(上海)有限公司拥有本手册内所有资料的版权。 任何个人和企业在未得到书面许可的情况下,不得传播、复制、转载、出版和出售涉及本手册的任何内 容。如有违反,我们将保留追究其法律责任的权利。敬请留意。
2009 年 3 月
第 4 代大型 DIPIPM 应用手册
目录
第 1 章 产品概要 ......................................................................................................................................... 1
2.2 保护功能及其工作时序.......................................................................................................................... 9 2.2.1 短路保护......................................................................................................................................... 9 2.2.2 控制电源欠压保护(UV) ..................................................................................................... 12 2.2.............................................................................................. 13
CAT5113P-00MSOP中文资料

CAT5111100-Tap Digitally Programmable Potentiometer (DPP™)with Buffered Wiper FEATURESs 100-position linear taper potentiometer s Non-volatile NVRAM wiper storage;buffered wipers Low power CMOS technology s Single supply operation: 2.5V-6.0V s Increment up/down serial interface s Resistance values: 10k Ω, 50k Ω and 100k Ωs Available in PDIP, SOIC, TSSOP and MSOP packagesAPPLICATIONSs Automated product calibration s Remote control adjustments s Offset, gain and zero control s Tamper-proof calibrationss Contrast, brightness and volume controls s Motor controls and feedback systems s Programmable analog functionssystem values without effecting the stored setting. Wiper-control of the CAT5111 is accomplished with three input control pins, CS , U/D ,and INC . The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down.The digitally programmable potentiometer can be used as a buffered voltage divider. For applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the CAT5113. The buffered wiper of the CAT5111 is not compatible with that application. DPPs bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit.FUNCTIONAL DIAGRAMDESCRIPTIONThe CAT5111 is a single digitally programmable potentiometer (DPP™) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment.The CAT5111 contains a 100-tap series resistor array connected between two terminals R H and R L . An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, R WB . The CAT5111 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new Electronic PotentiometerImplementationWBCSINC U /DV WBHLGND© 2004 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeDoc. No. 2008, Rev. O1HAL O G E N F R E ETML EA D F R E ECAT51112Doc. No. 2008, Rev. Oof the CAT5111 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper.DEVICE OPERATIONThe CAT5111 operates like a digitally controlled potentiometer with R H and R L equivalent to the high and low terminals and R WB equivalent to the mechanical potentiometer's wiper. There are 100 available tap positions including the resistor end points, R H and R L .There are 99 resistor elements connected in series between the R H and R L terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC , U/D and CS . These inputs control a seven-bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs.With CS set LOW the CAT5111 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and seven-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5111 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory.When power is restored, the contents of the memory are recalled and the counter is set to the value stored.With INC set low, the CAT5111 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory.PIN DESCRIPTIONSINC : Increment Control InputThe INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input.U/D : Up/Down Control InputThe U/D input controls the direction of the wiper movement. When in a high state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment toward the R H terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the R L terminal.R H: High End Potentiometer TerminalR H is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the R L terminal. Voltage applied to the R H terminal cannot exceed the supply voltage, V CC or go below ground, GND.R WB : Wiper Potentiometer Terminal (Buffered)R WB is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC , U/D and CS .R L : Low End Potentiometer TerminalR L is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the R H terminal. Voltage applied to the R L terminal cannot exceed the supply voltage, V CC or go below ground, GND. R L and R H are electrically interchangeable.CS : Chip SelectThe chip select input is used to activate the control inputPIN FUNCTIONSPin Name FunctionINC Increment Control U/D Up/Down ControlR H Potentiometer High Terminal GND GroundR WB Buffered Wiper Terminal R L Potentiometer Low Terminal CS Chip Select V CCSupply VoltagePIN CONFIGURATIONPDIP Package (P, L)TSSOP Package (U, Y)MSOP Package (R, Z)INC V CC CS R L R WB U /DR HGND 12348765CS INC V CC R L R WBU /D R H GND12348765V CC R L R WBGNDR H INC U/D CS 12348765CS INC V CC R L R WBU /D R H GND12348765SOIC Package (S, V)CAT51113Doc. No. 2008, Rev. OOPERATING MODESABSOLUTE MAXIMUM RATINGS Supply VoltageV CC to GND –0.5V to +7V InputsCS to GND –0.5V to V CC +0.5V INC to GND –0.5V to V CC +0.5V U/D to GND –0.5V to V CC +0.5V R H to GND –0.5V to V CC +0.5V R L to GND –0.5V to V CC +0.5V R WB to GND–0.5V to V CC +0.5VOperating Ambient TemperatureCommercial (‘C ’ or Blank suffix)0°C to +70°C Industrial (‘I ’ suffix)– 40°C to +85°C Junction Temperature +150°C Storage Temperature –65°C to +150°C Lead Soldering (10 sec max)+300°C* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time.NOTES:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V CC + 1V (3)I W =source or sink(4)These parameters are periodically sampled and are not 100% tested.C C WB Power SupplySymbol Parameter Conditions MinTypMaxUnitsV CC Operating Voltage Range2.5— 6.0V I CC1Supply Current (Increment) V CC = 6V, f = 1MHz, I W =0——200µA V CC = 6V, f = 250kHz, I W =0——100I CC2Supply Current (Write) Programming, V CC = 6V——1mA V CC = 3V ——500µA ISB 1 (2)Supply Current (Standby)CS=V CC -0.3V—75150µAU/D, INC=V CC -0.3V or GNDDC Electrical Characteristics: V CC = +2.5V to +6.0V unless otherwise specifiedINC CS U/D Operation High to Low Low High Wiper toward R H High to Low Low Low Wiper toward R L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby XHighXStandbyRELIABILITY CHARACTERISTICS SymbolParameterTest MethodMinTyp Max UnitsV ZAP (1)ESD Susceptibility MIL-STD-883, Test Method 30152000Volts I LTH (1)(2)Latch-UpJEDEC Standard 17100mA T DR Data Retention MIL-STD-883, Test Method 1008100Years N ENDEnduranceMIL-STD-883, Test Method 10031,000,000StoresCAT51114Doc. No. 2008, Rev. OSymbol ParameterConditions Min Typ Max Units R POTPotentiometer Resistance-10 Device 10-50 Device 50 k Ω-00 Device100Pot Resistance Tolerance±20% V RH Voltage on R H pin 0 V CC VV RL Voltage on R L pin 0V CCVResolution1% INL Integral Linearity Error I W ≤ 2µA 0.5 1 LSB DNL Differential Linearity Error I W ≤ 2µA0.250.5 LSB R OUT Buffer Output Resistance .05V CC ≤ V WB ≤ .95V CC , V CC =5V 1 Ω I OUT Buffer Output Current .05V CC ≤ V WB ≤ .95V CC , V CC =5V3mA TC RPOT TC of Pot Resistance 300ppm/o C TC RATIO Ratiometric TC TBD ppm/o C R ISOIsolation Resistance TBDΩ C RH /C RL /C RWPotentiometer Capacitances 8/8/25pF fc Frequency Response Passive Attenuator, 10k Ω 1.7MHzV WB(SWING)Output Voltage RangeI OUT ≤100µA, V CC =5V0.01V CC.99V CCPotentiometer ParametersCAT51115Doc. No. 2008, Rev. OV CC Range 2.5V ≤ V CC ≤ 6V Input Pulse Levels 0.2V CC to 0.7V CC Input Rise and Fall Times 10ns Input Reference Levels0.5V CCAC CONDITIONS OF TEST A. C. TIMING(1)Typical values are for T A =25˚C and nominal supply voltage.(2)This parameter is periodically sampled and not 100% tested.(3)MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.CSU R WBSymbolParameterMinTyp (1)MaxUnitst CI CS to INC Setup 100——ns t DI U/D to INC Setup 50——ns t ID U/D to INC Hold 100——ns t IL INC LOW Period 250——ns t IH INC HIGH Period250——ns t IC INC Inactive to CS Inactive1——µs t CPH CS Deselect Time (NO STORE)100——ns t CPH CS Deselect Time (STORE)10——ms t IW INC to V OUT Change —15µs t CYC INC Cycle Time1——µs t R, t F (2)INC Input Rise and Fall Time ——500µs t PU (2)Power-up to Wiper Stable ——1msec t WRStore Cycle—510msAC OPERATING CHARACTERISTICS:V CC = +2.5V to +6.0V, V H = V CC , V L = 0V , unless otherwise specifiedCAT51116Doc. No. 2008, Rev. OORDERING INFORMATIONNotes:(1) The device used in the above example is a CAT5111 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)CAT5111Catalyst Semiconductor, Inc.Corporate Headquarters 1250 Borregas AvenueSunnyvale, CA 94089Phone: 408.542.1000Fax: 408.542.1200Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™AE 2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.Publication #:2002Revison:OIssue date:4/12/04REVISION HISTORY。
三品SANP变频器说明书

目录1、前言 (3)1.1 安全守则 (4)1.2 购入时注意事项 (5)1.3 SANP系列铭牌说明 (5)2、存储及安装 (6)2.1安装场所及环境 (6)2.2安装空间及方向 (7)3、配线 (8)3.1 主回路配线图 (8)3.2配线注意事项 (9)3.3 基本配线图 (11)4.1 产品通用规格 (14)4.2 接线端子说明 (15)4.3 主回路端子说明 (17)4.4 控制端子说明 (17)5、数位操作器说明 (18)5.1 数位操作器说明 (18)5.2 指示灯说明 (20)5.3 显示项目说明 (20)5.4 操作说明 (22)6、功能一览表 (24)7、功能说明 (33)9、周边设施选用及配置 (94)10、故障信息及排除方法 (106)9、周边设施选用及配置 (120)11、三品MODBUS通讯规约 (114)12、附录 (123)附录一:机器外形及安装尺寸 (123)附录二:面板外形及安装尺寸 (130)11、产品保修卡 (132)12、产品保修协议 (133)前 言感谢您选购SANP 系列变频器!本变频器是针对中国电网和各行业三相异步电动机调速的特点而设计;采用最新式微处理器,控制精度高、性能稳定、操作方便、保护功能更加完善。
在使用变频器前请详细阅读本使用说明书,以便正确安装使用本 产品,充分发挥其功能,并确保使用安全。
请妥善保存此说明书,以便日后保养、维护、检修时使用。
!SANP-0.75~415KW Series操作说明书Operating Instructions表示高压警告表示一般警告表示禁止操作【安全守则】1、请委托专业人员进行布线;如果布线不当可能会造成触电或火灾!2、请确认输入电源处于OFF(断开)位置后,方可进行布线作业!3、请务必连接好接地线,并且保证接地线截面积!4、请不要将交流电源连接到变频器输出端子上(U、V、W)。
5、请确认输入电源电压与本品的额定电压相符。
IPP10N03L中文资料

IPB10N03LOpti MOS ® Buck converter seriesProduct Summary V DS30V R DS(on) max. SMD version 8.9m ΩID73AFeature• N-Channel• Logic Level• Low On-Resistance R DS(on)• Excellent Gate Charge x R DS(on) product (FOM)• Superior thermal resistance• 175°C operating temperature • Avalanche rated • d v /d t rated• Ideal for fast switching buck convertersP- TO263 -3-2P- TO220 -3-1Marking 10N03L 10N03LType Package Ordering Code IPP10N03L P- TO220 -3-1Q67042-S4040IPB10N03L P- TO263 -3-2Q67040-S4346Maximum Ratings , at T j = 25 °C, unless otherwise specifiedParameterSymbol Value Unit Continuous drain current 1)T C =25°CI D7363APulsed drain currentT C =25°CI D puls 292Avalanche energy, single pulseI D =30A, V DD =25V, R GS =25ΩE AS 25mJRepetitive avalanche energy, limited by T jmax 2)E AR 10Reverse diode d v /d tI S =73A, V DS =24, d i /d t =200A/µs, T jmax =175°Cd v /d t 6kV/µs Gate source voltage V GS ±20V Power dissipationT C =25°CP tot 107W Operating and storage temperature T j , T stg-55... +175°C IEC climatic category; DIN IEC 68-155/175/56IPB10N03LThermal Characteristics Parameter SymbolValues Unitmin.typ.max.CharacteristicsThermal resistance, junction - case R thJC -0.9 1.4K/WSMD version, device on PCB:@ min. footprint @ 6 cm 2 cooling area 3)R thJA---- 6240Electrical Characteristics , at T j = 25 °C, unless otherwise specified ParameterSymbolValues Unitmin.typ.max.Static CharacteristicsDrain-source breakdown voltageV GS =0V, I D =1mAV (BR)DSS 30--VGate threshold voltage, V GS = V DSI D =60µAV GS(th) 1.2 1.62Zero gate voltage drain currentV DS =30V, V GS =0V, T j =25°C V DS =30V, V GS =0V, T j =175°CI DSS-- 0.0110 1100µAGate-source leakage currentV GS =20V, V DS =0VI GSS -1100nA Drain-source on-state resistanceV GS =4.5V, I D =36AV GS =4.5V, I D =36A, SMD versionR DS(on)-- 9.99.5 13.413.1m ΩDrain-source on-state resistance 4)V GS =10V, I D =36AV GS =10V, I D =36A, SMD versionR DS(on)--6.86.59.28.91Current limited by bondwire ; with an RthJC = 1.4K/W the chip is able to carry I D = 88A at 25°C, for detailed information see app.-note ANPS071E available at /optimos 2Defined by design. Not subject to production test.3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air.4Diagrams are related to straight lead versionsIPB10N03LElectrical Characteristics ParameterSymbol ConditionsValues Unitmin.typ.max.Dynamic Characteristics Transconductance g fs V DS ≥2*I D *R DS(on)max , I D =63A3263-SInput capacitance C iss V GS =0V, V DS =25V, f =1MHz-12901710pF Output capacitanceC oss -500670Reverse transfer capacitance C rss -130190Gate resistance R G -1.4-ΩTurn-on delay time t d(on)V DD =15V, V GS =10V, I D =18A, R G =4.7Ω-7.711.6nsRise timet r -2030Turn-off delay time t d(off)-31.547.3Fall timet f -1928.5Gate Charge Characteristics Gate to source charge Q gs V DD =15V, I D =36A-45nCGate to drain charge Q gd -10.613.3Gate charge total Q g V DD =15V, I D =36A, V GS =0 to 5V -1923.8Output charge Q ossV DS =15V, I D =36A, V GS =0V-18.222.8nC Gate plateau voltage V (plateau)V DD =15V, I D =36A -3.6-VReverse DiodeInverse diode continuous forward currentI ST C =25°C--73AInv. diode direct current, pulsed I SM --292Inverse diode forward voltage V SD V GS =0V, I F =73A -0.96 1.28V Reverse recovery time t rr V R =15V, I F =l S , d i F /d t =100A/µs-32.941.2ns Reverse recovery chargeQ rr-3341nCIPB10N03L1 Power dissipation P tot = f (T C )P t o t2 Drain current I D = f (T C )parameter: V≥ 10 VI D4 Max. transient thermal impedance Z thJC = f (t p )parameter : D = t/T10 10 10 10 10 10 K/WZ t h JC3 Safe operating area I D = f ( V DS )parameter : D = 0 , T = 25 °C2I DIPB10N03L5 Typ. output characteristic I D = f (V DS ); T j =25°C parameter: t= 80 µsI D6 Typ. drain-source on resistance R DS(on) = f (I D )parameter: V R D S (o n )7 Typ. transfer characteristics I D = f ( V GS ); V DS ≥ 2 x I D x R DS(on)max parameter: t p = 80 µsI D8 Typ. forward transconductance g fs = f(I D ); T j =25°C parameter: g fsg f sIPB10N03L9 Drain-source on-state resistance R DS(on) = f (T j )parameter : I= 36 A, V = 10 VR D S (o n)10 Typ. gate threshold voltage V GS(th) = f (T j )parameter: V GS = V DSV G S (t h )11 Typ. capacitances C = f (V DS )parameter: V GS =0V, f =1 MHzC12 Forward character. of reverse diode I F = f (V SD )parameter: T, t p = 80 µsI FIPB10N03L13 Typ. avalanche energy E AS = f (T j )par.: I D = 30 A, V DD = 25 V, R GS = 25 Ω14 Typ. gate charge V GS = f (Q Gate )parameter: I = 36 A pulsedVG S15 Drain-source breakdown voltage V (BR)DSS = f (T j )parameter: I =10 mAV (B R )D S SIPB10N03L Published byInfineon Technologies AG,Bereichs KommunikationSt.-Martin-Strasse 53,D-81541 München© Infineon Technologies AG 1999All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be considered as warranted characteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,regarding circuits, descriptions and charts stated herein.Infineon Technologies is an approved CECC manufacturer.InformationFor further information on technology, delivery terms and conditions and prices please contact your nearestInfineon Technologies Office in Germany or our Infineon Technologies Reprensatives worldwide (see address list). WarningsDue to technical requirements components may contain dangerous substances.For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the expresswritten approval of Infineon Technologies, if a failure of such components can reasonably be expected tocause the failure of that life-support device or system, or to affect the safety or effectiveness of that deviceor system Life support devices or systems are intended to be implanted in the human body, or to supportand/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the healthof the user or other persons may be endangered.。
热缩管产品介绍资料

P5 热缩管工艺路线图
配比/造粒
原材料
出货
拌料
挤出成型
辐照
★扩张成型
成品检验
打卷
委外加工
裁切
包装
P6 热缩管的分类(常 见)
2:1 单壁热缩管 3:1
4:1
2:1 双壁热缩管 3:1
列公式计算纵向变化率Lc:
L1 – L2
纵向变化率Lc[%] =
×100%
L1
P9 热缩管的收缩条件&选型
Ⅰ,热缩管的收缩条件:
① 收缩工具:恒温烤箱、隧道炉,热风枪; ② 收缩温度:150℃~200℃之间; ③ 热缩时间:建议温烤箱(150℃~200℃)X5min&热风枪(300℃-350℃)X30秒内(仅供参考)
抗UV性(黑色)
其它性能 ROHS2.0
标准 UL224-2021 UL224-2021 UL 224-2021 UL 224-2021 ASTM D2671 ASTM D2671 UL224-2021 ASTM D149-2020 UL 224-2021 UL224 UL224-2021 UL224-2021 /
热老化后断裂伸长率%(158℃X168H)
热冲击(200℃X4h)
低温柔韧性(-40℃X4H)
耐压等级600V 电气性能 击穿强度
体积电阻率Ω.cm 铜安定性 化学性能 抗腐蚀性 阻燃性
抗UV性(黑色)
其它性能 ROHS2.0
标准 UL224-2021 UL224-2021 UL 224-2021 UL 224-2021 ASTM D2671 ASTM D2671 UL224-2021 ASTM D149-2020 UL 224-2021 UL224 UL224-2021 UL224-2021 /
光猫BOM

采购订单序时簿
2019/01/21 2019/01/21
2019/01/21 2019/01/21
班信科技(惠州)有限公司 深圳市茂兴恒业科技有限公司
深圳市磁联达电子有限公司 深圳市明智芯科技有限公司
JYKLX190121-03 JYKLX190121-04
JYKLX190121-05 JYKLX190121-06
Page 2
采购订单序时簿
31.63.5085R 31.63.5086R 31.63.5087R 31.63.5088R 31.63.5089R 31.63.5090R 31.63.5091R 31.63.5092R 31.63.5093R 31.63.5094R 31.85.0005R 31.85.5014R 31.85.5015R 31.85.5016R 31.85.5017R 31.86.4202R 31.86.4207R 31.86.6306R 31.86.6311R 31.86.6317R 31.86.6318R 32.08.0001R 32.20.0005R 32.26.0018R 32.26.0026R 32.26.0038R 32.26.0039R 32.42.0001R 32.42.0003R 32.42.0015R 32.42.0024R 32.42.0046R 32.42.0055R 32.42.0059R 32.42.0107R 32.42.0111R 32.42.0130R 32.42.0131R 32.42.0147R 32.42.0166R 32.42.0241R 32.42.0246R 32.42.0247R 32.42.0248R 32.42.0249R 32.42.0250R 32.42.0251R 32.42.0252R 32.42.0253R 32.42.0254R 32.42.0255R 32.42.0256R 32.42.0257R 32.42.0258R 32.42.0259R 32.63.0002R
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CAT5111100-Tap Digitally Programmable Potentiometer (DPP™)with Buffered Wiper FEATURESs 100-position linear taper potentiometer s Non-volatile NVRAM wiper storage;buffered wipers Low power CMOS technology s Single supply operation: 2.5V-6.0V s Increment up/down serial interface s Resistance values: 10k Ω, 50k Ω and 100k Ωs Available in PDIP, SOIC, TSSOP and MSOP packagesAPPLICATIONSs Automated product calibration s Remote control adjustments s Offset, gain and zero control s Tamper-proof calibrationss Contrast, brightness and volume controls s Motor controls and feedback systems s Programmable analog functionssystem values without effecting the stored setting. Wiper-control of the CAT5111 is accomplished with three input control pins, CS , U/D ,and INC . The INC input increments the wiper in the direction which is determined by the logic state of the U/D input. The CS input is used to select the device and also store the wiper position prior to power down.The digitally programmable potentiometer can be used as a buffered voltage divider. For applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the CAT5113. The buffered wiper of the CAT5111 is not compatible with that application. DPPs bring variability and programmability to a broad range of applications and are used primarily to control, regulate or adjust a characteristic or parameter of an analog circuit.FUNCTIONAL DIAGRAMDESCRIPTIONThe CAT5111 is a single digitally programmable potentiometer (DPP™) designed as a electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment.The CAT5111 contains a 100-tap series resistor array connected between two terminals R H and R L . An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, R WB . The CAT5111 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile NVRAM memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new Electronic PotentiometerImplementationWBCSINC U /DV WBHLGND© 2004 by Catalyst Semiconductor, Inc.Characteristics subject to change without noticeDoc. No. 2008, Rev. O1HAL O G E N F R E ETML EA D F R E ECAT51112Doc. No. 2008, Rev. Oof the CAT5111 and is active low. When in a high state, activity on the INC and U/D inputs will not affect or change the position of the wiper.DEVICE OPERATIONThe CAT5111 operates like a digitally controlled potentiometer with R H and R L equivalent to the high and low terminals and R WB equivalent to the mechanical potentiometer's wiper. There are 100 available tap positions including the resistor end points, R H and R L .There are 99 resistor elements connected in series between the R H and R L terminals. The wiper terminal is connected to one of the 100 taps and controlled by three inputs, INC , U/D and CS . These inputs control a seven-bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC and CS inputs.With CS set LOW the CAT5111 is selected and will respond to the U/D and INC inputs. HIGH to LOW transitions on INC wil increment or decrement the wiper (depending on the state of the U/D input and seven-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. When the CAT5111 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory.When power is restored, the contents of the memory are recalled and the counter is set to the value stored.With INC set low, the CAT5111 may be de-selected and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory.PIN DESCRIPTIONSINC : Increment Control InputThe INC input (on the falling edge) moves the wiper in the up or down direction determined by the condition of the U/D input.U/D : Up/Down Control InputThe U/D input controls the direction of the wiper movement. When in a high state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment toward the R H terminal. When in a low state and CS is low, any high-to-low transition on INC will cause the wiper to move one increment towards the R L terminal.R H: High End Potentiometer TerminalR H is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the R L terminal. Voltage applied to the R H terminal cannot exceed the supply voltage, V CC or go below ground, GND.R WB : Wiper Potentiometer Terminal (Buffered)R WB is the buffered wiper terminal of the potentiometer. Its position on the resistor array is controlled by the control inputs, INC , U/D and CS .R L : Low End Potentiometer TerminalR L is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the R H terminal. Voltage applied to the R L terminal cannot exceed the supply voltage, V CC or go below ground, GND. R L and R H are electrically interchangeable.CS : Chip SelectThe chip select input is used to activate the control inputPIN FUNCTIONSPin Name FunctionINC Increment Control U/D Up/Down ControlR H Potentiometer High Terminal GND GroundR WB Buffered Wiper Terminal R L Potentiometer Low Terminal CS Chip Select V CCSupply VoltagePIN CONFIGURATIONPDIP Package (P, L)TSSOP Package (U, Y)MSOP Package (R, Z)INC V CC CS R L R WB U /DR HGND 12348765CS INC V CC R L R WBU /D R H GND12348765V CC R L R WBGNDR H INC U/D CS 12348765CS INC V CC R L R WBU /D R H GND12348765SOIC Package (S, V)CAT51113Doc. No. 2008, Rev. OOPERATING MODESABSOLUTE MAXIMUM RATINGS Supply VoltageV CC to GND –0.5V to +7V InputsCS to GND –0.5V to V CC +0.5V INC to GND –0.5V to V CC +0.5V U/D to GND –0.5V to V CC +0.5V R H to GND –0.5V to V CC +0.5V R L to GND –0.5V to V CC +0.5V R WB to GND–0.5V to V CC +0.5VOperating Ambient TemperatureCommercial (‘C ’ or Blank suffix)0°C to +70°C Industrial (‘I ’ suffix)– 40°C to +85°C Junction Temperature +150°C Storage Temperature –65°C to +150°C Lead Soldering (10 sec max)+300°C* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time.NOTES:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V CC + 1V (3)I W =source or sink(4)These parameters are periodically sampled and are not 100% tested.C C WB Power SupplySymbol Parameter Conditions MinTypMaxUnitsV CC Operating Voltage Range2.5— 6.0V I CC1Supply Current (Increment) V CC = 6V, f = 1MHz, I W =0——200µA V CC = 6V, f = 250kHz, I W =0——100I CC2Supply Current (Write) Programming, V CC = 6V——1mA V CC = 3V ——500µA ISB 1 (2)Supply Current (Standby)CS=V CC -0.3V—75150µAU/D, INC=V CC -0.3V or GNDDC Electrical Characteristics: V CC = +2.5V to +6.0V unless otherwise specifiedINC CS U/D Operation High to Low Low High Wiper toward R H High to Low Low Low Wiper toward R L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby XHighXStandbyRELIABILITY CHARACTERISTICS SymbolParameterTest MethodMinTyp Max UnitsV ZAP (1)ESD Susceptibility MIL-STD-883, Test Method 30152000Volts I LTH (1)(2)Latch-UpJEDEC Standard 17100mA T DR Data Retention MIL-STD-883, Test Method 1008100Years N ENDEnduranceMIL-STD-883, Test Method 10031,000,000StoresCAT51114Doc. No. 2008, Rev. OSymbol ParameterConditions Min Typ Max Units R POTPotentiometer Resistance-10 Device 10-50 Device 50 k Ω-00 Device100Pot Resistance Tolerance±20% V RH Voltage on R H pin 0 V CC VV RL Voltage on R L pin 0V CCVResolution1% INL Integral Linearity Error I W ≤ 2µA 0.5 1 LSB DNL Differential Linearity Error I W ≤ 2µA0.250.5 LSB R OUT Buffer Output Resistance .05V CC ≤ V WB ≤ .95V CC , V CC =5V 1 Ω I OUT Buffer Output Current .05V CC ≤ V WB ≤ .95V CC , V CC =5V3mA TC RPOT TC of Pot Resistance 300ppm/o C TC RATIO Ratiometric TC TBD ppm/o C R ISOIsolation Resistance TBDΩ C RH /C RL /C RWPotentiometer Capacitances 8/8/25pF fc Frequency Response Passive Attenuator, 10k Ω 1.7MHzV WB(SWING)Output Voltage RangeI OUT ≤100µA, V CC =5V0.01V CC.99V CCPotentiometer ParametersCAT51115Doc. No. 2008, Rev. OV CC Range 2.5V ≤ V CC ≤ 6V Input Pulse Levels 0.2V CC to 0.7V CC Input Rise and Fall Times 10ns Input Reference Levels0.5V CCAC CONDITIONS OF TEST A. C. TIMING(1)Typical values are for T A =25˚C and nominal supply voltage.(2)This parameter is periodically sampled and not 100% tested.(3)MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.CSU R WBSymbolParameterMinTyp (1)MaxUnitst CI CS to INC Setup 100——ns t DI U/D to INC Setup 50——ns t ID U/D to INC Hold 100——ns t IL INC LOW Period 250——ns t IH INC HIGH Period250——ns t IC INC Inactive to CS Inactive1——µs t CPH CS Deselect Time (NO STORE)100——ns t CPH CS Deselect Time (STORE)10——ms t IW INC to V OUT Change —15µs t CYC INC Cycle Time1——µs t R, t F (2)INC Input Rise and Fall Time ——500µs t PU (2)Power-up to Wiper Stable ——1msec t WRStore Cycle—510msAC OPERATING CHARACTERISTICS:V CC = +2.5V to +6.0V, V H = V CC , V L = 0V , unless otherwise specifiedCAT51116Doc. No. 2008, Rev. OORDERING INFORMATIONNotes:(1) The device used in the above example is a CAT5111 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)CAT5111Catalyst Semiconductor, Inc.Corporate Headquarters 1250 Borregas AvenueSunnyvale, CA 94089Phone: 408.542.1000Fax: 408.542.1200Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™AE 2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.Publication #:2002Revison:OIssue date:4/12/04REVISION HISTORY。