1790128中文资料
EP1C12F144C7中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」
EP1C6
5,980 20
92,160 2
185
EP1C12
12,060 52
239,616 2
249
EP1C20 20,060
64 294,912
2 301
1
芯片中文手册,看全文,戳
气旋 FPGA系列数据手册
初稿信息
Cyclone器件在四方扁平封装（QFP）,并提供节省空间
FineLine BGA 包（见
Cyclone器件提供一个全局时钟网络和多达两个PLL.全局时钟网络由八 个全局时钟线驱动整个器件.全局时钟网络可以为设备内所有资源 ,如IOEs,LE和存储器块提供时钟.
全局时钟线也可用于控制信号.旋风PLL提供通用与时钟倍频和移相,以 及外部输出高速差分I / O支持时钟.
图1
示出旋风EP1C12装置图.
M4K RAM块与4K位内存加上平价（4,608位）真正双端口存储器 块.这些块宽高达200 MHz提供专用真正双端口,简单双端口或单端 口内存最高可达36位.这些块加在器件分成列在一定LAB之间. Cyclone器件提供嵌入式RAM 60至288千位之间.
每个Cyclone器件I / O引脚由I / O单元（IOE）位于输送 围绕装置外周端部LAB行和列. I / O 引脚支持各种单端和差分I / O标准,如 66 MHz32位PCI标准,并在到LVDS I / O标准 311 Mbps.每个IOE包含一个双向I / O缓冲区和三个寄存器 用于登记输入,输出和输出使能信号.两用 DQS,DQ和DM引脚以及延时链（用于相位对齐DDR 信号）提供与外部存储器设备,诸如接口支持 DDR SDRAM和高达133兆赫（266 Mbps）FCRAM器件.
配置设备配置Cyclone器件.
FM1288中文数据手册(仅供参考)
FM-1288 高性能汽车免提语音理器产前信息本文件包含一个试制产品信息。
规格和试生产资料如有更改恕不另行通知。
富迪科技的产品并不是为了挽救生命或维持生命的应用。
因此，如果这样使用的话迪科技不承担任何责任。
富迪的产品有富迪的书面批准才能用于生命支持设备或系统。
如果有这样的组件故障可合理预期会导致该生命支持设备或系统的失效，或影响的设备或系统的安全性或有效性。
生命支持设备或系统的目的是植入人体，或支持和/或维持和维持和/或保护人类生活。
如果他们失败了，这个假设合理，用户或其他人的健康可能会受到威胁。
在此我们拒绝任何形式的担保，但不限于保证不侵权，还包括对于电路说明和图表说明。
Fortémedia, SAM, ForteVoice, Fortémedia and SAM logos are trademarks of Fortémedia,, Inc.All other trademarks belong to their respective companies.Copyright © 2012 Fortémedia all rights reserved目录1. 简介 (9)1.1概述 (9)1.2个主要特点 (9)1.3引脚配置（LQFP） (10)1.4设备终端功能 (11)1.5部硬件框图 (14)1.6系统应用程序框图 (15)2. 功能描述 (17)2.1概述 (17)2.2串行EEPROM接口（引脚15，16） (17)2.3 UART接口（引脚12，13） (22)2.4 IIC兼容串行接口-SHI（引脚23，24） (24)2.5数字语音数据接口（引脚8，9，10,11） (25)2.5.1 PCM接口主从 (26)2.5.2 IIS接口 (28)2.6 ADC（引脚39，40，41，42，43，44） (33)2.7 DAC（引脚 1，3，47，48） (34)2.8操作模式 (35)2.9电STAP选项（引脚17） (37)2.10静音控制和指示（引脚20，21） (37)2.11扬声器音量控制（引脚25，26） (38)2.12系统时钟输入和产生（引脚27，28） (38)2.13旁路模式（引脚14） (39)3.通过EEPROM，UART，SHI访问fm1288 (40)3.1访问通过EEPROM (41)3.2 通过实例访问EEPROM (42)3.3通过UART访问 (43)3.5通过SHI访问 (44)3.6个例子通过施 (44)4. 电气和时序规 (44)4.1绝对最大额定值 (45)4.2推荐操作条件 (45)4.3直流特性 (46)4.4交流特性 (47)4.5时序特性 (49)5. 语音处理器性能细节 (52)6. 引脚定义细节 (53)7. 封装尺寸（LQFP） (55)8. 订货信息 (56)附录 I：操作所需的外部元件 (57)参考 (59)状态信息本产品数据表的状态是产品信息。
MC1GU128NCYA-0QC00中文资料
MultiMediaCard SpecificationVersion : Ver. 0.9Date 4 – June - 2004Samsung Electronics Co., LTDSemiconductor Flash Memory Product Planning & Applications1 Introduction to the MultiMediaCard ----------------------------------------------------------- 51.1 System Features ----------------------------------------------------------------------------------------- 5-------------------------------------------------------------------------------------- 51.2 ProductModel2 Function Description ------------------------------------------------------------------------------- 72.1 Flash Technology Independence ------------------------------------------------------------------ 72.2 Defect and Error Management --------------------------------------------------------------------- 72.3 Endurance ----------------------------------------------------------------------------------------------- 72.4 Automatic Sleep Mode ------------------------------------------------------------------------------- 72.5 Hot Insertion -------------------------------------------------------------------------------------------- 82.6 MultiMediaCard Mode -------------------------------------------------------------------------------- 82.6.1 MultiMediaCard Standard Compliance ----------------------------------------------------------- 82.6.2 Negotiation Operation Conditions ----------------------------------------------------------------- 82.6.3 Card Acquisition and Identification ---------------------------------------------------------------- 82.6.4 Card Status ---------------------------------------------------------------------------------------------- 82.6.5 Memory Array Partitioning --------------------------------------------------------------------------- 92.6.6 Read and Write Operations ------------------------------------------------------------------------- 92.6.7 Data Transfer Rate ------------------------------------------------------------------------------------102.6.8 Data Protection in the Flash Card -----------------------------------------------------------------10-----------------------------------------------------------------------------------------------------10 2.6.9 Erase2.6.10 Write Protection ----------------------------------------------------------------------------------------102.6.11 Copy Bit ------------------------------------------------------------------------------------------------- 102.6.12 The CSD Register ------------------------------------------------------------------------------------ 112.7 SPI Mode ----------------------------------------------------------------------------------------------- 112.7.1 Negotiating Operation Conditions ---------------------------------------------------------------- 112.7.2 Card Acquisition and Identification --------------------------------------------------------------- 112.7.3 Card Status --------------------------------------------------------------------------------------------- 112.7.4 Memory Array Partitioning -------------------------------------------------------------------------- 112.7.5 Read and Write Operations ------------------------------------------------------------------------- 112.7.6 Data Transfer Rate ------------------------------------------------------------------------------------ 112.7.7 Data Protection in the MultiMediaCard ----------------------------------------------------------- 1212-----------------------------------------------------------------------------------------------------2.7.8 Erase2.7.9 Write Protection ---------------------------------------------------------------------------------------- 123 Product Specifications ----------------------------------------------------------------------------- 133.1 Recommended Operating Conditions ------------------------------------------------------------------------- 133.2 Operating Characteristis ----------------------------------------------------------------- 143.3 System Environmental Specifications ----------------------------------------------------------------- 153.4 System Reliability and Maintenance -------------------------------------------------------------- 153.5 Physical Specifications ------------------------------------------------------------------------------- 164 MultiMediaCard Interface Description --------------------------------------------------------- 174.1 Pin Assignments in MultiMediaCard Mode ------------------------------------------------------- 174.2 Pin Assignments in SPI Mode ---------------------------------------------------------------------- 184.3 MultiMediaCard Bus Topology ---------------------------------------------------------------------- 184.4 SPI Bus Topology -------------------------------------------------------------------------------------------------- 194.4.1 SPI Interface Concept ------------------------------------------------------------------------------------------- 194.4.2 SPI Bus Topology ------------------------------------------------------------------------------------------------ 1920------------------------------------------------------------------------------------------------- 4.5 Registers4.5.1 Operation Condition Register (OCR) ---------------------------------------------------------------------------204.5.2 Card Identification (CID) ------------------------------------------------------------------------------214.5.3 Relative Card Address (RCA) ----------------------------------------------------------------------- 21 4.5.4 Card Specific Data (CSD) ---------------------------------------------------------------------------- 22 4.6 MultiMediaCard Communication -------------------------------------------------------------------- 3030----------------------------------------------------------------------------------------------- 4.6.1 Commands4.7 Read, Write and Erase Time-out Conditions ----------------------------------------------------- 33 4.8 Card Identification Mode ------------------------------------------------------------------------------ 34 4.8.1 Operating Voltage Range Validation --------------------------------------------------------------- 35 4.9 Data Transfer Mode ------------------------------------------------------------------------------------ 35 4.9.1 Block Read ----------------------------------------------------------------------------------------------- 37 4.9.2 Block Write ----------------------------------------------------------------------------------------------- 3738------------------------------------------------------------------------------------------------------ 4.9.3 Erase4.9.4 Write Protect Management -------------------------------------------------------------------------- 38 4.9.5 Card Lock/Unlock Operation ------------------------------------------------------------------------ 38----------------------------------------------------------------------------------------------- 41 4.9.6 Responses4.9.7 Status ------------------------------------------------------------------------------------------------------ 42 4.9.8 Command Response Timing ------------------------------------------------------------------------ 4448 4.9.9 Reset------------------------------------------------------------------------------------------------------ 4.10 SPI Communication ----------------------------------------------------------------------------------- 49 4.10.1 Mode Selection ----------------------------------------------------------------------------------------- 49 4.10.2 Bus Transfer Protection ------------------------------------------------------------------------------ 49 4.10.3 Data Read Overview ---------------------------------------------------------------------------------- 50 4.10.4 Data Write Overview ---------------------------------------------------------------------------------- 51 4.10.5 Erase and Write Protect Management ----------------------------------------------------------- 52 4.10.6 Reading CID/CSD Registers ------------------------------------------------------------------------ 53 4.10.7 Reset Sequence --------------------------------------------------------------------------------------- 53 4.10.8 Error Conditions ---------------------------------------------------------------------------------------- 53 4.10.9 Memory Array Partitioning --------------------------------------------------------------------------- 53 4.10.10 Card Lock/Unlock -------------------------------------------------------------------------------------- 53 4.10.11 Commands ----------------------------------------------------------------------------------------------- 54 4.10.12 Responses ----------------------------------------------------------------------------------------------- 56 4.10.13 Data Tokens --------------------------------------------------------------------------------------------- 58 4.10.14 Data Error Token --------------------------------------------------------------------------------------- 59 4.10.15 Clearing Status Bits ------------------------------------------------------------------------------------ 60 4.11 SPI Bus Timing ----------------------------------------------------------------------------------------- 61 4.12 Error Handling ------------------------------------------------------------------------------------------ 64 4.12.1 Error Correction Code (ECC) ----------------------------------------------------------------------- 64 4.12.2 Cyclic Redundancy Check (CRC) ----------------------------------------------------------------- 642 Function Description2.1 Flash Technology IndependenceThe 512 byte sector size of the MultiMediaCard is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the MultiMediaCard. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the MultiMediaCard uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the MultiMediaCard today will be able to access future MultiMediaCards built with new flash technology without having to update or change host software.2.2 Defect and Error ManagementMultiMediaCards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. MultiMediaCards do a read after write under margin conditions to verify that the data is written correctly (except in the case of a Write without Erase Command). In the rare case that a bit is found to be defective, MultiMediaCards replace this bad bit with a spare bit within the sector header. If necessary, MultiMediaCards will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.The MultiMediaCards soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, MultiMediaCards have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.These defect and error management systems coupled with the solid-state construction give MultiMediaCards unparalleled reliability2.3 EnduranceMultiMediaCards have an endurance specification for each sector of 1,000,000 writes (reading a logical sector is unlimited). This is far beyond what is needed in nearly all applications of MultiMediaCards. Even very heavy use of the MultiMediaCard in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s five year lifetime. For instance, it would take over 100 years to wear out an area on the MultiMediaCard on which a files of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.With typical applications the endurance limit is not of any practical concern to the vast majority of users.2.4 Automatic Sleep ModeAn important feature of the MultiMediaCard is automatic entrance and exit from sleep mode. Upon completion of an operation, the MultiMediaCard will enter the sleep mode to conserve power if no further commands are received within 5 msec The host does not have to take any action for this to occur. In most systems, the MultiMediaCard is in sleep mode except when the host is accessing it, thus conserving power. When the host is ready to access the MultiMediaCard and it is in sleep mode, any command issued to the MultiMediaCard will cause it to exit sleep and respond. The host does not have to issue a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead.2.5 Hot InsertionSupport for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. Please see connector data sheets for more details. This approach is similar to that used in PCMCIA to allow for hot insertion. This applies to both MultiMediaCard and SPI modes.2.6 MultiMediaCard Mode2.6.1 MultiMediaCard Standard ComplianceThe MultiMediaCard is fully compliant with MultiMediaCard standard specification V3.31.The structure of the Card Specific Data (CSD) register is compliant with CSD structure V1.2.2.6.2 Negotiating Operation ConditionsThe MultiMediaCard supports the operation condition verification sequence defined in the MultiMediaCard standard specifications. The MultiMediaCard host should define an operating voltage range that is not supported by the MultiMediaCard. It will put itself in an inactive state and ignore any bus communication. The only way to get the card out of the inactive state is by powering it down and up again. In addition the host can explicitly send the card to the inactive state by using the GO_INACTIVE_STATE command.2.6.3 Card Acquisition and IdentificationThe MultiMediaCard bus is a single master (MultiMediaCard host) and multi-slaves (cards) bus. The host can query the bus and find out how many cards of which type are currently connected. The MultiMediaCard’s CID register is pre-programmed with a unique card identification number which is used during the acquisition and identification procedureIn addition, the MultiMediaCard host can read the card’s CID register using the READ_CID MultiMediaCard command. The CID register is programmed during the MultiMediaCard testing and formatting procedure, on the manufacturing floor. The MultiMediaCard host can only read this register and not write to it.2.6.4 Card StatusMultiMediaCard status is stored in a 32 bit status register which is sent as the data field in the card respond to host commands. Status register provides information about the card’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.2.6.7 Data Protection in the Flash CardEvery sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.The MultiMediaCard can be considered error free and no additional data protection is needed. However, if an application uses additional, external, ECC protection, the data organization is defined in the user writeable section of the CSD register2.6.8 EraseThe smallest erasable unit in the MultiMediaCard is a erase group. In order to speed up the erase procedure, multiple erase groups can be erased in the same time. The erase operation is divided into two stages.Tagging - Selecting the Sectors for ErasingTo facilitate selection, a first command with the starting address is followed by a second command with the final address, and all erase groups within this range will be selected for erase.Erasing - Starting the Erase ProcessTagging can address erase groups. An arbitrary selection of erase groups may be erased at one time. Tagging and erasing must follow a strict command sequence (refer to the MultiMediaCard standard specification for details).2.6.9 Write ProtectionThe MultiMediaCard erase groups are grouped into write protection groups. Commands are provided for limiting and enabling write and erase privileges for each group individually. The current write protect map can be read using SEND_WRITE_PROT command.In addition two, permanent and temporary, card levels write protection options are available.Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared.The One Time Programmable (OTP) characteristic of the permanent write protect bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.10 Copy BitThe content of an MultiMediaCard can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared.The Copy bit of the MultiMediaCard is programmed (during test and formatting on the manufacturing floor) as a copy. The MultiMediaCard can be purchased with the copy bit set (copy) or cleared, indicating the card is a master.The One Time Programmable (OTP) characteristic of the Copy bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.11 The CSD RegisterAll the configuration information of the MultiMediaCard is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contains the host controlled data - the card Copy and write protection and the user ECC register.The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.2.7 SPI ModeThe SPI mode is a secondary (optional) communication protocol offered for MultiMediaCard. This mode is a subset of the MultiMediaCard protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.2.7.1 Negotiating Operation ConditionsThe operating condition negotiation function of the MultiMediaCard bus is not supported in SPI mode. The host must work within the valid voltage range (2.7 to 3.6 volts) of the card.2.7.2 Card Acquisition and IdentificationThe card acquisition and identification function of the MultiMediaCard bus is not supported in SPI mode. The host must know the number of cards currently connected on the bus. Specific card selection is done via the CS signal.2.7.3 Card StatusIn SPI mode only 16 bits (containing the errors relevant to SPI mode) can be read out of the MultiMediaCard status register.2.7.4 Memory Array PartitioningMemory partitioning in SPI mode is equivalent to MultiMediaCard mode. All read and write commands are byte addressable.2.7.5 Read and Write OperationsIn SPI mode, only single block read/write mode is supported.2.7.6 Data Transfer RateIn SPI mode only block mode is supported. The typical access time (latency) for each data block, in read operation, is 1.5mS. The write typical access time (latency) for each data block, in read operation, is 1.5mS. The write block operation is done in handshake mode. The card will keep DataOut line low as long as the write operation is in progress and there are no write buffers available.2.7.7 Data Protection in the MultiMediaCardSame as for the MultiMediaCard mode.2.7.8 EraseSame as in MultiMediaCard mode2.7.9 Write ProtectionSame as in MultiMediaCard modeFigure 3-1 Timing Diagram of Data Input and Output3.5 Physical SpecificationsDimensions of Normal MMC(24mm x 32mm x 1.4mm)Dimensions of RS-MMC(24mm x 18mm x 1.4mm)rising and falling edges). If the host does not allow the switchable R OD implementation, a fix R CMD can be used. Consequently the maximum operating implementation, a fix R CMD can be used. Consequently the maximum operating frequency in the open drain mode has to be reduced in this case.4.4 SPI Bus Topology4.4.1 SPI Interface ConceptThe Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on certain Motorola micro-controllers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the MultiMediaCard SPI channel consists of the following 4 signals:- CS : Host to card chip select signal- CLK : Host to card clock signal- DataIn : Host to card data signal- DataOut : Card to host data signalAnother SPI common characteristic, which is implemented in the MultiMediaCard card as well, is byte transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal. The SPI standard defines the physical link only and not the complete data transfer protocol. The MultiMediaCard uses a subset of the MultiMediaCard protocol and command set.4.4.2 SPI Bus TopologyThe MultiMediaCard card identification and addressing algorithms are replaced by hardware Chip Select (CS) signal. There are no broadcast commands. A card (slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 4-3). The CS signal bust is continuously active for the duration of the SPI transaction (command, response and data). The only exception is card-programming time. At this time the host can de-assert the CS signal without affecting the programming process. The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability of executing commands while data is being read or written and, therefore, eliminates the sequential and multi block read/write operations. The SPI channel supports only single block read/write.Figure 4-3 SPI Bus SystemReadThe read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay between the end bit of the read command and the start bit of the data block. This number is card dependent and should be used by the host to calculate throughput and the maximal frequency for stream read.WriteThe R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g. SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be used by the host to calculate throughput.EraseThe duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.4.8 Card Identification ModeAll the data communication in the card identification mode uses only the command line (CMD). MultiMediaCard State Diagram (Card Identification Mode)Figure 4-2 MultiMediaCard State Diagram (Card Identification Mode)The host starts the card identification process in open drain mode with the identification clock rate f OD(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must pick a common denominator for operation and notify the application that cards with out of range parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State (refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the register information from memory field) and is not ready yet for communication. In this case the host must repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a relative card address (RCA, shorter than CID), which will be used to address the card in future communication (faster than with the CID). Once the RCA is received the card transfers to the Standby State and does not react to further identification cycles. The card also switches the output drivers from the open-drain to the push-pull mode in this state. The host repeats the identification process as long as it receives a response (CID) to its identification command (CMD2). When no card responds to this command, all cards have been identified. The time-out condition to recognize this, is waiting for the start bit for more than 5 clock periods after sending CMD24.8.1 Operating Voltage Range ValidationThe MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The MultiMediaCard supports the range of 2.7 V to 3.6V supply voltage. So the MultiMediaCard sends a R3 response to CMD1 which contains an OCR value of 0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter “Responses”). By omitting the voltage range in the command, the host can query the card stack and determine the common voltage range before sending out-of-range cards into the Inactive State. This bus query should be used if the host is able to select a common voltage range or if a notification to the application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation and reissue CMD1 with this condition sending incompatible cards into the Inactive State.4.9 Data Transfer ModeWhen in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PushPull clock rate is equal to the slow f OpenDrain clock rate. SEND_CSD (CMD9) allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage capacity, maximum clock rate etc..。
DS12887时钟芯片_中文资料_
DS12887时钟芯片(中文资料一)特点·可作为IBM AT 计算机的时钟和日历·与MC14681B 和DS1287的管脚兼容·在没有外部电源的情况下可工作10年·自带晶体振荡器及电池·可计算到2100年前的秒、分、小时、星期、日期、月、年七种日历信息并带闰年补偿·用二进制码或BCD 码代表日历和闹钟信息·有12和24小时两种制式，12小时制时有AM 和PM提示·可选用夏令时模式·可以应用于MOTOROLA 和INTEL 两种总线·数据/地址总线复用·内建128字节RAM14字节时钟控制寄存器114字节通用RAM·可编程方波输出·总线兼容中断（/IRQ ）·三种可编程中断时间性中断可产生每秒一次直到每天一次中断周期性中断122ms 到500ms时钟更新结束中断管脚名称AD0－AD7－地址/数据复用总线 NC －空脚MOT －总线类型选择（MOTOROLA/INTEL ） CS －片选 AS －ALER/W －在INTEL 总线下作为/WR DS －在INTEL 总线下作为/RD RESET －复位信号 IRQ －中断请求输出 SQW －方波输出 VCC －+5电源 GND －电源地上电/掉电当VCC 高于4.25V200ms 后，芯片可以被外部程序操作；当VCC 低于4.25V 时，芯片处于写保护状态（所有的输入均无效），同时所有输出呈高阻状态；当VCC 低于3V 时，芯片将自动把供电方式切换为由内部电池供电。
管脚功能MOT （总线模式选择）当此脚接到VCC 时，选用的是MOTOROLA 总线时序；当它接到地或不接时，选用的是INTEL 总线时序。
SQW（方波输出）－当VCC低于4.25V时没有作用。
周期性中断率和方波中断频率表寄存器A中的控制位RS3 RS2 RS1 RS0 P1周期中断周期SQW输出频率0 0 0 0 无无0 0 0 1 3.90625ms 256Hz0 0 1 0 7.8125ms 128Hz0 0 1 1 122.070μs 8.192kHz0 1 0 0 244.141μs 4.096 kHz0 1 0 1 488.281μs 2.048 kHz0 1 1 0 976.5625μs 1.024 kHz0 1 1 1 1.953125ms 512 Hz1 0 0 0 3.90625 ms 256 Hz1 0 0 1 7.8125 ms 128 Hz1 0 1 0 15.625 ms 64 Hz1 0 1 1 31.25 ms 32 Hz1 1 0 0 62.5 ms 16 Hz1 1 0 1 125 ms 8 Hz1 1 1 0 250 ms 4 Hz1 1 1 1 500 ms2 HzAD0－AD7（双向数据/地址复用总线）AS（地址锁存）ALEDS（Data Strobe or Read Input） RD当系统选择的是INTEL总线模式时，DS被称作RD。
FPGA可编程逻辑器件芯片EP3C120F780C7N中文规格书
Signal Name Direction DescriptionPlatform Designer Interface Name Note: Because the signals are shared, an interface cannot issue or accept a write response and a read response in the same clock cycle.The following encodings are available:•00: OKAY - Successfulresponse for a transaction.•01: RESERVED -Encoding is reserved.•10: SLAVEERROR - Error from an endpoint slave.Indicates an unsuccessful transaction.•11: DECODEERROR -Indicates an attempted access to an undefined location.For read responses:•One response is sentwith each readdata . Aread burst length of N results in N responses. It is not valid to produce fewer responses, even in the event of an error . It is valid for the response signal values to be different for eachreaddata in the burst.•The interface must have read control signals.Pipeline support is possible with thereaddatavalid signal.•On a read error , thecorresponding readdatais a "don't care".4.3.1.4.2. Write Data Mover Avalon-ST Descriptor SinksThe Write Data Mover has two Avalon-ST sink interfaces to receive the descriptors that define the data transfers to be executed. One of the interfaces receives descriptors for normal data transfers, while the other receives descriptors for high-priority data transfers.The descriptor format for the Write Data Mover is described in the section Descriptor Formats for Data Movers .Note: The user application is responsible for performing the scheduling between priority and normal queues. No arbitration is performed inside the Write Data Mover .4.InterfacesUG-20237 | 2021.03.29Send FeedbackTable 34.Write Data Mover Avalon-ST Normal Descriptor Sink Interface Signal Name DirectionDescription Platform Designer Interface Name wrdm_desc_ready_o O When asserted, this readysignal indicates the normal descriptor queue in the Write Data Mover is ready to accept data. The ready latency of this interface is 3cycles.wrdm_descwrdm_desc_valid_i I When asserted, this signalqualifies valid data on any cycle where data is being transferred to the normal descriptor queue. On each cycle where this signal is active, the queue samples the data.wrdm_desc_data_i[173:0]I [173:160]: reserved. Should be tied to 0.[159:152]: descriptor ID[151:149] : application specific[148]: reserved[147]: single source (4)[146]: immediate (5)[145:128]: number of dwords to transfer up to 1MB[127:64]: destination PCIe address[63:0]: source Avalon-MMaddress / immediate data Table 35.Write Data Mover Avalon-ST Priority Descriptor Sink Interface(4)When the single source bit is set, the same source address is used for all the transfers. If the bit is not set, the address increments for each transfer . Note that in single source mode, the PCIe address and Avalon-MM address must be 64-byte aligned.(5)When set, the immediate bit indicates immediate writes. Immediate writes of one or two dwords are supported. For immediate transfers, bits [31:0] or [63:0] contain the payload for one- or two-dword transfers respectively. The two-dword immediate writes cannot cross a 4k boundary.4.InterfacesUG-20237 | 2021.03.29Send FeedbackSignal Name Direction DescriptionPlatform Designer Interface Namedescriptor queue. On each cycle where this signal is active, the queue samples the data.wrdm_prio_data_i[173:0]I [173:160]: reserved. Should be tied to 0.[159:152]: descriptor ID[151:149] : application specific[148]: reserved[147]: single source[146]: immediate[145:128]: number of dwords to transfer up to 1MB[127:64]: destination PCIe address[63:0]: source Avalon-MMaddress / immediate dataThe Write Data Mover internally supports two queues of descriptors. The priority queue has absolute priority over the normal queue, so it should be used carefully to avoid starving the normal queue.If the Write Data Mover receives a descriptor on the priority interface while processing a descriptor from the normal queue, it switches to processing descriptors from the priority queue after it has completed processing the current descriptor . The Write Data Mover resumes processing descriptors from the normal queue once the priority queue is empty. Do not use the same descriptor ID simultaneously in the two queues as there would be no way to distinguish them on the Status Avalon-ST source interface.The Write Data Mover handles one descriptor at a time. When a descriptor has been processed, the Write Data Mover will read the next descriptor from the priority or normal descriptor interface.Note: There is no buffer to store descriptors inside the Write Data Mover . In Intel's DMA design example, the buffer is located in the external DMA controller and supports up to 128 descriptors.Software should only send new descriptors when the Write Data Mover has processed all previously sent descriptors. The Write Data Mover indicates the completion of the its data processing by performing an immediate write to the system memory using the last descriptor in the descriptor table. For more details, refer to the Write DMA Example section in the P-tile Avalon Memory Mapped (Avalon-MM) IP for PCI Express Design Example User Guide (see the link in the Related Information below).Related InformationWrite DMA Example4.InterfacesUG-20237 | 2021.03.29Send Feedback。
OPA128JM中文资料
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1013 || 1 1015 || 2
nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fA, p-p fA/√Hz
Ω || pF Ω || pF
VOLTAGE RANGE(4)
Common-Mode Input Range
±10 ±12
±10 ±12
±10 ±12
±10 ±12
90dB min q IMPROVED REPLACEMENT FOR AD515
S9S08DZ128资料翻译
MC9S08DZ128MC9S08DZ96MC9S08DV128MC9S08DV96数据手册HCS08微处理控制器MC9S08DZ128第一版2008年5月飞思卡尔半导体MC9S08DZ128系列产品的特性8位HCSO8中央处理单元（CPU）•40-MHz HCS08 CPU（20-MHz总线）•HC08指令集，带附加的BGND指令•支持最多32个中断/复位源片内存储器•整个工作电压和温度范围内可读取/编程/擦除的Flash存储器•最大2K的EEPROM在线可编程内存；支持8字节单页或4字节双页擦除分区；执行Flash程序的同时可进行编程和擦除操作；支持擦除取消操作节能模式•两种非常低功耗停止模式•Reduced power wait mode降低功耗等待模式•超低功耗实时中断，在运行、等待和停止模式下均可操作时钟源选项•振荡器（XOSC）—闭环控制的皮尔斯（Pierce）振荡器；支持范围31.25 kHz至38.4 kHz或1 MHz至16MHz之间的晶体或陶瓷谐振器•多功能时钟生成器（MCG）—PLL和FLL模式（在使用内部温度补偿时FLL能够达到1.5%内的偏差）；带微调功能的内部参考时钟源；带可选择晶体振荡器或陶瓷谐振器的外部参考时钟源系统保护•监视微控制器（计算机）看门狗（COP）复位，支持备用专用1KHZ的内部时钟源或总线时钟操作的选项。
带有可选择的视窗化得操作•带复位和中断的低压检测电路；可选择的电压阀值•支持非法指令代码复位•支持非法操作地址复位•支持Flash与EEPROM块保护•支持时钟信号丢失保护开发支持•单线背景调试接口•总线实时捕获功能的上及在线仿真（ICE）外围设备•ADC（模数转换）24通道- 12位分辨率, 2.5μs转换时间, 自动比较功能，温度传感器，包含内部能兮参考源通道•ACMPx—两个模拟比较器，支持比较器输出的上升，下降或任意边缘触发的中断;可选择与内部能隙参考电压源比较；运行在STOP3模式；•MSCAN— CAN协议- Version 2.0 A, B; 支持标准和扩展数据帧；支持远程帧；5个带FIFO 存储框架的接收缓冲器；灵活的接收识别符过滤器，可编程如下：2 x 32位、4 x 16位或8 x 8位•SCIx—两个SCI，可支持LIN 2.0协议和SAE J2602协议；全双工；主节点支持break 信号生成；从节点支持break信号检测；支持激活边沿唤醒•SPIx—多达两个SPIs;全双工或单线双向;双重缓冲发送与接受;主从模式; 支持高位优先或低位优先的移动•IICx—多达两个IICs; 支持最高100kps的总线负载; 多主节点模式运行;可编程的从地址; 通用呼叫地址; 逐字节传输驱动的中断r•TPMx—一个6通道(TPM1), 一2通道(TPM2)和一个4通道(TPM3);可支持输入捕捉, 输出比较, 或每个通道带缓冲的边沿对齐PWM输出。
飞思卡尔MC9S12XS128技术手册翻译AD
飞思卡尔MC9S12XS128技术手册（AD转换部分）英文资料:飞思卡尔MC9S12XS256RMV1官方技术手册1.1 XS12系列单片机的特点XS12系列单片机特点如下：·16位S12CPU—向上支持S12模糊指令集并去除了其中的MEM, WAV, WAVR, REV, REVW 五条指令；—模块映射地址机制（MMC）；—背景调试模块（BDM）；·CRG时钟和复位发生器—COP看门狗；—实时中断；·标准定时器模块—8个16位输入捕捉或输出比较通道；；—16位计数器，8位精密与分频功能；—1个16位脉冲累加器；·周期中断定时器PIT—4具有独立溢出定时的定时器；—溢出定时可选范围在1到2^24总线时钟；—溢出中断和外部触发器；·多达8个的8位或4个16位PWM通道—每个通道的周期和占空比有程序决定；—输出方式可以选择左对齐或中心对其；—可编程时钟选择逻辑，且可选频率范围很宽；·SPI通信模块—可选择8位或16位数据宽度；—全双工或半双工通信方式；—收发双向缓冲；—主机或从机模式；—可选择最高有效为先输出或者最低有效位先输出；·两个SCI串行通信接口—全双工或半双工模式·输入输出端口—多达91个通用I/O引脚，根据封装方式，有些引脚未被引出；—两个单输入引脚；·封装形式—112引脚薄型四边引线扁平封装（LQFP）；—80引脚扁平封装（QFP）；—64引脚LQFP封装；·工作条件—全功率模式下单电源供电范围3.15V到5V；—CPU总线频率最大为40MHz—工作温度范围–40 C到125 C第十章模拟—数字转换10.1 介绍ADC12B16C是一个16通道，12位，复用方式输入逐次逼近模拟—数字转换器。
ATD的精度由电器规格决定。
10.1.1 特点·可设置8位、10位、12位精度·在停止模式下，ATD转换使用内部时钟·转换序列结束后自动进入低耗电模式·可编程采样时间·转化结果可选择左对齐或右对齐·外部触发控制·转换序列结束后产生中断·模拟输入的16个通道为复用方式·可以选择VRH、VRL、 (VRL+VRH)/2特殊转换方式·转换序列长度1到16·可选择连续转换方式·多通道扫描·任何AD通道均可配置外部触发功能，并且可选择4种额外的触发输入。