10计数输出 CD4017-4022

© 2002 Fairchild Semiconductor CorporationDS005950October 1987Revised March 2002CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8 Decoded OutputsCD4017BC • CD4022BCDecade Counter/Divider with 10 Decoded Outputs •Divide-by-8 Counter/Divider with 8 Decoded OutputsGeneral DescriptionThe CD4017BC is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit.The CD4022BC is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit.These counters are cleared to their zero count by a logical “1” on their reset line. These counters are advanced on the positive edge of the clock signal when the clock enable sig-nal is in the logical “0” state.The configuration of the CD4017BC and CD4022BC per-mits medium speed operation and assures a hazard free counting sequence. The 10/8 decoded outputs are nor-mally in the logical “0” state and go to the logical “1” state only at their respective time slot. Each decoded output remains high for 1 full clock cycle. The carry-out signal completes a full cycle for every 10/8 clock input cycles and is used as a ripple carry signal to any succeeding stages.Featuress Wide supply voltage range: 3.0V to 15V s High noise immunity:0.45 V DD (typ.)s Low power Fan out of 2 driving 74LTTL compatibility:or 1 driving 74LS s Medium speed operation: 5.0 MHz (typ.)with 10V V DD s Low power:10 µW (typ.)s Fully static operationApplications•Automotive •Instrumentation •Medical electronics •Alarm systems •Industrial electronics •Remote meteringOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Connection DiagramsPin Assignments for DIP , SOIC and SOPCD4017BTop ViewPin Assignments for DIP and SOICCD4022BTop ViewOrder Number Package NumberPackage DescriptionCD4017BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4017BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4017BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide CD4022BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow CD4022BCNN16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide查询CD4017BC供应商 2C D 4017B C • C D 4022B CLogic DiagramsCD4017BTerminal No. 8 = GND Terminal No. 16 = V DDCD4022BTerminal No. 16 = V DD Terminal No. 8 = GNDCD4017BC • CD4022BCAbsolute Maximum Ratings (Note 1)(Note 2)Recommended Operating Conditions (Note 2)Note 1: “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices should be operated at these limits. The table of “Recom-mended Operating Conditions ” and “Electrical Characteristics ” provides conditions for actual device operation.Note 2: V SS = 0V unless otherwise specified.DC Electrical Characteristics (Note 2)Note 3: I OL and I OH are tested one output at a time.DC Supply Voltage (V DD )−0.5 V DC to +18 V DC Input Voltage (V IN )−0.5 V DC to V DD +0.5 V DCStorage Temperature (T S )−65°C to +150°CPower Dissipation (P D )Dual-In-Line 700 mW Small Outline 500 mWLead Temperature (T L )(Soldering, 10 seconds)260°C DC Supply Voltage (V DD )+3 V DC to +15 V DCInput Voltage (V IN )0 to V DD V DCOperating Temperature Range (T A )−55°C to +125°CSymbol ParameterConditions−55°C +25°+125°C UnitsMinMax MinTyp Max MinMax I DDQuiescent Device V DD = 5V 50.35150µACurrentV DD = 10V 100.510300V DD = 15V 20 1.020600V OLLOW Level |I O | < 1.0 µA Output VoltageV DD = 5V 0.0500.050.05VV DD = 10V 0.0500.050.05V DD = 15V0.0500.050.05V OHHIGH Level |I O | < 1.0 µA Output VoltageV DD = 5V 4.95 4.955 4.95VV DD = 10V 9.959.95109.95V DD = 15V14.9514.951514.95V ILLOW Level |I O | < 1.0 µAInput VoltageV DD = 5V, V O = 0.5V or 4.5V 1.5 1.5 1.5VV DD = 10V, V O = 1.0V or 9.0V 3.0 3.0 3.0V DD = 15V, V O = 1.5V or 13.5V4.04.0 4.0V IHHIGH Level |I O | < 1.0 µAInput VoltageV DD = 5V, V O = 0.5V or 4.5V 3.5 3.5 3.5VV DD = 10V, V O = 1.0V or 9.0V 7.07.07.0V DD = 15V, V O = 1.5V or 13.5V11.011.011.0I OLLOW Level Output V DD = 5V, V O = 0.4V 0.640.510.880.36mACurrent (Note 3)V DD = 10V, V O = 0.5V 1.6 1.3 2.250.9V DD = 15V, V O = 1.5V 4.2 3.48.8 2.4I OHHIGH Level Output V DD = 5V, V O = 4.6V −0.25−0.2−0.36−0.14mA Current (Note 3)V DD = 10V, V O = 9.5V −0.62−0.5−0.9−0.35V DD = 15V, V O = 13.5V −1.8−1.5−3.5−1.1I INInput CurrentV DD = 15V, V IN = 0V −0.1−10−5−0.1−1.0µA V DD = 15V, V IN = 15V0.110−50.11.0 4C D 4017B C • C D 4022B CAC Electrical Characteristics (Note 4)T A = 25°C, C L = 50 pF, R L = 200k, t rCL and t fCL = 20 ns, unless otherwise specified Note 4: AC Parameters are guaranteed by DC correlated testing.AC Electrical Characteristics (Note 4)T A = 25°C, C L = 50 pF, R L = 200k, t rCL and t fCL = 20 ns, unless otherwise specifiedSymbolParameter Conditions Min Typ Max UnitsCLOCK OPERATIONt PHL, t PLH Propagation Delay Time Carry Out LineV DD = 5V 415800nsV DD = 10V 160320V DD = 15V130250Carry Out LineV DD = 5V C L = 15 pF240480nsV DD = 10V 85170V DD = 15V70140Decode Out LinesV DD = 5V 5001000nsV DD = 10V 200400V DD = 15V160320t TLH , t THL Transition Time Carry Out and Decode Out Linest TLHV DD = 5V 200360nsV DD = 10V 100180V DD = 15V80130t THLV DD = 5V 100200nsV DD = 10V 50100V DD = 15V4080f CLMaximum Clock FrequencyV DD = 5V Measured with 1.02MHzV DD = 10V Respect to Carry 2.55V DD = 15VOutput Line3.06t WL , t WHMinimum Clock Pulse WidthV DD = 5V 125250ns V DD = 10V 4590V DD = 15V3570t rCL , t fCLClock Rise and Fall TimeV DD = 5V 20µs V DD = 10V 15V DD = 15V5t SUMinimum Clock Inhibit Data Setup TimeV DD = 5V 120240ns V DD = 10V 4080V DD = 15V3265C INAverage Input Capacitance57.5pF Symbol ParameterConditionsMinTypMaxUnitsRESET OPERATION t PHL, tPLHPropagation Delay Time Carry Out LineV DD = 5V 415800nsV DD = 10V 160320V DD = 15V130250Carry Out LineV DD = 5V 240480ns V DD = 10V C L = 15 pF85170V DD = 15V70140Decode Out LinesV DD = 5V 5001000ns V DD = 10V 200400V DD = 15V160320t WMinimum Reset V DD = 5V 200400ns Pulse WidthV DD = 10V 70140V DD = 15V 55110t REMMinimum Reset V DD = 5V 75150ns Removal TimeV DD = 10V 3060V DD = 15V2550CD4017BC • CD4022BCTiming DiagramsCD4017BCD4022B 6C D 4017B C • C D 4022B CPhysical Dimensionsinches (millimeters) unless otherwise noted16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" NarrowPackage Number M16ACD4017BC • CD4022BCPhysical Dimensionsinches (millimeters) unless otherwise noted (Continued)16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M16D8C D 4017B C • C D 4022B C D e c a d e C o u n t e r /D i v i d e r w i t h 10 D e c o d e d O u t p u t s • D i v i d e -b y -8 C o u n t e r /D i v i d e r w i t h 8D e c o d e d O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePackage Number N16EFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。