SN74HCT574PWT中文资料
74HC75PW资料
74HC75Quad bistable transparant latchRev. 03 — 12 November 2004Product data sheet1.General descriptionThe 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low powerSchottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDECstandard no.7A.The 74HC75 has four bistable latches. The two latches are simultaneously controlled byone of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the dataenters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs(nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up timeprior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latchedoutputs remain stable as long as the LEnn is LOW.2.Featuress Complementary Q and Q outputss V CC and GND on the center pinss Low-power dissipations Complies with JEDEC standard no.7As ESD protection:x HBM EIA/JESD22-A114-B exceeds 2000Vx MM EIA/JESD22-A115-A exceeds 200V.s Multiple package optionss Specified from−40°C to+80°C and from−40°C to+125°C.3.Quick reference data[1]C PD is used to determine the dynamic power dissipation (P D in µW).P D =C PD ×V CC 2×f i ×N +∑(C L ×V CC 2×f o )where:f i =input frequency in MHz;f o =output frequency in MHz;C L =output load capacitance in pF;V CC =supply voltage in V;N =number of inputs switching;∑(C L ×V CC 2×f o )= sum of outputs.4.Ordering informationTable 1:Quick reference data Symbol Parameter Conditions Min Typ Max Unitt PHL , t PLHpropagation delay C L =15pF;V CC =5VnD to nQ, nQ -11-ns LEnn to nQ, nQ-11-ns C I input capacitance - 3.5-pF C PDpower dissipation capacitance per latchV I =GND to V CC[1]-42-pFTable 2:Ordering informationType numberPackageTemperature rangeName DescriptionVersion 74HC75N −40°C to +125°C DIP16plastic dual in-line package; 16leads (300mil)SOT38-474HC75D −40°C to +125°C SO16plastic small outline package; 16leads;body width 3.9mmSOT109-174HC75DB −40°C to +125°C SSOP16plastic shrink small outline package; 16leads;body width 5.3mmSOT338-174HC75PW−40°C to +125°CTSSOP16plastic thin shrink small outline package;16leads; body width 4.4mmSOT403-15.Functional diagramFig 1.Functional diagram Fig 2.Logic symbol001aab853L1D CP16213Q1L2D CP153Q14L3D CP10641D LE122D3D LE34Q11L4D CP974DQ81Q 1Q2Q 2Q3Q 3Q4Q 4Q001aab8511D LE12L1,2L3,4LE341341Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q2D3D 4D891110141511627636.Pinning information6.1PinningFig 3.IEC logic symbol Fig 4.Logic diagram001aab8524C171D986101113C121D16131514001aab854LATCH 1D CP 1Q 1D LE12Q 1QLATCH 2D CP 2Q 2D Q 2QLATCH 3D CP 3Q 3D LE34Q 3QLATCH 4D CP 4Q 4D Q 4QFig 5.Pin configuration751Q 1Q 1D 2Q 2D 2Q LE34LE12V CC GND 3D 3Q 4D 3Q 4Q4Q001aab850123456781091211141316156.2Pin descriptionTable 3:Pin descriptionSymbol Pin Description1Q1complementary latch output 11D2data input 12D3data input 2LE344latch enable input for latches 3 and 4 (active HIGH)V CC5positive supply voltage3D6data input 34D7data input 44Q8complementary latch output 44Q9latch output 43Q10latch output 33Q11complementary latch output 3GND12ground (0V)LE1213latch enable input for latches 1 and 2 (active HIGH)2Q14complementary latch output 22Q15latch output 21Q16latch output 17.Functional description7.1Function tableTable 4:Function table[1]Operating mode Input OutputLEnn nD nQ nQData enabled H L L HH H H LData latched L X q q[1]H=HIGH voltage level;L=LOW voltage level;q=lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOWLEnn transition;X=don’t care.8.Limiting values[1]Above 70°C: P tot derates linearly with 12mW/K.[2]Above 70°C: P tot derates linearly with 8mW/K.9.Recommended operating conditionsTable 5:Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).Symbol Parameter ConditionsMin Max Unit V CC supply voltage −0.5+7V I IK input diode current V I <−0.5V or V I >V CC +0.5 V -±20mA I OK output diode current V O <−0.5V or V O >V CC +0.5V-±20mA I O output source or sink currentV O =−0.5V to V CC +0.5V-±25mA I CC , I GND V CC or GND current -±50mA T stg storage temperature −65+150°C P totpower dissipation DIP16 package [1]-750mW SO16, SSOP16 and TSSOP16 packages[2]-500mWTable 6:Recommended operating conditions Symbol Parameter ConditionsMin Typ Max Unit V CC supply voltage 2.0 5.0 6.0V V I input voltage 0-V CC V V O output voltage 0-V CC V t r , t finput rise and fall timesV CC = 2.0 V --1000ns V CC = 4.5 V - 6.0500ns V CC = 6.0 V--400ns T ambambient temperature−40-+125°C10.Static characteristicsTable 7:Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground=0V).Symbol Parameter Conditions Min Typ Max Unit T amb=25°CV IH HIGH-level input voltage V CC=2.0V 1.5 1.2-VV CC=4.5V 3.15 2.4-VV CC=6.0V 4.2 3.2-VV IL LOW-level input voltage V CC=2.0V-0.80.5VV CC=4.5V- 2.1 1.35VV CC=6.0V- 2.8 1.8VV OH HIGH-level output voltage V I=V IH or V ILI O=−20µA; V CC=2.0V 1.9 2.0-VI O=−20µA; V CC=4.5V 4.4 4.5-VI O=−20µA; V CC=6.0V 5.9 6.0-VI O=−4mA; V CC=4.5V 3.98 4.32-VI O=−5.2mA; V CC=6.0V 5.48 5.81-VV OL LOW-level output voltage V I=V IH or V ILI O=20µA; V CC=2.0V-00.1VI O=20µA; V CC=4.5V-00.1VI O=20µA; V CC=6.0V-00.1VI O=4mA; V CC=4.5V-0.150.26VI O=5.2mA; V CC=6.0V-0.160.26VI LI input leakage current V I=V CC or GND; V CC=6.0V--±0.1µA--8.0µA I CC quiescent supply current V I=V CC or GND; I O=0A;V CC=6.0VC I input capacitance- 3.5-pF T amb=−40°C to +85°CV IH HIGH-level input voltage V CC=2.0V 1.5--VV CC=4.5V 3.15--VV CC=6.0V 4.2--VV IL LOW-level input voltage V CC=2.0V--0.5VV CC=4.5V-- 1.35VV CC=6.0V-- 1.8VV OH HIGH-level output voltage V I=V IH or V ILI O=−20µA; V CC=2.0V 1.9--VI O=−20µA; V CC=4.5V 4.4--VI O=−20µA; V CC=6.0V 5.9--VI O=−4mA; V CC=4.5V 3.84--VI O=−5.2mA; V CC=6.0V 5.34--VV OL LOW-level output voltage V I=V IH or V ILI O=20µA; V CC=2.0V--0.1VI O=20µA; V CC=4.5V--0.1VI O=20µA; V CC=6.0V--0.1VI O=4mA; V CC=4.5V--0.33VI O=5.2mA; V CC=6.0V--0.33V I LI input leakage current V I=V CC or GND; V CC=6.0V--±1.0µA I CC quiescent supply current V I=V CC or GND; I O=0A;V CC=6.0V--80µA T amb=−40°C to +125°CV IH HIGH-level input voltage V CC=2.0V 1.5--VV CC=4.5V 3.15--VV CC=6.0V 4.2--V V IL LOW-level input voltage V CC=2.0V--0.5VV CC=4.5V-- 1.35VV CC=6.0V-- 1.8V V OH HIGH-level output voltage V I=V IH or V IL-I O=−20µA; V CC=2.0V 1.9--VI O=−20µA; V CC=4.5V 4.4--VI O=−20µA; V CC=6.0V 5.9--VI O=−4mA; V CC=4.5V 3.7--VI O=−5.2mA; V CC=6.0V 5.2--V V OL LOW-level output voltage V I=V IH or V IL-I O=20µA; V CC=2.0V--0.1VI O=20µA; V CC=4.5V--0.1VI O=20µA; V CC=6.0V--0.1VI O=4mA; V CC=4.5V--0.4VI O=5.2mA; V CC=6.0V--0.4V I LI input leakage current V I=V CC or GND; V CC=6.0V--±1.0µAI CC quiescent supply current V I=V CC or GND; I O=0A;V CC=6.0V --160µATable 7:Static characteristics …continuedAt recommended operating conditions; voltages are referenced to GND (ground=0V).Symbol Parameter Conditions Min Typ Max Unit11.Dynamic characteristicsTable 8:Dynamic characteristicsGND=0 V; t r=t f=6 ns; C L=50 pF; unless otherwise specified, see Figure10.Symbol Parameter Conditions Min Typ Max Unit T amb = 25°Ct PHL, t PLH propagation delaynD to nQ see Figure6V CC = 2.0 V-33110ns V CC = 4.5 V-1222ns V CC = 6.0 V-1019ns V CC=5.0V; C L=15pF-11-nspropagation delay nD to nQ see Figure7V CC = 2.0 V-39120ns V CC = 4.5 V-1424ns V CC = 6.0 V-1120ns V CC=5.0V; C L=15pF-11-nspropagation delay LEnn to nQ see Figure9V CC = 2.0 V-33120ns V CC = 4.5 V-1224ns V CC = 6.0 V-1020ns V CC=5.0V; C L=15pF-11-nspropagation delay LEnn to nQ see Figure9V CC = 2.0 V-39125ns V CC = 4.5 V-1425ns V CC = 6.0 V-1121ns V CC=5.0V; C L=15pF-11-nst THL, t TLH output transition time see Figure6 and7V CC = 2.0 V-1975nsV CC = 4.5 V-715nsV CC = 6.0 V-613nst W enable pulse widthHIGH see Figure9V CC = 2.0 V8017-ns V CC = 4.5 V166-ns V CC = 6.0 V145-nst su set-up time nD toLEnn see Figure8V CC = 2.0 V6014-ns V CC = 4.5 V125-ns V CC = 6.0 V104-nst h hold time nD to LEnn see Figure8V CC = 2.0 V3−8-nsV CC = 4.5 V3−3-nsV CC = 6.0 V3−2-nsC PDpower dissipation capacitance per latch V I =GND to V CC[1]-42-pFT amb =−40°C to +85°C t PHL , t PLHpropagation delay nD to nQsee Figure 6V CC = 2.0 V --140ns V CC = 4.5 V --28ns V CC = 6.0 V--24nspropagation delay nD to nQsee Figure 7V CC = 2.0 V --150ns V CC = 4.5 V --30ns V CC = 6.0 V--26nspropagation delay LEnn to nQsee Figure 9V CC = 2.0 V --150ns V CC = 4.5 V --30ns V CC = 6.0 V--26nspropagation delay LEnn to nQsee Figure 9V CC = 2.0 V --155ns V CC = 4.5 V --31ns V CC = 6.0 V--26nst THL , t TLHoutput transition timesee Figure 6 and 7V CC = 2.0 V --95ns V CC = 4.5 V --19ns V CC = 6.0 V--16nst Wenable pulse width HIGHsee Figure 9V CC = 2.0 V 100--ns V CC = 4.5 V 20--ns V CC = 6.0 V17--nst suset-up time nD to LEnnsee Figure 8V CC = 2.0 V 75--ns V CC = 4.5 V 15--ns V CC = 6.0 V13--nst hhold time nD to LEnnsee Figure 8V CC = 2.0 V 3--ns V CC = 4.5 V 3--ns V CC = 6.0 V3--nsTable 8:Dynamic characteristics …continuedGND =0 V; t r =t f =6 ns; C L =50 pF; unless otherwise specified, see Figure 10.Symbol ParameterConditions Min Typ Max Unit[1]C PD is used to determine the dynamic power dissipation (P D in µW).P D =C PD ×V CC 2×f i ×N +∑(C L ×V CC 2×f o )where:f i =input frequency in MHz;f o =output frequency in MHz;C L =output load capacitance in pF;V CC =supply voltage in V;N =number of inputs switching;∑(C L ×V CC 2×f o )= sum of outputs.T amb =−40°C to +125°Ct PHL , t PLHpropagation delay nD to nQsee Figure 6V CC = 2.0 V --165ns V CC = 4.5 V --33ns V CC = 6.0 V--28ns propagation delay nD to nQsee Figure 7V CC = 2.0 V --180ns V CC = 4.5 V --36ns V CC = 6.0 V--31ns propagation delay LEnn to nQsee Figure 9V CC = 2.0 V --180ns V CC = 4.5 V --36ns V CC = 6.0 V--31ns propagation delay LEnn to nQsee Figure 9V CC = 2.0 V --190ns V CC = 4.5 V --38ns V CC = 6.0 V--32ns t THL , t TLHoutput transition timesee Figure 6 and 7V CC = 2.0 V --110ns V CC = 4.5 V --22ns V CC = 6.0 V--19ns t Wenable pulse width HIGHsee Figure 9V CC = 2.0 V 120--ns V CC = 4.5 V 24--ns V CC = 6.0 V20--ns t suset-up time nD to LEnnsee Figure 8V CC = 2.0 V 90--ns V CC = 4.5 V 18--ns V CC = 6.0 V15--ns t hhold time nD to LEnnsee Figure 8V CC = 2.0 V 3--ns V CC = 4.5 V 3--ns V CC = 6.0 V3--nsTable 8:Dynamic characteristics …continuedGND =0 V; t r =t f =6 ns; C L =50 pF; unless otherwise specified, see Figure 10.Symbol Parameter Conditions Min Typ Max Unit12.WaveformsV M = 0.5×V I .Fig 6.Waveforms showing the data input (nD)to output (nQ)propagation delays and theoutput transition timesV M = 0.5×V I .Fig 7.Waveforms showing the data input (nD)to output (nQ)propagation delays and theoutput transition timesThe shaded areas indicate when the input is permitted to change for predictable output performance.V M = 0.5×V I .Fig 8.Waveforms showing the data set-up and hold times for nD input to LEnn input001aab855nD inputnQ outputV Mt PHLt THL t TLHt PLHV M001aab856nD inputnQ outputV Mt PHLt THL t TLHt PLHV Mt sut h nQ output LEnn inputV MV M001aab858t sut hnD inputQ = D Q = DV M = 0.5×V I .Fig 9.Waveforms showing the latch enable input (LEnn) pulse width, the latch enableinput to outputs (nQ, nQ) propagation delays and the output transition timesTest data is given in T able 9.Definitions for test circuit:R T = Termination resistance should be equal to output impedance Z o of the pulse generator.C L = Load capacitance including jig and probe capacitance.Fig 10.Load circuitry for switching times Table 9:Test dataSupply Input Load V CC V I t r , t f C L 2.0 V V CC 6 ns 50 pF 4.5 V V CC 6 ns 50 pF 6.0 V V CC 6 ns 50 pF 5.0 VV CC6 ns15 pFnD inputLEnn inputnQ outputnQ outputt W V M V MV M 001aab857t PHLt PLHt THLt TLH t THLt PLHt PHLt TLHmna101V CCV IV OR TC LPULSE GENERATORD.U.T.13.Package outlineFig 11.Package outline SOT38-4 (DIP16)REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDECJEITASOT38-495-01-1403-02-13M Hc(e )1M EALs e a t i n g p l a n eA 1w Mb 1b 2eDA 2Z16198Epin 1 indexb0510 mmscaleNote1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.UNIT Amax.12b 1(1)(1)(1)b 2c D E e M Z H L mm DIMENSIONS (inch dimensions are derived from the original mm dimensions)A min. A max.b max.w M E e 11.731.300.530.380.360.2319.5018.55 6.486.20 3.603.050.2542.547.628.257.8010.08.30.764.20.51 3.2inches0.0680.0510.0210.0150.0140.0091.250.850.0490.0330.770.730.260.240.140.120.010.10.30.320.310.390.330.030.170.020.13DIP16: plastic dual in-line package; 16 leads (300 mil)SOT38-4Fig 12.Package outline SOT109-1 (SO16)Xw MθAA 1A 2b pD H EL pQdetail XE Z ecL v M A(A )3A89116ypin 1 indexUNIT Amax.A 1A 2A 3b p c D (1)E (1)(1)e H E L L p Q Z y w v θREFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IEC JEDEC JEITAmm inches1.750.250.101.451.250.250.490.360.250.1910.09.84.03.8 1.27 6.25.80.70.60.70.380oo 0.250.1DIMENSIONS (inch dimensions are derived from the original mm dimensions)Note1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.1.00.4 SOT109-199-12-2703-02-19076E07MS-0120.0690.0100.0040.0570.0490.010.0190.0140.01000.00750.390.380.160.150.051.050.0410.2440.2280.0280.0200.0280.0120.010.250.010.0040.0390.0160 2.5 5 mmscaleSO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1Fig 13.Package outline SOT338-1 (SSOP16)UNIT A 1A 2A 3b p c D (1)E (1)e H E L L p Q Z y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDEC JEITAmm0.210.051.801.650.250.380.250.200.096.46.05.45.20.651.257.97.61.030.630.90.71.000.5580oo 0.130.20.1DIMENSIONS (mm are the original dimensions)Note1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.SOT338-199-12-2703-02-19(1)w Mb pD H EE Z ecv M AXAy18169θAA 1A 2L p Qdetail XL(A )3MO-150pin 1 index0 2.5 5 mmscaleSSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1Amax.2Fig 14.Package outline SOT403-1 (TSSOP16)UNIT A 1A 2A 3b p c D (1)E (2)(1)e H E L L p Q Z y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDEC JEITAmm0.150.050.950.800.300.190.20.15.14.94.54.30.656.66.20.40.30.400.0680oo 0.130.10.21DIMENSIONS (mm are the original dimensions)Notes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.0.750.50SOT403-1MO-15399-12-2703-02-18w Mb pD Ze0.2518169θAA 1A 2L p Qdetail XL(A )3H EE cv M AXAy0 2.5 5 mmscaleTSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1Amax.1.1pin 1 index14.Revision historyTable 10:Revision historyDocument ID Release date Data sheet status Change notice Doc. number Supersedes74HC75_320041112Product data sheet-9397 750 1381674HC_HCT75_CNV_2 Modifications:•The format of this data sheet has been redesigned to comply with the current presentation andinformation standard of Philips Semiconductors.•Removed type number 74HCT75.•Inserted family specification.74HC_HCT75_CNV_219970918Product specification--74HC_HCT75_174HC_HCT75_119901201Product specification---15.Data sheet status[1]Please consult the most recently issued data sheet before initiating or completing a design.[2]The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL .[3]For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.16.DefinitionsShort-form specification —The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.17.DisclaimersLife support —These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.Right to make changes —Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’),relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to theseproducts,and makes no representations or warranties that these products are free from patent,copyright,or mask work right infringement,unless otherwise specified.18.Contact informationFor additional information, please visit: For sales office addresses, send an email to: sales.addresses@Level Data sheet status [1]Product status [2][3]DefinitionI Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.IIPreliminary dataQualificationThis data sheet contains data from the preliminary specification.Supplementary data will be published at a later date.Philips Semiconductors reserves the right to change the specification without notice,in order to improve the design and supply the best possible product.III Product data ProductionThis data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design,manufacturing and supply.Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).19.Contents1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Quick reference data. . . . . . . . . . . . . . . . . . . . . 24Ordering information. . . . . . . . . . . . . . . . . . . . . 25Functional diagram . . . . . . . . . . . . . . . . . . . . . . 36Pinning information. . . . . . . . . . . . . . . . . . . . . . 46.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 57Functional description . . . . . . . . . . . . . . . . . . . 57.1Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 58Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 69Recommended operating conditions. . . . . . . . 610Static characteristics. . . . . . . . . . . . . . . . . . . . . 711Dynamic characteristics . . . . . . . . . . . . . . . . . . 912Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213Package outline . . . . . . . . . . . . . . . . . . . . . . . . 1414Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1815Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 1916Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1917Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1918Contact information . . . . . . . . . . . . . . . . . . . . 19© Koninklijke Philips Electronics N.V.2004All rights are reserved.Reproduction in whole or in part is prohibited without the priorwritten consent of the copyright owner.The information presented in this document doesnot form part of any quotation or contract,is believed to be accurate and reliable and maybe changed without notice.No liability will be accepted by the publisher for anyconsequence of its use.Publication thereof does not convey nor imply any license underpatent- or other industrial or intellectual property rights.Date of release: 12 November 2004Document number: 9397 750 13816。
HD74BC574AT中文资料
HD74BC574AOctal D Type Flip Flops With 3 State OutputsADE-205-042A (Z)2nd. EditionSep. 2000 DescriptionThe HD74BC574A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight edge triger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the strage elements.Features• Input/Output are at high impedance state when power supply is off.• Built in input pull up circuit can make input pins be open, when not used.• TTL level input• Wide operating temperature rangeTa = –40 to + 85°CHD74BC574A2Function TableInputsOutput Control CKD Output QL H HL L L L L X Q 0H X XZH :High level L :Low level X :ImmaterialZ:High impedance: Low to high transition Q 0:Level of Q before the indicated steady state input conditions were established.Pin ArrangementHD74BC574A3Absolute Maximum RatingsItemSymbol Rating Unit Supply voltage V CC –0.5 to +7.0V Input diode current I IK ±30mA Input voltage V IN –0.5 to +7.5V Output voltage V OUT –0.5 to +7.5V Off state output voltage V OUT(off)–0.5 to +5.5V Storage temperature Tstg–65 to +150°CNote:1.The absolute maximum ratings are values which must not individually be exceeded, andfurthermore, no two of which may be realized at the same time.Recommended Operating ConditionsItemSymbol Min Typ Max Unit Supply voltage V CC 4.5 5.0 5.5V Input voltage V IN 0—V CC V Output voltage V OUT 0—V CC V Operating temperature Topr –40—85°C Input rise/fall time*1t r , t f—8ns/VNote:1.This item guarantees maximum limit when one input switches.Waveform: Refer to test circuit of switching characteristics.HD74BC574A Logic Diagram4HD74BC574A5Electrical Characteristics (Ta = –40°C to +85°C)Item Symbol V CC (V)Min Max Unit Test ConditionsInput voltage V IH 2.0—V V IL —0.8V Output voltageV OH 4.5 2.4—V I OH = –3 mA 4.5 2.0—V I OH = –15 mA V OL4.5—0.4V I OL = 24 mA 4.5—0.5V I OL = 48 mA Input diode voltage V IK 4.5—–1.2V I IN = –18 mA Input currentI I5.5—–250µA V IN = 0 V 5.5— 1.0µA V IN = 5.5 V 5.5—100µA V IN = 7.0 V Short circuit output current*1I OS 5.5–100–225mA V IN = 0 or 5.5 V Off state output current I OZH 5.5—50µA V O = 2.7 V I OZL 5.5—–50µA V O = 0.5 V Supply currentI CCL 5.5—29.5mA V IN = 0 or 5.5 V All outputs is “L”I CCH 5.5— 2.5mA V IN = 0 or 5.5 V All outputs is “H”I CCZ 5.5— 2.5mA V IN = 0 or 5.5 V All outputs is “Z”I CCT *25.5—1.5mAV IN = 3.4 or 0.5 V Notes: 1.Not more than one output should be shorted at a time and duration of the short circuit should notexceed one second.2.When input by the TTL level, it shows I CC increase at per one input pin.HD74BC574A6Switching Test Method (C L = 50 pF)Ta = 25°C V CC = 5.0 VTa = –40 to 85°C V CC = 5.0 V ±10%Item SymbolMin Max Min Max Unit Test conditions Propagation CK →Q t PLH3.08.0 3.010.0nsSee under figuredelay time t PHL 3.08.0 3.010.0Output enable time t ZH 3.09.0 3.011.0ns t ZL 3.09.0 3.011.0Output disable time t HZ 3.08.0 3.010.0ns t LZ 3.08.0 3.010.0Setup time t s (H) 2.0— 2.0—ns t s (L) 2.0— 2.0—Hold time t h (H) 2.0— 2.0—ns t h (L) 2.0— 2.0—Pulse width t W (H) 6.0— 6.0—ns t W (L) 6.0—6.0—Input capacitance C IN 3.0 (Typ)——pF V IN = V CC or GND Output capacitanceC O15.0 (Typ)—pFV O = V CC or GNDTest CircuitHD74BC574A Waveforms-1Waveforms-27HD74BC574A8Waveforms-3Notes:1.t r = 2.5 ns, t f = 2.5 ns2.Input waveform: PRR = 1 MHz, duty cycle 50%3.Waveform-A shows input conditions such that the output is “L” level when enable by the output control.4.Waveform-B shows input conditions such that the output is “H” level when enable by the output control.HD74BC574A Package Dimensions9HD74BC574A10HD74BC574A11Cautions 1.Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,copyright, trademark, or other intellectual property rights for information contained in this document.Hitachi bears no responsibility for problems that may arise with third party’s rights, includingintellectual property rights, in connection with use of the information contained in this document.2.Products and product specifications may be subject to change without notice. Confirm that you havereceived the latest product standards or specifications before final design, purchase or use.3.Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,traffic, safety equipment or medical equipment for life support.4.Design your application so that the product is used within the ranges guaranteed by Hitachi particularlyfor maximum rating, operating supply voltage range, heat radiation characteristics, installationconditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeablefailure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.5.This product is not designed to be radiation resistant.6.No one is permitted to reproduce or duplicate, in any form, the whole or part of this document withoutwritten approval from Hitachi.7.Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductorproducts.Hitachi, Ltd.Semiconductor & Integrated Circuits.Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.Hitachi Asia Ltd.Hitachi Tower16 Collyer Quay #20-00,Singapore 049318Tel : <65>-538-6533/538-8577Fax : <65>-538-6933/538-3877URL : .sgURL NorthAmerica : /Europe : /hel/ecg Asia : Japan : http://www.hitachi.co.jp/Sicd/indx.htmHitachi Asia Ltd.(Taipei Branch Office)4/F, No. 167, Tun Hwa North Road,Hung-Kuo Building,Taipei (105), TaiwanTel : <886>-(2)-2718-3666Fax : <886>-(2)-2718-8180Telex : 23222 HAS-TPURL : Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon, Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : Hitachi Europe Ltd.Electronic Components Group.Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000Fax: <44> (1628) 585160Hitachi Europe GmbH Electronic Components Group Dornacher Stra βe 3D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0Fax: <49> (89) 9 29 30 00Hitachi Semiconductor (America) Inc.179 East Tasman Drive,San Jose,CA 95134 Tel: <1> (408) 433-1990Fax: <1>(408) 433-0223For further information write to:Colophon 2.0。
74HC574
20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP
CD54HC574, CD54HCT574 (CERDIP)
CD74HC574 (PDIP, SOIC) CD74HCT574 (PDIP, SOIC, TSSOP)
TOP VIEW
OE 1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CP
Functional Diagram
D0
D1
D2
D3
D4
D5
D6
D7
D CP Q
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
TRUTH TABLE
INPUTS
OUTPUT
OE
CP
Dn
Qn
74HCT574D中文资料
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver • ICC category: MSI
14 60
75
90 ns 2.0 Fig.6
5 12
15
18
4.5
4 10
13
15
6.0
tW
clock pulse width
80 14
HIGH or LOW
16 5
14 4
100
120
20
24
17
20
ns 2.0 Fig.6 4.5 6.0
tsu
set-up time
Dn to CP
60 6 12 2 10 2
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
74系列芯片功能大全
74系列芯片功能大全7400 TTL 2输入端四与非门7401 TTL 集电极开路2输入端四与非门7402 TTL 2输入端四或非门7403 TTL 集电极开路2输入端四与非门7404 TTL 六反相器7405 TTL 集电极开路六反相器7406 TTL 集电极开路六反相高压驱动器7407 TTL 集电极开路六正相高压驱动器7408 TTL 2输入端四与门7409 TTL 集电极开路2输入端四与门7410 TTL 3输入端3与非门74107 TTL 带清除主从双J-K触发器74109 TTL 带预置清除正触发双J-K触发器7411 TTL 3输入端3与门74112 TTL 带预置清除负触发双J-K触发器7412 TTL 开路输出3输入端三与非门74121 TTL 单稳态多谐振荡器74122 TTL 可再触发单稳态多谐振荡器74123 TTL 双可再触发单稳态多谐振荡器74125 TTL 三态输出高有效四总线缓冲门74126 TTL 三态输出低有效四总线缓冲门7413 TTL 4输入端双与非施密特触发器74132 TTL 2输入端四与非施密特触发器74133 TTL 13输入端与非门74136 TTL 四异或门74138 TTL 3-8线译码器/复工器74139 TTL 双2-4线译码器/复工器7414 TTL 六反相施密特触发器74145 TTL BCD—十进制译码/驱动器7415 TTL 开路输出3输入端三与门74150 TTL 16选1数据选择/多路开关74151 TTL 8选1数据选择器74153 TTL 双4选1数据选择器74154 TTL 4线—16线译码器74155 TTL 图腾柱输出译码器/分配器74156 TTL 开路输出译码器/分配器74157 TTL 同相输出四2选1数据选择器74158 TTL 反相输出四2选1数据选择器7416 TTL 开路输出六反相缓冲/驱动器74160 TTL 可预置BCD异步清除计数器74161 TTL 可予制四位二进制异步清除计数器74162 TTL 可预置BCD同步清除计数器74163 TTL 可予制四位二进制同步清除计数器74164 TTL 八位串行入/并行输出移位寄存器74165 TTL 八位并行入/串行输出移位寄存器74166 TTL 八位并入/串出移位寄存器74169 TTL 二进制四位加/减同步计数器7417 TTL 开路输出六同相缓冲/驱动器74170 TTL 开路输出4×4寄存器堆74173 TTL 三态输出四位D型寄存器74174 TTL 带公共时钟和复位六D触发器74175 TTL 带公共时钟和复位四D触发器74180 TTL 9位奇数/偶数发生器/校验器74181 TTL 算术逻辑单元/函数发生器74185 TTL 二进制—BCD代码转换器74190 TTL BCD同步加/减计数器74191 TTL 二进制同步可逆计数器74192 TTL 可预置BCD双时钟可逆计数器74193 TTL 可预置四位二进制双时钟可逆计数器74194 TTL 四位双向通用移位寄存器74195 TTL 四位并行通道移位寄存器74196 TTL 十进制/二-十进制可预置计数锁存器74197 TTL 二进制可预置锁存器/计数器7420 TTL 4输入端双与非门7421 TTL 4输入端双与门7422 TTL 开路输出4输入端双与非门74221 TTL 双/单稳态多谐振荡器74240 TTL 八反相三态缓冲器/线驱动器74241 TTL 八同相三态缓冲器/线驱动器74243 TTL 四同相三态总线收发器74244 TTL 八同相三态缓冲器/线驱动器74245 TTL 八同相三态总线收发器74247 TTL BCD—7段15V输出译码/驱动器74248 TTL BCD—7段译码/升压输出驱动器74249 TTL BCD—7段译码/开路输出驱动器74251 TTL 三态输出8选1数据选择器/复工器74253 TTL 三态输出双4选1数据选择器/复工器74256 TTL 双四位可寻址锁存器74257 TTL 三态原码四2选1数据选择器/复工器74258 TTL 三态反码四2选1数据选择器/复工器74259 TTL 八位可寻址锁存器/3-8线译码器7426 TTL 2输入端高压接口四与非门74260 TTL 5输入端双或非门74266 TTL 2输入端四异或非门7427 TTL 3输入端三或非门74273 TTL 带公共时钟复位八D触发器74279 TTL 四图腾柱输出S-R锁存器7428 TTL 2输入端四或非门缓冲器74283 TTL 4位二进制全加器74290 TTL 二/五分频十进制计数器74293 TTL 二/八分频四位二进制计数器74295 TTL 四位双向通用移位寄存器74298 TTL 四2输入多路带存贮开关74299 TTL 三态输出八位通用移位寄存器7430 TTL 8输入端与非门7432 TTL 2输入端四或门74322 TTL 带符号扩展端八位移位寄存器74323 TTL 三态输出八位双向移位/存贮寄存器7433 TTL 开路输出2输入端四或非缓冲器74347 TTL BCD—7段译码器/驱动器74352 TTL 双4选1数据选择器/复工器74353 TTL 三态输出双4选1数据选择器/复工器74365 TTL 门使能输入三态输出六同相线驱动器74365 TTL 门使能输入三态输出六同相线驱动器74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器74373 TTL 三态同相八D锁存器74374 TTL 三态反相八D锁存器74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D锁存器74378 TTL 单边输出公共使能六D锁存器74379 TTL 双边输出公共使能四D锁存器7438 TTL 开路输出2输入端四与非缓冲器74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器74390 TTL 双十进制计数器74393 TTL 双四位二进制计数器7440 TTL 4输入端双与非缓冲器7442 TTL BCD—十进制代码转换器74352 TTL 双4选1数据选择器/复工器74353 TTL 三态输出双4选1数据选择器/复工器74365 TTL 门使能输入三态输出六同相线驱动器74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器74373 TTL 三态同相八D锁存器74374 TTL 三态反相八D锁存器74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D锁存器74378 TTL 单边输出公共使能六D锁存器74379 TTL 双边输出公共使能四D锁存器7438 TTL 开路输出2输入端四与非缓冲器74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器74390 TTL 双十进制计数器74393 TTL 双四位二进制计数器7440 TTL 4输入端双与非缓冲器7442 TTL BCD—十进制代码转换器74447 TTL BCD—7段译码器/驱动器7445 TTL BCD—十进制代码转换/驱动器74450 TTL 16:1多路转接复用器多工器74451 TTL 双8:1多路转接复用器多工器74453 TTL 四4:1多路转接复用器多工器7446 TTL BCD—7段低有效译码/驱动器74460 TTL 十位比较器74461 TTL 八进制计数器74465 TTL 三态同相2与使能端八总线缓冲器74466 TTL 三态反相2与使能八总线缓冲器74467 TTL 三态同相2使能端八总线缓冲器74468 TTL 三态反相2使能端八总线缓冲器74469 TTL 八位双向计数器7447 TTL BCD—7段高有效译码/驱动器7448 TTL BCD—7段译码器/内部上拉输出驱动74490 TTL 双十进制计数器74491 TTL 十位计数器74498 TTL 八进制移位寄存器7450 TTL 2-3/2-2输入端双与或非门74502 TTL 八位逐次逼近寄存器74503 TTL 八位逐次逼近寄存器7451 TTL 2-3/2-2输入端双与或非门74533 TTL 三态反相八D锁存器74534 TTL 三态反相八D锁存器7454 TTL 四路输入与或非门74540 TTL 八位三态反相输出总线缓冲器7455 TTL 4输入端二路输入与或非门74563 TTL 八位三态反相输出触发器74564 TTL 八位三态反相输出D触发器74573 TTL 八位三态输出触发器74574 TTL 八位三态输出D触发器74645 TTL 三态输出八同相总线传送接收器74670 TTL 三态输出4×4寄存器堆7473 TTL 带清除负触发双J-K触发器7474 TTL 带置位复位正触发双D触发器7476 TTL 带预置清除双J-K触发器7483 TTL 四位二进制快速进位全加器7485 TTL 四位数字比较器7486 TTL 2输入端四异或门7490 TTL 可二/五分频十进制计数器7493 TTL 可二/八分频二进制计数器7495 TTL 四位并行输入\输出移位寄存器7497 TTL 6位同步二进制乘法器常用74系列标准数字电路的中文名称资料器件代号器件名称 74 74LS 74HC00 四2输入端与非门√√√01 四2输入端与非门(OC) √√02 四2输入端或非门√√√03 四2输入端与非门(OC) √√04 六反相器√√√05 六反相器(OC) √√06 六高压输出反相器(OC,30V) √√07 六高压输出缓冲,驱动器(OC,30V) √√√08 四2输入端与门√√√09 四2输入端与门(OC) √√√10 三3输入端与非门√√√11 三3输入端与门√√12 三3输入端与非门(OC) √√√13 双4输入端与非门√√√14 六反相器√√√15 三3输入端与门 (OC) √√16 六高压输出反相器(OC,15V) √17 六高压输出缓冲,驱动器(OC,15V) √20 双4输入端与非门√√√21 双4输入端与门√√√22 双4输入端与非门(OC) √√25 双4输入端或非门(有选通端) √√√26 四2输入端高压输出与非缓冲器√√√27 三3输入端或非门√√√28 四2输入端或非缓冲器√√√30 8输入端与非门√√√32 四2输入端或门√√√33 四2输入端或非缓冲器(OC) √√37 四2输入端与非缓冲器√√38 四2输入端与非缓冲器(OC) √√40 双4输入端与非缓冲器√√√42 4线-10线译码器(BCD输入) √√43 4线-10线译码器(余3码输入) √44 4线-10线译码器(余3葛莱码输入) √48 4线-7段译码器√49 4线-7段译码器√50 双2路2-2输入与或非门√√√51 2路3-3输入,2路2-2输入与或非门√√√52 4路2-3-2-2输入与或门√53 4路2-2-2-2输入与或非门√54 4路2-3-3-2输入与或非门√√55 2路4-4输入与或非门√60 双4输入与扩展器√√61 三3输入与扩展器√62 4路2-3-3-2输入与或扩展器√64 4路4-2-3-2输入与或非门√65 4路4-2-3-2输入与或非门(OC) √70 与门输入J-K触发器√71 与或门输入J-K触发器√72 与门输入J-K触发器√74 双上升沿D型触发器√√78 双D型触发器√√85 四位数值比较器√86 四2输入端异或门√√√87 4位二进制原码/反码√95 4位移位寄存器√101 与或门输入J-K触发器√102 与门输入J-K触发器√107 双主-从J-K触发器√108 双主-从J-K触发器√109 双主-从J-K触发器√110 与门输入J-K触发器√111 双主-从J-K触发器√√112 双下降沿J-K触发器√113 双下降沿J-K触发器√114 双下降沿J-K触发器√116 双4位锁存器√120 双脉冲同步驱动器√121 单稳态触发器√√√122 可重触发单稳态触发器√√√123 可重触发双稳态触发器√√√125 四总线缓冲器√√√126 四总线缓冲器√√√128 四2输入端或非线驱动器√√√132 四2输入端与非门√√√。
74ls574芯片中文使用手册说明书
特点： 逻辑图说明：LS574的八个触发器是边沿触发D 型触发器。
在时钟的正跳动，Q 输出将处于D 输入端已建立的逻辑状态。
时钟线上的施密特触发缓冲输入将简化系统设计，因为输入滞后作用使交流和直流抗扰度一般提高400mV 。
缓冲输出的控制输入将使八个输出处于正常状态（高电平或低电平）或处于高阻状态。
在高阻态下，输出既不能有效地给总线加负载，也不能有效地驱动总线。
输出控制不影响触发器的内部工作，既老数据可以保持，甚至当输出被关闭，新的数据也可以置入。
·三态总线驱动输出 ·置数全并行存取 ·缓冲控制输入·时钟输入有改善抗扰度的滞后作用 外引线排列图功能表输入输出控制 时钟 数据输出 CLK D Q L ↑ H H L ↑ L L L L × Q O H × × Z H=高电平 L=低电平 ×=不定 Z=高阻态↑=从低转换到高电平 Q O=建立稳态输入条件前Q 的电平推荐工作条件74Ⅱ 54 参数值 参数值 符号 参数名称 最小典型最大最小典型 最大 单位Vcc 电源电压 4.75 5 5.25 4.5 5 5.5 V V IH 输入高电平电压 2.0 2.0 V V IL 输入低电平电压 0.8 0.7 V I OH 输出高电平电流 -2.6 -1 mA I OL 输出低电平电流 24 12 mA 高 15 15 ns t W 时钟脉冲宽度低15 15 ns t su 数据建立时间 20↑ 20↑ ns t h 数据保持时间 0↑ 0↑ ns T A工作环境温度-4085-55125℃电 性 能：（除特别说明外，均为全温度范围）74Ⅱ54参数值参数值符号参数名称测试条件最小典型最大最小典型 最大 单位V IK 输入钳位电压Vcc=最小 I I =-18mA-1.5 -1.5 V V OH 输出高电平电压Vcc=最小 V IL =最大V IH =2V I OH =最大 2.4 2.4 3.4V V OL 输出低电平电压Vcc=最小 V IL =最大V IH =2V I OL =最大0.5 0.25 0.4VI I 输入电流 (最大输入电压时)Vcc=最大 V I =7V0.1 0.1 mA I IH 输入高电平电流 Vcc=最大 V I =2.7V 20 20 μAI IL 输入低电平电流 Vcc=最大 V I =0.4V-0.4 -0.4 mA I OZH 高关态输出电流Vcc=最大 V I =2.0VV o=2.7V20 20μAI OZL 低关态输出电流Vcc=最大 V I =2.0VV o=0.4V-20 -20 μA I OS 输出短路电流 Vcc =最大 V O =0V -30 -130-30 -130 mA I CC 电源电流 Vcc=最大 (注)402740 mA注：Icc 在输出控制端加4.5V 时测量。
SN74HCT645PWG4中文资料
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)SN74HCT645DW ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645DWE4ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645DWG4ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645DWR ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645DWRE4ACTIVE SOICDW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645DWRG4ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645N ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SN74HCT645N3OBSOLETE PDIP N 20TBD Call TI Call TISN74HCT645NE4ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SN74HCT645NSR ACTIVE SO NS 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645NSRE4ACTIVE SO NS 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PW ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWE4ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWG4ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWR ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWRE4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWRG4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWT ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWTE4ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT645PWTG4ACTIVETSSOPPW20250Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.24-May-2007Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annualbasis.24-May-2007TAPE AND REELINFORMATION19-May-2007DevicePackage Pins SiteReel Diameter (mm)Reel Width (mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74HCT645DWR DW 20MLA 3302410.813.0 2.71224Q1SN74HCT645NSR NS 20MLA 330248.213.0 2.51224Q1SN74HCT645PWRPW20MLA330166.957.11.6816Q1TAPE AND REEL BOX INFORMATIONDevice Package Pins Site Length (mm)Width (mm)Height (mm)SN74HCT645DWR DW 20MLA 333.2333.231.75SN74HCT645NSR NS 20MLA 333.2333.231.75SN74HCT645PWRPW20MLA342.9336.628.5819-May-200719-May-2007IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. 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SL74HCT574中文资料
ICC
Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current
5.5
4.0
40
160
µA
∆ICC
≥-55°C
25°C to 125°C 2.4
mA
5.5
2.9
SLS
System Logic Semiconductor
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.
X = don’t care Z = higogic Semiconductor
元器件交易网
SL74HCT574
MAXIMUM RATINGS *
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PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)SN74HCT574DBR ACTIVE SSOP DB 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574DBRE4ACTIVE SSOP DB 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574DW ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574DWR ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574DWRE4ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574N ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SN74HCT574N3OBSOLETE PDIP N 20TBD Call TI Call TISN74HCT574NE4ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type SN74HCT574NSR ACTIVE SO NS 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574NSRE4ACTIVE SO NS 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574PW ACTIVETSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574PWE4ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574PWLE OBSOLETE TSSOP PW 20TBDCall TI Call TISN74HCT574PWR ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574PWRE4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574PWT ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HCT574PWTE4ACTIVETSSOPPW20250Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)6-Dec-2006(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annualbasis.6-Dec-2006TAPE AND REELINFORMATION30-Apr-2007DevicePackage Pins SiteReel Diameter (mm)Reel Width (mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74HCT574DBR DB 20MLA 330168.27.5 2.51216Q1SN74HCT574DWR DW 20MLA 3302410.813.0 2.71224Q1SN74HCT574NSRNS 20MLA 330248.213.0 2.51224Q1SN74HCT574PWRPW20MLA330166.957.11.6816Q1TAPE AND REEL BOX INFORMATIONDevice Package Pins Site Length (mm)Width (mm)Height (mm)SN74HCT574DBR DB 20MLA 333.2333.228.58SN74HCT574DWR DW 20MLA 333.2333.231.75SN74HCT574NSR NS 20MLA 333.2333.231.75SN74HCT574PWRPW20MLA333.2333.228.5830-Apr-200730-Apr-2007IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements, improvements,and other changes to its products and services at any time and to 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