74LVTH162245
VISION AT697 EVB User's Manual
8 VISION AT697 EVB User's Manual
4.4 PLL, SKEW配置
CPU内部时钟,可以使用bypass或PLL SKEW可以调整, 线路如下:
缺省设定是全off
© 2009 上海创景计算机系统有限公司
4.5 其他
还有一些CPU的管脚培植如下:
CPU 配置
9
nBRDY一直是下拉的 如果使用PLL,并且PLL lock后, D5就会亮
EDAC配置
4.4
PLL, SKEW配置
4.5
其他
第5章 Power
第6章 Clock
第7章 Buffer
第8章 SDRAM
第9章 RS232
第10章 LED
第11章 Key
第12章 CPCI
第13章 DSU
第14章 扩展接口
第15章 CPLD
© 2009 上海创景计算机系统有限公司 Nhomakorabea目录
I
1 2 4 5 5 6 7 8 9 11 13 15 16 17 18 20 21 22 24 26
• 四个IO用于按键，可接到Interrupt
© 2009 上海创景计算机系统有限公司
功能介绍
3
• CPCI接口，CPCI 工作于33Mhz, 32Bits。支持Host, Satellite • 可外接CPU Clock, PCI Clock • 丰富的外接扩展接口，可通过CPCI P4, P5，也可通过SAMTEK QSH-QTH接
这SEL8_40Bits在CPLD中进行了译码:
//config 8 / 40 bits operation
always @(posedge clk)
74LVCH162245A(总线隔离,U20 U21 U22)
查询74LVC162245A供应商SSOP48:plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1TSSOP48:plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1NOTESDefinitionsShort-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.DisclaimersLife support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.Philips Semiconductors811 East Arques AvenueP.O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381© Copyright Philips Electronics North America Corporation 1998All rights reserved. Printed in U.S.A.print code Date of release: 05-96。
74LVT162245MTDX中文资料
© 2005 Fairchild Semiconductor Corporation DS012446January 1999Revised June 200574LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs74LVT162245 • 74LVTH162245Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port OutputsGeneral DescriptionThe LVT162245 and LVTH162245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state.The LVT162245 and LVTH162245 are designed with equivalent 25: series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers,clock drivers, and bus transceivers/transmitters.The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These non-inverting transceivers are designed for low volt-age (3.3V) V CC applications, but with the capability to pro-vide a TTL interface to a 5V environment. The LVT162245and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation simi-lar to 5V ABT while maintaining a low power dissipation.Featuress Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH162245),also available without bushold feature (74LVT162245).s Live insertion/extraction permitteds Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25: making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink r 12 mA.B Port outputs source/sink 32 mA/ 64 mA s Functionally compatible with the 74 series 162245s Latch-up performance exceeds 500 mA s ESD performance:Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000Vs Also packaged in plastic Fine Pitch Ball Grid Array (FBGA)Ordering Code:Note 1: Ordering code “G” indicates Trays.Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Order Number Package Number Package Description74LVT162245G (Note 1)(Note 2)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT162245MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT162245MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162245G (Note 1)(Note 2)BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE]74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL]74LVTH162245MTD MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE]74LVTH162245MTXMTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] 274L V T 162245 • 74L V T H 162245Logic SymbolConnection DiagramsPin Assignments for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH HIGH Voltage LevelL LOW Voltage Level X ImmaterialZ High ImpedancePin Names DescriptionOE n Output Enable Input (Active LOW)T/R n Transmit/Receive Input A 0–A 15Side A Inputs/3-STATE Outputs B 0–B 15Side B Inputs/3-STATE Outputs NCNo Connect123456A B 0NC T/R 1OE 1NC A 0B B 2B 1NC NC A 1A 2C B 4B 3V CC V CC A 3A 4D B 6B 5GND GND A 5A 6E B 8B 7GND GND A 7A 8F B 10B 9GND GND A 9A 10G B 12B 11V CC V CC A 11A 12H B 14B 13NC NC A 13A 14JB 15NCT/R 2OE 2NCA 15Inputs OutputsOE 1T/R 1L L Bus B 0–B 7 Data to Bus A 0–A 7L H Bus A 0–A 7 Data to Bus B 0–B 7HXHIGH-Z State on A 0–A 7, B 0–B 7Inputs OutputsOE 2T/R 2L L Bus B 8–B 15 Data to Bus A 8–A 15L H Bus A 8–A 15 Data to Bus B 8–B 15HXHIGH-Z State on A 8–A 15, B 8–B 1574LVT162245 • 74LVTH162245Functional DescriptionThe LVT162245 and LVTH162245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identi-cally, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.Logic DiagramsPlease note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474L V T 162245 • 74L V T H 162245Absolute Maximum Ratings (Note 3)Recommended Operating ConditionsNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: I O Absolute Maximum Rating must be observed.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 4.6V V I DC Input Voltage 0.5 to 7.0VV O Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to 7.0Output in HIGH or LOW State (Note 4)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA I O DC Output Current64V O ! V CC Output at HIGH State mA 128V O ! V CCOutput at LOW StateI CC DC Supply Current per Supply Pin r 64mA I GND DC Ground Current per Ground Pin r 128mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH-Level Output Current B Port 32mA A Port 12I OL LOW-Level Output Current B Port 64mAA Port12T AFree Air Operating Temperature40 85q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax V IK Input Clamp Diode Voltage 2.7 1.2V I I 18 mA V IH Input HIGH Voltage 2.7–3.6 2.0V V O d 0.1V or V IL Input LOW Voltage 2.7–3.60.8V V O t V CC 0.1V V OHOutput HIGH VoltageA Port 3.0 2.0V I OH 12 mA 2.7–3.6V CC 0.2V I OH 100 P A B Port2.7 2.4V I OH 8 mA3.0 2.0I OH 32 mA V OLOutput LOW VoltageA Port3.00.8V I OL 12 mA 2.70.2VI OL 100 P A B Port2.70.5VI OL 24 mA 3.00.4I OL 16 mA 3.00.5I OL 32 mA 3.00.55I OL 64 mA I I(HOLD)Bushold Input Minimum Drive3.075P A V I 0.8V (Note 5) 75V I 2.0V I I(OD)Bushold Input Over-Drive 3.0500P A (Note 6)(Note 5)Current to Change State 500(Note 7)I IInput Current3.610P AV I 5.5V Control Pins 3.6r 1V I 0V or V CC Data Pins3.6 5V I 0V 1V I V CCI OFFPower Off Leakage Current 0r 100P A 0V d V I or V O d 5.5V74LVT162245 • 74LVTH162245DC Electrical Characteristics (Continued)Note 5: Applies to Bushold versions only (74LVTH162245).Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.Dynamic Switching Characteristics (Note 9)Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.Symbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax I PU/PD Power Up/Down 0–1.5V r 100P A V O 0.5V to 3.0V 3-STATE CurrentV I GND to V CC I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.5V I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.0V (Note 5)I OZH 3-STATE Output Leakage Current 3.65P A V O 3.0V I OZH 3-STATE Output Leakage Current3.65P A V O 3.6V (Note 5)I OZH 3-STATE Output Leakage Current 3.610P A V CC V O d 5.5V I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ Power Supply Current3.60.19mA V CC d V O d 5.5V,Outputs Disabled 'I CCIncrease in Power Supply Current 3.60.2mAOne Input at V CC 0.6V (Note 8)Other Inputs at V CC or GNDSymbol ParameterV CC T A 25q C Units Conditions (V)MinTyp MaxC L 50 pF, R L 500:V OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 10)V OLVQuiet Output Minimum Dynamic V OL3.30.8V(Note 10) 674L V T 162245 • 74L V T H 162245AC Electrical CharacteristicsNote 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Capacitance (Note 12)Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.SymbolParameterT A 40q C to 85q CUnitsC L 50 pF, R L 500:V CC 3.3V r 0.3V V CC 2.7V MinMax MinMax t PLH Propagation Delay Data to A Port Output1.0 4.0 1.0 4.6ns t PHL 1.0 3.7 1.0 4.1t PLH Propagation Delay Data to B Port Output 1.0 3.5 1.0 3.9ns t PHL 1.0 3.5 1.0 3.9t PZH Output Enable Time for A Port Output 1.0 5.3 1.0 6.3ns t PZL 1.0 5.6 1.07.2t PZH Output Enable Time for B Port Output 1.0 4.6 1.0 5.4ns t PZL 1.0 5.3 1.0 6.9t PHZ Output Disable Time for A Port Output 1.5 5.6 1.5 6.3ns t PLZ 1.5 5.5 1.5 5.5t PHZ Output Disable Time for B Port Output 1.5 5.4 1.5 6.1ns t PLZ 1.55.1 1.55.4t OSHL A Port Output to Output Skew 1.0 1.0ns t OSLH (Note 11)t OSHL B Port Output to Output Skew 1.01.0ns t OSLH(Note 11)Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC 0V, V I 0V or V CC 4pF C I/OInput/Output CapacitanceV CC 3.0V, V O 0V or V CC8pF74LVT162245 • 74LVTH162245Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A 874L V T 162245 • 74L V T H 162245Physical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" WidePackage Number MS48A974LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
SNJ54LVTH162245WD中文资料
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)5962-9678001QXA ACTIVE CFP WD 481TBD Call TI Level-NC-NC-NC 5962-9678001VXA ACTIVE CFP WD 481TBDCall TI Level-NC-NC-NC 74LVTH162245DGGRG4ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74LVTH162245DLRG4ACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74LVTH162245GRDR ACTIVE LFBGA GRD 541000TBDSNPB Level-1-240C-UNLIM 74LVTH162245GRE4ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74LVTH162245ZQLR ACTIVE VFBGA ZQL 561000Green (RoHS &no Sb/Br)SNAGCU Level-1-260C-UNLIM 74LVTH162245ZRDR ACTIVE LFBGA ZRD 541000Green (RoHS &no Sb/Br)SNAGCU Level-1-260C-UNLIM SN74LVTH162245DGGR ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245DL ACTIVE SSOP DL 4825Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245DLG4ACTIVE SSOP DL 4825Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245DLR ACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245KR ACTIVE VFBGA GQL 561000TBD SNPB Level-1-240C-UNLIM SNJ54LVTH162245WDACTIVECFPWD481TBDCall TILevel-NC-NC-NC(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in anew design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM4-Oct-2005Addendum-Page 1元器件交易网元器件交易网元器件交易网IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. T o minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetworkMicrocontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。
逻辑器件74LVCH16245A与74LVC16245A的差异
逻辑器件74LVCH16245A与74LVC16245A的差异 前段时间公司⼀款⽣产了很久的产品出现⼀个很奇怪的问题，先放上等效图说明：1. INPUT左边是⼀个连接器，相当于直接到地的⼀个开关，所以这⾥⽤⼀个SW1替代2. 设备在上电后，SW1处于断开状态，所以INPUT为⾼，这时TO_MCU检测为⾼；当SW1按下时，NPUT为低，此时TO_MCU为低 遇到的问题是，SW1按下时，TO_MCU为低，再将SW1断开，INPUT为⾼，但是这时TO_MCU还是为低，这是个很奇怪的现象，后⾯发现是芯⽚信号⽤错了，本来是⽤74LVC16245A的，结果⽤成了74LVC H16245A，就是多了这个H结果就是不⼀样，后⾯将INPUT上拉电阻R1更换为4.7K后正常，那么这两个型号有什么差异呢，初⼀看都是⼀样的，只有些细微的差异。
如下截取⾃74LVCH16245A Datasheet从以上信息可知1. 输⼊脚在没有驱动的情况下，其输⼊端也会保持⼀个有效的逻辑状态，即要么是0，要么是1，总之是⼀个确定的逻辑状态。
2. 逻辑状态的转变，输⼊电流必须⼤于500uA，否则输⼊端会⼀直保持上⼀个逻辑状态。
再来分析为什么把R1从10K变为4.7K就可以了1. R1 = 10K时，I = 3.3 / 10K==>330uA2. R1 = 4.7K时，I =3.3 /4.7K==>702uA从上⾯两点来看，R1 = 10K时，⼩于500uA，所以输⼊的状态⼀直保持上⼀个逻辑电平；R1 = 4.7K时，才会进⾏状态转换，这时就可以跟74LVC16245A⼀样了，这就是多了⼀个H多出的内容，有点类似锁存的味道；在输⼊⽐较多的情况，需要留意其电流的消耗，因为每个输⼊脚都要提供⼤于500uA的电流，如果数量⼀多，就不得不好考虑其电流的消耗了，如如果16个PIN全部⽤上，都在同⼀时刻切换的话，这时候16*0.5mA=8mA。
74LVT2245D-T中文资料
19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7 mna817
19
G3
3 EN1 (BA)
1
3 EN2 (AB)
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mna818
Fig 2. IEC logic symbol
SOT339-1
plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74LVTH2245PW −40 °C to +85 °C TSSOP20
Description
Version
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
plastic shrink small outline package; 20 leads; body width 5.3 mm
The 74LVT2245; 74LVTH2245 is designed with 30 Ω series resistance in both the HIGH-state and LOW-state of the output. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers and transmitters.
LVTH162245总线驱动芯片
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)CLVTH162245IDGGREP ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CLVTH162245MDLREPACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/04709-01XE ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/04709-02YEACTIVESSOPDL481000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has takenand continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74LVTH162245-EP :•Catalog:SN74LVTH162245•Military:SN54LVTH162245NOTE:Qualified Version Definitions:•Catalog-TI's standard catalog product •Military -QML certified for Military and Defense ApplicationsPACKAGE OPTION ADDENDUM18-Sep-2008TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CLVTH162245IDGGREP TSSOP DGG 482000330.024.48.615.8 1.812.024.0Q1CLVTH162245MDLREPSSOPDL481000330.032.411.3516.23.116.032.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CLVTH162245IDGGREP TSSOP DGG482000346.0346.041.0 CLVTH162245MDLREP SSOP DL481000346.0346.049.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI 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notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. 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YL2440
YL2440优点(以下是其它开发板所没有的):1,双网卡(10M CS8900Q3, 100M DM9000都有) 2,高速IDE接口(配上LINUX,WCE驱动的)3,标准VGA接口4,CF卡接口5,CAN总线接口6,130万象素的摄像头接口7,IRDA红外线数据通讯口8,双系统,LINUX2.6和WinCE5.0注意: 本页仅出售YL2440开发板的光盘若需YL2440开发板,本店另有套件出售,详见:/, 那儿将附送YL2440开发板的光盘. 合作愉快. DVD光盘内的主要资料如下:.With.Platform.Builder ( PB5.0) Microsoft eMbedded Visual C++ 4.0Linux 2.6 全套开发包及源代码WinCE 5.0 全套开发包及源代码YL2440开以板原理图BIOS源码(ADS编译)裸板(无系统)测试程席源码.下面是驱动详细见绍:YL2440开发板简介YL2440 开发板采用SAMSUNG S3C2440A微处理器设计，核心板采用DIMM－200连接器与底板相连接，并且兼容我公司出品的YL2410核心板。
该板可流畅进行MP3编解码和 QVGA，可接130万像素摄像头。
尤适用于开发GPS导航,各种监控设备，网络应用产品等。
YL2440开发板硬件资源:中央处理器◆ CPU: 三星S3C2440A，主频400MHz；外部存储器◆内存：64M字节；◆ NOR Flash：2M字节（SST39VF1601）；◆ NAND Flash：64M字节（K9F1208，用户可自己更换为16M、32M或128M的NandFlash）串口◆两个五线异步串行口，波特率高达115200bps；◆一个九线异步串行口，采用ST16C550扩展出来的，波特率高达1.5Mbps；网络接口◆一个10M网口，采用CS8900Q3，带联接和传输指示灯；◆一个100M网口，采用DM9000，带联接和传输指示灯；USB接口◆一个USB1.1 HOST接口；◆一个USB1.1 Device接口；红外通讯口◆一个IRDA红外线数据通讯口；CAN总线接口◆一个CAN总线接口，全面支持CAN2.0A和CAN2.0B协议；音频接口◆采用IIS接口芯片UDA1341，一路立体声音频输出接口可接耳机或音箱；◆支持录音，板子自带驻机体话筒可直接录音，另有一路话筒输入接口可接麦克风；存储接口◆一个SD卡接口，可接1GB SD卡；◆一个CF卡接口（3.3V，接口信号均加了74LVTH162245驱动），工作在TrueIDE模式；◆一个IDE接口(接口信号均加了74LVTH162245驱动)，可直接挂接硬盘；LCD和触摸屏接口◆板上集成了4线电阻式触摸屏接口的相关电路；◆一个50芯LCD接口引出了LCD控制器的全部信号，并且这些信号引脚都加了74LVTH162245驱动，所以LCD输出更加稳定可靠；◆标准配置为256K色240x320/3.5英寸TFT液晶屏，带触摸屏◆支持黑白、4级灰度、16级灰度、256色、4096色STN液晶屏，尺寸从3.5寸到12.1寸，屏幕分辨率可达到1024×768象素；◆板上引出一个5V电源输出接口，可为大尺寸TFT液晶屏的5V CCFL背光模块供电；摄像头接口◆板上自带一个130万象素的摄像头，可直接摄像并在液晶屏上显示，并有一个2毫米间距双排插座用作摄像头扩展，用户可使用这个扩展口连接其他型号摄像头；VGA接口◆一个标准VGA接口，可直接连接各种VGA接口的CRT显示器或液晶显示器，带对比度微调电位器；时钟源◆内部实时时钟（带有后备锂电池）；复位电路◆一个复位按键，并采用专用复位芯片进行复位，稳定可靠；调试及下载接口◆一个20芯Multi－ICE标准JTAG接口，支持SDT2.51,ADS1.2等调试；电源接口◆ 5V电源供电，带电源开关和指示灯；其他◆八个小按键，四个高亮LED；◆一个蜂鸣器（带使能控制的短路块）；◆一个可调电阻接到ADC引脚上用来验证模数转换；◆一个50芯2毫米间距双排标准连接器用作扩展口，引出了地址线、数据线、读写、片选、中断、IO口、ADC、5V和3.3V电源、地等用户扩展可能用到的信号；；操作系统◆支持Linux2.6.12◆支持WinCE5.0用户光盘上提供的开发工具和源代码：1) ADS1.20安装程序(评估版)；2) 使用SUPERJTAG并支持ADS1.20的JTAG调试软件ARMJTAGDEBUGFINAL；3) 烧写FLASH的工具软件SJF2410（这个工具支持2410/2440，包含NT/2000/XP解决方案）；4) 串口工具软件sscom32.exe、dnw.exe、tftp.exe；5) 64K色（RGB565）图片字模软件；6) USB Device接口驱动程序；7) BIOS源代码（ADS1.20的项目文件）；8) 测试程序(ADS1.20的项目文件，包含全部源代码)，包括如下测试：RTC 实时时钟测试、按键测试（中断测试）、蜂鸣器测试、SD卡读写测试、音频录音放音测试、蜂鸣器测试（PWM测试）、ADC模数转换器测试、IIS音频播放 wav音乐测试、IIS音频录音测试、IrDA红外测试和、触摸屏测试、3.5寸夏普TFT液晶屏测试、CAN总线测试、VGA测试、摄像头测试等等；9) Linux for S3c2440内核源码包以及编译工具，含CS8900和DM9000的EHTNENET端口驱动，UART驱动USB HOST & DEVICE驱动；10) 核心板和底板电路原理图（OrCAD格式）11) 元件封装库和PCB尺寸结构图；12) 开发板使用手册（pdf格式）；13) 开发板上所用到的主要芯片手册、资料；14) ADS使用、DNW串口使用和超级终端配置的一些多媒体演示；4500元的 YL2440 套件包括:1) 一块已测试好的YL2440开发板（包括YL2440核心板与底板）2) 可选购配件LCD：CT35T CT64T CT80T CT104T (配有触摸笔)3) YL2440用户光盘4) 一个SUPER JTAG调试头（带20芯排线）, 可选购仿真器：ARMstep-P/ ARMstep-U/ ARM-tracerII5) 一条25P（公对母）并口线6) 一条9线交叉串口线7) 一条交叉网线8) 一条USB线9) 一条触摸笔10) 一个130万象素的摄像头11) 一个5V/2A直流电源12) 一个精美包装盒YL2440开发平台技术规格。
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3
74LVT162245 • 74LVTH162245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC VO ! VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
(Top Thru View)
2
74LVT162245 • 74LVTH162245
Functional Description
The LVT162245 and LVTH162245 contain sixteen noninverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Inputs OE2 L L H T/R2 L H X Outputs Bus B8–B15 Data to Bus A8–A15 Bus A8–A15 Data to Bus B8–B15 HIGH-Z State on A8–A15, B8–B15
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
FBGA Pin Assignments
1 A B C D E F G H J B0 B2 B4 B6 B8 B10 B12 B14 B15 2 NC B1 B3 B5 B7 B9 B11 B13 NC 3 T/R1 NC VCC GND GND GND VCC NC T/R2 4 OE1 NC VCC GND GND GND VCC NC OE2 5 NC A1 A3 A5 A7 A9 A11 A13 NC 6 A0 A2 A4 A6 A8 A10 A12 A14 A15
Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V
s Also packaged in plastic Fine Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT162245G (Note 1)(Note 2) 74LVT162245MEA (Note 2) 74LVT162245MTD (Note 2) 74LVTH162245G (Note 1)(Note 2) 74LVTH162245MEA 74LVTH162245MEX 74LVTH162245MTD 74LVTH162245MTX Package Number BGA54A (Preliminary) MS48A MTD48 BGA54A MS48A MS48A MTD48 MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
74LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen noninverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVT162245 and LVTH162245 are designed with equivalent 25: series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162245 and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162245), also available without bushold feature (74LVT162245). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25: making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink r12 mA. B Port outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 162245 s Latch-up performance exceeds 500 mA s ESD performance: