M74HC133B1R中文资料

DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP SOP TSSOP
M74HC133B1R M74HC133M1R
T&R
M74HC133RM13TR M74HC133TTR
All inputs are equipped with protection circuits against static discharge and transient excess voltage.
4.5
IO=-4.0 mA
6.0
IO=-5.2 mA
2.0
IO=20 µA
4.5
IO=20 µA
6.0
IO=20 µA
4.5
IO=4.0 mA
6.0
IO=5.2 mA
6.0 VI = VCC or GND
Value
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50Ω)
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WAVEFORM : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
1.5
1.5
1.5
3.15
3.15
3.15
V
4.2
4.2
4.2
0.5
0.5
0.5
1.35
1.35
1.35 V
1.8
1.8
1.8
1.9 2.0
1.9
1.9
4.4 4.5
4.4
4.4
5.9 6.0
5.9
5.9
V
4.18 4.31
4.13
4.10
5.68 5.8
5.63
5.60
0.0 0.1
0.1
0.1
0.0 0.1
0.1
0.1
0.0 0.1
0.1
0.1 V
0.17 0.26
0.33
0.40
0.18 0.26
0.33
0.40
± 0.1
±1
± 1 µA
6.0 VI = VCC or GND
1
10
20 µA
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M74HC133
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X : Don’t Care
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC Supply Voltage
-0.5 oltage
-0.5 to VCC + 0.5
s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 133
29
pF
1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
Min. Typ. Max. Min. Max. Min. Max.
30 75
95
110
8 15
19
22 ns
7 13
16
19
42 130
165
195
16 26
33
39 ns
14 22
28
33
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
3.3
MAX. 1.65
MIN. 0.020 0.030
20
7.1 5.1
1.27
inch TYP.
0.020 0.010 0.335 0.100 0.700
0.130
MAX. 0.065
0.787
0.280 0.201 0.050
P001C 6/9
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DIM.
A a1 a2 b b1 C c1 D E e e3 F G L M S
MIN. 0.1 0.35 0.19
9.8 5.8
3.8 4.6 0.5
SO-16 MECHANICAL DATA
mm. TYP
0.5
1.27 8.89
MAX. 1.75 0.2 1.65 0.46 0.25
MIN.
0.003
0.013 0.007
M74HC133
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元器件交易网
M74HC133
Plastic DIP-16 (0.25) MECHANICAL DATA
DIM.
a1 B b b1 D E e e3 F I L Z
MIN. 0.51 0.77
mm. TYP
0.5 0.25 8.5 2.54 17.78
DESCRIPTION
The M74HC133 is an high speed CMOS 13-INPUT NAND GATE fabricated with silicon gate C2MOS technology. The internal circuit is composed of 7 stages including buffer output, which enables high noise immunity and stable output.
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
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M74HC133
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top
tr, tf
元器件交易网
M74HC133
13 INPUT NAND GATE
s HIGH SPEED : tPD = 14 ns (TYP.) at VCC = 6V
s LOW POWER DISSIPATION: ICC =1µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.)
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
ICC or IGND DC VCC or Ground Current
SYMBOL
A to G, H to M
Y GND Vcc
NAME AND FUNCTION
Data Inputs Data Output Ground (0V) Positive Supply Voltage
TRUTH TABLE
A
B
C
D
E
F
G
H
I
J
K
L
M
Y
L
X
X
X
X
X
X
X
X
X
X
X
X
H
X
L
X
X
X
X
± 50
mA
PD
Power Dissipation
500(*)
mW
Tstg Storage Temperature
-65 to +150
°C
TL
Lead Temperature (10 sec)
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied