MIPI_DSI_Specification_v1b_8320061508
mipi之dsi协议 低速模式的时钟频率
mipi之dsi协议低速模式的时钟频率摘要：一、DSI协议简介二、MIPI DSI低速模式时钟频率的计算方法三、MIPI DSI低速模式时钟频率的应用场景四、如何优化低速模式时钟频率以提高显示性能五、总结正文：近年来，移动设备显示技术不断发展，MIPI DSI（Mobile Industry Processor Interface Display Serial Interface）协议作为智能手机、平板电脑等移动设备中显示屏与处理器之间的重要通信接口，得到了广泛应用。
本文将重点介绍MIPI DSI低速模式时钟频率的计算方法、应用场景以及如何优化低速模式时钟频率以提高显示性能。
一、DSI协议简介MIPI DSI协议是一种专为移动设备显示器设计的串行接口协议，它通过简单的双线串行接口实现显示屏与处理器之间的数据传输。
DSI协议具有传输速率高、功耗低、兼容性强等优点，成为移动设备显示领域的主流接口。
根据传输速率的不同，DSI协议可分为高速模式和低速模式。
二、MIPI DSI低速模式时钟频率的计算方法MIPI DSI低速模式时钟频率的计算公式为：时钟频率= 数据速率/ 8其中，数据速率单位为MB/s，时钟频率单位为Hz。
例如，当DSI接口传输速率为1.5 MB/s时，低速模式时钟频率为：时钟频率= 1.5 MB/s / 8 = 187.5 kHz三、MIPI DSI低速模式时钟频率的应用场景MIPI DSI低速模式时钟频率主要用于以下场景：1.显示屏分辨率较低，对传输速率要求不高的情况。
2.电池续航能力要求较高的移动设备，如智能手机、平板电脑等。
3.显示器驱动电路简化，降低成本和复杂度的需求。
四、如何优化低速模式时钟频率以提高显示性能1.选择合适的显示屏分辨率：根据设备性能和应用场景，合理选择显示屏分辨率，降低对传输速率的要求。
2.优化显示控制器：采用高性能的显示控制器，提高数据处理能力，从而提高低速模式下的显示性能。
MIPI-DSI-Essential(MIPI协议详细介绍)演示课件
MIPI DSI EssentialTable of Contents •MIPI DSI Overview•PHY Layer–D-PHY Architecture–Global Operation •Lane Management Layer •DSI Protocol LayerMIPI DSI Overview•Serial Interface– Low Pin Count– Reduced Power Consumption•2 Types of Data Signaling–High Speed Data Transmission - 500Mbps/Lane, differential signaling–Low Power Data Transmission - 10Mbps, single ended signaling, lane 0 only •Lane-Scalable, up to 4 data lanes •Packet Based Data Transmission–DSI Protocol has ECC, CRC capability - robust data transmission–Protocol Support Multiple displays (up to 4)MIPI DSI Interface Physical Architecture■ 1 Clock Lane, unidirectional■ 1 to 4 Data Lanes■ Lane0 is bidirectional for LP data output transmission of the driver ICMIPI DSI Functional LayersTransmitter Side8-bits8-bitsLow Level ProtocolDataControlData Control Add (TX) / Extract (RX) low levelprotocol, synchronization, ECC, CRC packet headers and footers.Low Level ProtocolDataControlData Control N * 8-bitsTX: Distribute data to 1, 2, 3 or 4 lanes RX: Assembly data from 1, 2, 3 or 4 to onebyte stream 8-bits8-bitsLane Management LayerLane Management LayerReceiver SidePHY Layer Data3ControlPHY LayerControlPixel to Byte Packing FormatsDataControlPixel Control Pack / Unpack Pixels or Commandsfrom / to Byte Stream Byte to Pixel Unpacking FormatsDataControlPixel Control ApplicationPixelControlApplicationPixelControlEncode and Interpretat Data /Commands16-, 18- or 24-bit PixelsData2Data1Data0N * 8-bitsData1Data3Data3Data0High Speed Unidirectional Clock Lane 0 -High Speed bidirectional Data Lane 1 -High Speed Unidirectional Data Lane 2 -High Speed Unidirectional Data Lane 3 -High Speed Unidirectional DataPhysical Transmission / ReceptionSerializer / DeserializerByte Clock Generation / Recovery (DDR)per MIPI D-PHY SpecVideo Mode DisplayDisplay DriverHost ProcessorDisplay PanelLCD DisplayBus InterfaceBus InterfaceColor Frame BufferDisplay RefreshTiming ControlUpdate Frame BufferHS Mode Operation in Practice - LPDT to HSDTLP01LP00LP11LP Transmitter DrivingHS Transmitter DrivingHS ClockR-term OnDPDNHS Mode Operation in Practice - SOTSOTDATA000011101ClkDataBus Turn Around•Handover Bus Possession–Host to client, client to host–When host request data from client and whenhost read status of client–Client must send BTA after client's datatransmission–TE-signaling•Sequence (ex, Read Request to Client)–Host Send "Read Request" to Client -> Host sends BTA -> Client Get Bus -> Host Releases Bus ->Client sends data -> Client sends BTA -> HostGet BusBus Turn Aroundin PracticeBTAClient LPDTHost DrivingClient DrivingDPDNLane Management LayerMulti Lane Distributionand MergingDistributor Merger Function(receive)DSI Protocol LayerPacket-basedProtocol•Data Flow–Image data, Signal events, Commands ->Protocol Layer -> Packets ->Physical layer -> Packet Receive -> Interpret Packet to Image data,Signal Event, Commands–Signal Event : V-sync, H-sync.–Commands : DCS Commands•Many packets can be transferred in a transmissionECC Generation- DI - Data 0- Data 1ECCCRC Calculation- DataCRCECC Generation- DI- Word CountECCEndian Policy •Long Packet Case–LS Byte First, MS Byte LastVirtual Channel•Up to 4 peripherals possible with tagged command or blocks of data, using the Virtual Channel ID Field–DSI hub is needed, Not possible to connect many display to same bus DSI HubHost ProcessorMain Display Panel LCDDisplayBus InterfaceBusInterfaceDSIOut 1Out 2InterfaceLCD DisplayFrame BufferSub- DisplayMultiple Packets perTransmission- With EoTp- Without EoTpOnly Video ModeVideo Mode Command ModeMotorola Legacy operation for videomodeProtocol SpecificOnly Video ModeVideo Mode Command Mode Protocol SpecificPackets for DCScommands•DCS Short Write : write a single data byte to a peripheral–05h / 15h (no parameters /one parameter)–If BTA follows ACK by display or AwER•DCS Long Write / write_LUT Command, Data Type = 11 1001 (39h)–Used to send larger blocks of data to a displaymodule–DI byte, a two-byte WC, an ECC byte, followedby the DCS Command Byte, a payload of lengthPackets for DSIProtocol•Set Maximum Return Packet Size, Data Type = 11 0111 (37h)–This prevents FIFO overflow for Read packetpayload in processor, considering the case that–Memory read command can retrieve a numerous bytes of data.•Null Packet (Long), Data Type = 00 1001 (09h)– This prevents the data lane(s) going back to LP-11, with less overhead to continue HS burst.Packets forVideomode•Sync Event : generate video sync signal internally–V Sync Start(0x01), V Sync End(0x11)–H Sync Start(0x21), H Sync End(0x31)•Video Streams (Long)–RGB Video StreamsRGB Pixel Stream -16bit, 24bit24-Bit PixelData Type : 0x3E Word Count:1H Line Pixel Length x 316-Bit PixelData Type : 0x0E Word Count:1H Line Pixel Length x 2Video Streaming - Non Burst OperationVideo Streaming - BurstOperationReverseTransmissions•Occur on D0 after host has made BTA•Display is expected to reply data or at least reply ACK–ACK means everything's ok•Response Type–Tearing Effect (TEE)–Acknowledge = ACK–Acknowledge and Error Report = AwERReverse Response Data TypeLPDT Reverse Example11100001=LPDT Data type 05 =short write noparams 00010001= 0x11=SLPOUTECCBTADisplay EMEdphy table 8 : ACK =00100001 (0x84)BTA back to hostError Detect and Reporting■Error Bit MappingQnACommand ModeDisplayHost ProcessorDisplay PanelLCD DisplayBus InterfaceColor Frame BufferImage Update DataCommands & Image UpdateDataBus InterfaceDisplay ControllerPHY Layer D-PHY ArchitecturePHY Lane Configuration•Minimum Configuration–At least 1 Clock Lane, 1 Data Lane •Reverse-direction traffic uses lane 0 only–Lane 1, 2, 3 (if present)are unidirectional •Lane number fixed at design / manufacture(Module level)–No dynamic lane configuration by hostprocessor.•Transmission data Unit–One byte•Lane Module may contain–HS-TX, HS-RX, or both•If LP mode is used at command mode configuration , both host and peripheral must include LP Rx and LP Tx–Also CD needed if bi-directional in use•The LP-CD shall check for contention at least once before driving a new state on the line•Master and a Slave conceptLow power transmitter High speed receiverLow power receiverContention (=“collision”) detectionHigh speed transmitterLeast PHY Lane Configuration -Detailed ViewData lane 0CLK lane* Bi-directional but not HS reverse * LP for bi-directional* uni-directional * LP for minimum transition controlD-PHY Signal Level•2 Types of Signal Level–HSDT–LPDT LP VOH - typ 1.2V, 1.1V ~ 1.3VHS diff - typ 200mv, 140mv ~ 270mvHS comm - typ 200mv, 150mv ~ 250mvLP VOH - typ 0V, -50mV ~ 50mVLP VIL : 550mVLP VIH -typ 1.2v 0.88V ~ 1.35VHS Mode- Transmitter Receiver Structure •HS Data Transmission–While HSDT is active, Termination R is enabledR-term(ZID) : 100OhmTransmitter side Receiver sidePCB, Conn, FPCB 0V400mV 300mV100mVHS Mode - Signaling Detailed View300mv 100mv 200mv100mv200mvV diff = |V OD|■Vdiff 200mV, Vcm 200mV Typ ConditionHS Mode - Clock Transmission•HS Clock–DDR Clock Structure, 1 Clk Period : 2*UI–Clock Burst always contains an even number oftransition–Clock can also run while D0 is in LP mode(especially Videomode)•Ex) 500Mbps–Freq : 250Mhz, 1Clk Period : 4ns, IU = 2ns,HS Mode - Clockto Data•Data to Clock Timing Definition–90 Degree Phase Shift CLK to Data–The First bit of DSI Packet must be sent at arising edge of HS ClkData LaneClock LaneHSDT Signal inPracticeVo+ : typically ~300mVVCM = 200mV nomVo- : typically ~100mVVdiff(positive)LP Signaling Detailed View •Typically 1.2V•T LPX - min : 50nsLPDT Signal in Practice2T LPXtypically 1.2V DPDNPHY Layer Global OperationData Unit Of D-PHY•Minimum Data Unit is 1 Byte–Transmitter - Byte stream -> Bit stream–Receiver - Bit stream -> Byte stream•HS Lane can be differential 1 or 0•LP Lane on D0 can have four state(LP +/-)–LP00 : "Bridge", "Space"–LP01 : "HS-Rqst", "Mark-0"–LP10 : "LP-Rqst", "Mart-1"。
mipi之dsi协议 低速模式的时钟频率
mipi之dsi协议低速模式的时钟频率
摘要：
1.引言
2.MIPI DSI协议简介
3.MIPI DSI协议的低速模式
4.低速模式的时钟频率
5.结论
正文：
MIPI DSI（Display Serial Interface）协议是一种显示器接口标准，用于连接移动设备中的处理器和显示器。
它支持多种数据传输模式，包括低速模式。
本文将详细介绍MIPI DSI协议的低速模式的时钟频率。
MIPI DSI协议支持多种数据传输速率，包括高速模式（High-Speed Mode，HS）、中速模式（Medium-Speed Mode，MS）和低速模式（Low-Speed Mode，LS）。
低速模式主要用于低带宽要求的应用场景，如液晶显示器（LCD）驱动等。
在低速模式下，数据传输速率较低，但能满足大多数显示应用的需求。
在MIPI DSI协议的低速模式下，时钟频率是一个关键参数。
时钟频率决定了数据传输速率和显示器更新频率。
根据MIPI DSI协议标准，低速模式的时钟频率范围为10 MHz至65 MHz。
实际应用中，时钟频率的选择取决于显示器分辨率和刷新率等性能要求。
一般来说，较高的时钟频率可以实现更高的分辨率和刷新率，但也会消耗更多的电能。
因此，设计者需要根据具体应用场景权
衡时钟频率与其他性能指标。
总之，MIPI DSI协议的低速模式在显示应用中具有广泛的应用。
时钟频率的选择需根据具体应用场景进行权衡，以实现最佳的性能与功耗平衡。
MIPI及DSI协议介绍
MIPI及DSI协议介绍郑明桑sam0030@MIPI是什么v M obile I ndustry P rocessor I nterface 移动通信行业处理器接口v MIPI包括：DCS 显示命令接口DBI 显示总线接口DPI 显示像素接口DSI 显示串行接口CSI 显示摄像接口MIPI优点v高速率最多四个通道，每个通道最大传输1 Gbpsv低功耗LowPower 1.2 V HighSpeed 200mVv低成本：PIN脚更少，PCB占用空间更少v抗干扰（EMI，ESD）高速传输信号200mV，差分信号与其他差分信号对比v TMDS：最小化差分信号传输v LVDS：低压差分信号D-PHY层定义D-PHY介绍v通道（lane）v1个单向clock通道v1到4个data通道v传输模式v Low Power模式：用于控制，最大10Mbps此时Data0的D+，D-是两个独立的信号线v High Speed模式：数据传输，80Mbps—1Gbpsv数据格式LSB first，MSB lastv传输方向只有Data0且在LP模式下，才能反向传输，其他都是单向的Lane State&Line Levelv Lane State:v LP Mode：LP-00, LP-01, LP-10, LP-11(DpDn)v HS Mode：HS-0,HS-1(差分信号)Lane Modulev LP-CD: LowPower ContentionDetector(LP争用探测器) v LP-RX/TX HS-RX/TXOperating Modev Operating Mode:v每个模式都必须从Stop State(LP-11)开始v Escape mode request (LP-11→LP-10→LP-00→LP-01→LP-00)，Exit（LP-10→LP-11）v High-Speed mode request (LP-11→LP-01→LP-00)，Exit(EOT →LP-11)v Control Mode (Turnaround BTA)request (LP-11→LP-10→LP-00→LP-10→LP-00)，Exit(LP-00→LP-10→LP-11)v Mode切换图Escape Modev Escape模式是在LP状态下的特殊模式，只有进入该模式，下面这些功能才能实现：LPDT：Low Power Data TransmissionULPS：Ultra-Low Power StateTrigger（比如Remote trigger, Ack trigger and TE trigger）v一旦进入Escape模式，后面必须跟8-bit的entry命令才能实现对应ActionEscape Modev以LPDT为例，发送LCD sleep out 0x11命令，注意LSB firstEscape Modev ULPS:这种状态下，line处于Space状态，退出这种状态需要Mark-1状态唤醒High-Speed Modev HS模式所有通道同时开始，但每个通道可能不同时结束，clock必须也在hs模式，并且是双边沿触发，也就是data 速率是clock的两倍v完整的hs序列如下图,退出EOT+LP11High-Speed Mode v下面是HS下发送0x29 display on时序图BTA Modev It is different between DSI and other interface, other IF use Read signal to let slave send read response.But DSI integrate all control signal in DSI Data/Clock lane.v So DSI need a procedure enables information transfer in the opposite direction of the current direction.v用于读取外色参数（如ID）或确认发送包外设是否接收正确BTA Modev Acknowledge is a Trigger Message (00100001) sent when all preceding transmissions since the last peripheral to hostcommunication is received by the peripheral with no errors.DSI接口v DSI(Display Serial Interface)v DSI 收发接口，如下图：DSI传输模式v Command Mode类似MPU接口，需要IC 内如GRAM。
mipi dsi 吞吐量计算 分辨率
mipi dsi 吞吐量计算分辨率MIPI DSI（Mobile Industry Processor Interface - Display Serial Interface）是一种用于移动设备显示屏的串行接口标准。
其吞吐量（Throughput）计算涉及到多个因素，包括分辨率、帧率、颜色深度等。
下面我们将详细讨论如何根据分辨率计算MIPI DSI的吞吐量。
首先，我们需要了解MIPI DSI的基本数据传输单位——像素。
每个像素由多个颜色分量组成，通常是红色、绿色和蓝色（RGB）。
每个颜色分量的位数（即颜色深度）决定了显示图像的质量和颜色范围。
例如，常见的颜色深度有16位（每个颜色分量5位）、18位（每个颜色分量6位）和24位（每个颜色分量8位）等。
分辨率指的是显示屏的像素数量，通常以水平像素数和垂直像素数表示，例如1920x1080、2560x1440等。
要计算MIPI DSI的吞吐量，我们需要知道每秒钟需要传输的像素总数。
这可以通过将水平像素数与垂直像素数相乘，再乘以帧率（即每秒显示的图像数）来得到。
例如，对于一个1920x1080的显示屏，如果帧率为60Hz，那么每秒钟需要传输的像素总数为1920x1080x60 = 124416000个像素。
如果每个像素使用24位颜色深度，那么每秒钟需要传输的数据量（以位为单位）为124416000x24 = 2985984000位，即约2.986Gbps。
这就是根据分辨率计算MIPI DSI吞吐量的基本方法。
需要注意的是，实际吞吐量还可能受到其他因素的影响，如显示屏的刷新率、数据压缩等。
因此，在实际应用中，可能需要对计算结果进行一定的调整和优化。
MIPI_DSI_Specification_v1b_8320061508
MIPI Alliance Standard for Display Serial InterfaceV1.0MIPI Board approved 5 April 2006* Caution to Implementers *This document is a MIPI Specification formally approved by the MIPI Alliance Board of Directors per the process defined in the MIPI Alliance Bylaws. However, the Display Working Group has identified certain technical issues in this approved version of the specification that are pending further review and which may require revisions of or corrections to this document in the near future. Such revisions, if any, will be handled via the formal specification revision process as defined in the Bylaws.A Release Notes document has been prepared by the Display Working Group and is available to all members. The intent of the Release Notes is to provide a list of known technical issues under further discussion with the working group. This may not be an exhaustive list; its purpose is to simply catalog known issues as of this release date. Implementers of this specification should be aware of these facts, and take them into consideration as they work with the specification.Release Notes for the Display Serial Interface Specification can be found at the following direct, permanent link:https:///members/file.asp?id=4844MIPI Alliance Standard for Display Serial InterfaceVersion 1.00a – 19 April 2006MIPI Board Approved 5-Apr-2006Further technical changes to DSI are expected as work continues in the Display Working GroupNOTICE OF DISCLAIMER12The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled 3by any of the authors or developers of this material or MIPI. The material contained herein is provided on 4an “AS IS” basis and to the maximum extent permitted by applicable law, this material is provided AS IS 5AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all 6other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if7any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of8accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of 9negligence.10ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET11POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD 12TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY13AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR 14MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE15GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, 16CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER17CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR18ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH1920DAMAGES.21Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the2223contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;24and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance 25with the contents of this Document. The use or implementation of the contents of this Document may26involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,27patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any2829IPR or claims of IPR as respects the contents of this Document or otherwise.30Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 31MIPI Alliance, Inc.32c/o IEEE-ISTO33445 Hoes Lane34Piscataway, NJ 0885435Attn: Board SecretaryContents3637Version 1.00 – 13 April 2006 (i)381Overview (8)391.1Scope (8)401.2Purpose (8)412Terminology (Informational) (9)422.1Definitions (9)432.2Abbreviations (10)442.3Acronyms (10)453References (Informational) (13)463.1DBI and DBI-2 (Display Bus Interface Standards for Parallel Signaling) (13)473.2DPI and DPI-2 (Display Pixel Interface Standards for Parallel Signaling) (13)3.3DCS (Display Command Set) (14)48493.4CSI-2 (Camera Serial Interface 2) (14)503.5D-PHY (MIPI Alliance Standard for Physical Layer) (14)514DSI Introduction (15)524.1DSI Layer Definitions (16)534.2Command and Video Modes (17)4.2.1Command Mode (17)54554.2.2Video Mode Operation (17)564.2.3Virtual Channel Capability (18)5DSI Physical Layer (19)57585.1Data Flow Control (19)595.2Bidirectionality and Low Power Signaling Policy (19)605.3Command Mode Interfaces (20)615.4Video Mode Interfaces (20)625.5Bidirectional Control Mechanism (20)5.6.1Clock Requirements (21)64655.6.2Clock Power and Timing (22)666Multi-Lane Distribution and Merging (23)676.1Multi-Lane Interoperability and Lane-number Mismatch (24)686.1.1Clock Considerations with Multi-Lane (25)696.1.2Bi-directionality and Multi-Lane Capability (25)706.1.3SoT and EoT in Multi-Lane Configurations (25)717Low-Level Protocol Errors and Contention (28)727.1Low-Level Protocol Errors (28)737.1.1SoT Error (28)747.1.2SoT Sync Error (29)757.1.3EoT Sync Error (29)7.1.4Escape Mode Entry Command Error (30)76777.1.5LP Transmission Sync Error (30)787.1.6False Control Error (31)797.2Contention Detection and Recovery (31)807.2.1Contention Detection in LP Mode (32)817.2.2Contention Recovery Using Timers (32)7.3Additional Timers (34)82837.3.1Turnaround Acknowledge Timeout (TA_TO) (34)847.3.2Peripheral Reset Timeout (PR_TO) (35)7.4Acknowledge and Error Reporting Mechanism (35)85868DSI Protocol (37)878.1Multiple Packets per Transmission (37)888.2Packet Composition (37)898.3Endian Policy (38)908.4General Packet Structure (38)8.4.2Short Packet Format (40)92938.5Common Packet Elements (40)948.5.1Data Identifier Byte (40)958.5.2Error Correction Code (41)968.6Interleaved Data Streams (41)978.6.1Interleaved Data Streams and Bi-directionality (42)988.7Processor to Peripheral Direction (Processor-Sourced) Packet Data Types (42)998.8Processor-to-Peripheral Transactions – Detailed Format Description (43)1008.8.1Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h) (43)1018.8.2Color Mode On Command, Data Type = 00 0010 (02h) (44)1028.8.3Color Mode Off Command, Data Type = 01 0010 (12h) (44)1038.8.4Shutdown Peripheral Command, Data Type = 10 0010 (22h) (44)8.8.5Turn On Peripheral Command, Data Type = 11 0010 (32h) (44)1041058.8.6Generic Short WRITE Packet, 0 to 7 Parameters, Data Type = xx x011 (x3h and xBh) (44)1068.8.7Generic READ Request, 0 to 7 Parameters, Data Type = xx x100 (x4h and xCh) (44)1078.8.8DCS Commands (45)1088.8.9Set Maximum Return Packet Size, Data Type = 11 0111 (37h) (46)1098.8.10Null Packet (Long), Data Type = 00 1001 (09h) (46)8.8.11Blanking Packet (Long), Data Type = 01 1001 (19h) (46)1101118.8.12Generic Non-Image Data (Long), Data Type = 10 1001 (29h) (47)1128.8.13Packed Pixel Stream, 16-bit Format, Long packet, Data Type 00 1110 (0Eh) (47)8.8.14Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh) (48)1131148.8.15Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 10 1110 (2Eh) (49)1158.8.16Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh) (50)1168.8.17DO NOT USE and Reserved Data Types (50)1178.9Peripheral-to-Processor (Reverse Direction) LP Transmissions (51)1188.9.1Packet Structure for Peripheral-to-Processor LP Transmissions (51)1198.9.2System Requirements for ECC and Checksum and Packet Format (51)1208.9.3Appropriate Responses to Commands and ACK Requests (52)1218.9.4Format of Acknowledge with Error Report and Read Response Data Types (53)1228.9.5Error-Reporting Format (53)8.10Peripheral-to-Processor Transactions – Detailed Format Description (54)1231248.10.1Acknowledge with Error Report, Data Type 00 0010 (02h) (55)1258.10.2Generic Short Read Response with Optional ECC, Data Type 01 0xxx (10h – 17h) (55)8.10.3Generic Long Read Response with Optional ECC and Checksum, Data Type = 01 1010 126127(1Ah) 551288.10.4DCS Long Read Response with Optional ECC and Checksum, Data Type 01 1100 (1Ch)..56 1298.10.5DCS Short Read Response with Optional ECC, Data Type 10 0xxx (20h – 27h) (56)1308.10.6Multiple-packet Transmission and Error Reporting (56)1318.10.7Clearing Error Bits (56)1328.11Video Mode Interface Timing (56)1338.11.1Traffic Sequences (57)1348.11.2Non-Burst Mode with Sync Pulses (58)1358.11.3Non-Burst Mode with Sync Events (58)1368.11.4Burst Mode (59)1378.11.5Parameters (60)1388.12TE Signaling in DSI (61)1399Error-Correcting Code (ECC) and Checksum (63)1409.1Hamming Code for Packet Header Error Detection/Correction (63)1419.2Hamming-modified Code for DSI (63)9.3ECC Generation on the Transmitter and Byte-Padding (67)1421439.4Applying ECC and Byte-Padding on the Receiver (67)9.5Checksum Generation for Long Packet Payloads (68)14414510Compliance, Interoperability, and Optional Capabilities (70)14610.1Display Resolutions (70)14710.2Pixel Formats (71)14810.3Number of Lanes (71)14910.4Maximum Lane Frequency (71)15010.5Bidirectional Communication (71)15110.6ECC and Checksum Capabilities (72)15210.7Display Architecture (72)15310.8Multiple Peripheral Support (72)154Annex A (Informative) Contention Detection and Recovery Mechanisms (73)A.1PHY Detected Contention (73)155156A.1.1Protocol Response to PHY Detected Faults (73)MIPI Alliance Standard for Display Serial Interface 1571 Overview158The Display Serial Interface (DSI) specification defines protocols between a host processor and peripheral 159160devices that adhere to MIPI Alliance specifications for mobile device interfaces. The DSI specification 161builds on existing standards by adopting pixel formats and command set defined in MIPI Alliance 162standards for DBI-2 [2], DPI-2 [3], and DCS [1].1.1 Scope163Interface protocols as well as a description of signal timing relationships are within the scope of this 164165specification.166Electrical specifications and physical specifications are out of scope for this document. In addition, legacy interfaces such as DPI-2 and DBI-2 are also out of scope for this specification. Furthermore, device usage 167168of auxiliary buses such as I2C or SPI, while not precluded by this specification, are also not within its 169scope.1.2 Purpose170171The Display Serial Interface specification defines a standard high-speed serial interface between a 172peripheral, such as an active-matrix display module, and a host processor in a mobile device. By 173standardizing this interface, components may be developed that provide higher performance, lower power, 174less EMI and fewer pins than current devices, while maintaining compatibility across products from 175multiple vendors.2 Terminology (Informational)176177The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the 178words “shall”, “should”, “may”, and “can” in the development of documentation, as follows:179The word shall is used to indicate mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to).180181The use of the word must is deprecated and shall not be used when stating mandatory requirements; must is 182used only to describe unavoidable situations.183The use of the word will is deprecated and shall not be used when stating mandatory requirements; will is 184only used in statements of fact.185The word should is used to indicate that among several possibilities one is recommended as particularly 186suitable, without mentioning or excluding others; or that a certain course of action is preferred but not 187necessarily required; or that (in the negative form) a certain course of action is deprecated but not 188prohibited (should equals is recommended that).189The word may is used to indicate a course of action permissible within the limits of the standard (may 190equals is permitted).191The word can is used for statements of possibility and capability, whether material, physical, or causal (can 192equals is able to).193All sections are normative, unless they are explicitly indicated to be informative.2.1 Definitions194195Forward Direction: The signal direction is defined relative to the direction of the high-speed serial clock. 196Transmission from the side sending the clock to the side receiving the clock is the forward direction.197Half duplex: Bidirectional data transmission over a Lane allowing both transmission and reception but 198only in one direction at a time.199HS Transmission: Sending one or more packets in the forward direction in HS Mode. A HS Transmission 200is delimited before and after packet transmission by LP-11 states.201Host Processor: Hardware and software that provides the core functionality of a mobile device.Lane: Consists of two complementary Lane Modules communicating via two-line, point-to-point Lane 202203Interconnects. A Lane is used for either Data or Clock signal transmission.204Lane Interconnect: Two-line point-to-point interconnect used for both differential high-speed signaling 205and low-power single ended signaling.206Lane Module: Module at each side of the Lane for driving and/or receiving signals on the Lane.207Link: A complete connection between two devices containing one Clock Lane and at least one Data Lane. 208LP Transmission: Sending one or more packets in either direction in LP Mode or Escape Mode. A LP 209Transmission is delimited before and after packet transmission by LP-11 states.Packet: A group of two or more bytes organized in a specified way to transfer data across the interface. All 210211packets have a minimum specified set of components. The byte is the fundamental unit of data from which 212packets are made.213Payload: Application data only – with all Link synchronization, header, ECC and checksum and other 214protocol-related information removed. This is the “core” of transmissions between host processor and 215peripheral.216PHY: The set of Lane Modules on one side of a Link.217PHY Configuration: A set of Lanes that represent a possible Link. A PHY configuration consists of a 218minimum of two Lanes: one Clock Lane and one or more Data Lanes.219Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for 220Forward Direction.221Transmission: Refers to either HS or LP Transmission. See the HS Transmission and LP Transmission 222definitions for descriptions of the different transmission modes.223Virtual Channel: Multiple independent data streams for up to four peripherals are supported by this 224specification. The data stream for each peripheral is a Virtual Channel. These data streams may be 225interleaved and sent as sequential packets, with each packet dedicated to a particular peripheral or channel. 226Packet protocol includes information that directs each packet to its intended peripheral.227Word Count: Number of bytes.2.2 Abbreviations228229e.g. Forexample2.3 Acronyms230231AM Active matrix (display technology)232ProtocolAIP ApplicationIndependent233ASP Application Specific Protocol234BLLP Blanking or Low Power intervalPixel235perBPP Bits236Turn-AroundBTA Bus237InterfaceCSI CameraSerial238DBI Display Bus InterfaceDI Data239Identifier240DMA Direct Memory Access241DPI Display Pixel InterfaceDSIDisplay Serial Interface242 DT Data Type243 ECC Error-Correcting Code 244 EMI Electro Magnetic interference 245 EoTEnd of Transmission246 ESD Electrostatic Discharge 247 FpsFrames per second248 HS High Speed 249 ISTOIndustry Standards and Technology Organization250 LLP Low-Level Protocol 251 LP Low Power 252 LPI Low Power Interval 253 LPS Low Power State (state of serial data line when not transferring high-speed serial data) 254 LSBLeast Significant Bit255 Mbps Megabits per second256 MIPI Mobile Industry Processor Interface 257 MSBMost Significant Bit258 PE Packet End 259 PF Packet Footer 260 PH Packet Header 261 PHY Physical Layer 262 PI Packet Identifier 263 PPI PHY-Protocol Interface 264 PS Packet Start 265 PT Packet Type 266 PWB Printed Wired Board267 QCIFQuarter-size CIF (resolution 176x144 pixels or 144x176 pixels)268 QVGA Quarter-size Video Graphics Array (resolution 320x240 pixels or 240x320 pixels)269RAM Random Access Memory270271RGB Color presentation (Red, Green, Blue)272SLVS Scalable Low Voltage Signaling273SoT Start of Transmission274SVGA Super Video Graphics Array (resolution 800x600 pixels or 600x800 pixels) 275VGA Video Graphics Array (resolution 640x480 pixels or 480x640 pixels)VSA Vertical276ActiveSync277WVGA Wide VGA (resolution 800x480 pixels or 480x800 pixels)278CountWC Word3 References (Informational)279280[1] MIPI Alliance Standard for Display Command Set, version 1.00, April 2006281[2] MIPI Alliance Standard for Display Bus Interface, version 2.00, November 2005[3] MIPI Alliance Standard for Display Parallel Interface, version 2.00, September 2005282283[4] MIPI Alliance Standard for D-PHY, version 0.65, November 2005284Design and Analysis of Fault Tolerant Digital System by Barry W. Johnson285Error Correcting Codes: Hamming Distance by Don Johnson paper286Intel 8206 error detection and correction unit datasheet287National DP8400-2 Expandable Error Checker/Corrector datasheetMuch of DSI is based on existing MIPI Alliance standards as well as several MIPI Alliance standards in 288289simultaneous development. In the Application Layer, DSI duplicates pixel formats used in MIPI Alliance 290Standard for Display Parallel Interface [3] when it is in Video Mode operation. For display modules with a 291display controller and frame buffer, DSI shares a common command set with MIPI Alliance Standard for 292Display Bus Interface [2]. The command set is documented in MIPI Alliance Standard for Display 293Command Set [1].3.1 DBI and DBI-2 (Display Bus Interface Standards for Parallel Signaling)294295DBI and DBI-2 are MIPI Alliance specifications for parallel interfaces to display modules having display 296controllers and frame buffers. For systems based on these specifications, the host processor loads images to 297the on-panel frame buffer through the display processor. Once loaded, the display controller manages all 298display refresh functions on the display module without further intervention from the host processor. Image 299updates require the host processor to write new data into the frame buffer.300DBI and DBI-2 specify a parallel interface; that is, data is sent to the peripheral over an 8-, 9- or 16-bit-301wide parallel data bus, with additional control signals.302The DSI specification supports a Command Mode of operation. Like the parallel DBI, a DSI-compliant 303interface sends commands and parameters to the display. However, all information in DSI is first serialized 304before transmission to the display module. At the display, serial information is transformed back to parallel 305data and control signals for the on-panel display controller. Similarly, the display module can return status 306information and requested memory data to the host processor, using the same serial data path.3.2 DPI and DPI-2 (Display Pixel Interface Standards for Parallel Signaling)307DPI and DPI-2 are MIPI Alliance specifications for parallel interfaces to display modules without on-panel 308309display controller or frame buffer. These display modules rely on a steady flow of pixel data from host 310processor to the display, to maintain an image without flicker or other visual artifacts. MIPI Alliance 311specifications document several pixel formats for Active Matrix (AM) display modules.312Like DBI and DBI-2, DPI and DPI-2 are specifications for parallel interfaces. The data path may be 16-, 31318-, or 24-bits wide, depending on pixel format(s) supported by the display module. This specification 314refers to DPI mode of operation as Video Mode.Some display modules that use Video Mode in normal operation also make use of a simplified form of 315316Command Mode, when in low-power state. These display modules can shut down the streaming video 317interface and continue to refresh the screen from a small local frame buffer, at reduced resolution and pixel318depth. The local frame buffer shall be loaded, prior to interface shutdown, with image content to be319displayed when in low-power operation. These display modules can switch mode in response to power-320control commands.3.3 DCS (Display Command Set)321322DCS is a specification for the command set used by DSI and DBI-2 specifications. Commands are sent 323from the host processor to the display module. On the display module, a display controller receives andinterprets commands, then takes appropriate action. Commands fall into four broad categories: read 324325register, write register, read memory and write memory. A command may be accompanied by multiple 326parameters.3.4 CSI-2 (Camera Serial Interface 2)327CSI-2 is a MIPI Alliance standard for serial interface between a camera module and host processor. It is 328329based on the same physical layer technology and low-level protocols as DSI. Some significant differencesare:330331•CSI-2 uses unidirectional high-speed Link, whereas DSI is half-duplex bidirectional Link332•CSI-2 makes use of a secondary channel, based on I2C, for control and status functions333CSI-2 data direction is from peripheral (Camera Module) to host processor, while DSI’s primary data334direction is from host processor to peripheral (Display Module).3.5 D-PHY (MIPI Alliance Standard for Physical Layer)335MIPI Alliance Standard for D-PHY [4] provides the physical layer definition for DSI. The functionality 336337specified by the D-PHY standard covers all electrical and timing aspects, as well as low-level protocols, 338signaling, and message transmissions in various operating modes.4 DSI Introduction339340DSI specifies the interface between a host processor and a peripheral such as a display module. It builds on 341existing MIPI Alliance standards by adopting pixel formats and command set specified in DPI-2, DBI-2 342and DCS standards.343Figure 1 shows a simplified DSI interface. From a conceptual viewpoint, a DSI-compliant interface 344performs the same functions as interfaces based on DBI-2 and DPI-2 standards or similar parallel display 345interfaces. It sends pixels or commands to the peripheral, and can read back status or pixel information 346from the peripheral. The main difference is that DSI serializes all pixel data, commands, and events that, in 347traditional or legacy interfaces, are normally conveyed to and from the peripheral on a parallel data bus 348with additional control signals.349From a system or software point of view, the serialization and deserialization operations should be 350transparent. The most visible, and unavoidable, consequence of transformation to serial data and back to 351parallel is increased latency for transactions that require a response from the peripheral. For example, 352reading a pixel from the frame buffer on a display module will have a higher latency using DSI than DBI. 353Another fundamental difference is the host processor’s inability during a read transaction to throttle the 354rate, or size, of returned data.355356Figure 1 DSI Transmitter and Receiver Interface4.1 DSI Layer Definitions357Application Processor Peripheral358Figure 2 DSI Layers359360A conceptual view of DSI organizes the interface into several functional layers. A description of the layers 361follows and is also shown in Figure 2.362PHY Layer: The PHY Layer specifies transmission medium (electrical conductors), the input/output 363circuitry and the clocking mechanism that captures “ones” and “zeroes” from the serial bit stream. This part 364of the specification documents the characteristics of the transmission medium, electrical parameters for 365signaling and the timing relationship between clock and Data Lanes.366The mechanism for signaling Start of Transmission (SoT) and End of Transmission (EoT) is specified, as 367well as other “out of band” information that can be conveyed between transmitting and receiving PHYs. 368Bit-level and byte-level synchronization mechanisms are included as part of the PHY. Note that the 369electrical basis for DSI (SLVS) has two distinct modes of operation, each with its own set of electrical 370parameters.371The PHY layer is described in MIPI Alliance Standard for D-PHY [4].372Lane Management Layer: DSI is Lane-scalable for increased performance. The number of data signals 373may be 1, 2, 3, or 4 depending on the bandwidth requirements of the application. The transmitter side of the 374interface distributes the outgoing data stream to one or more Lanes (“distributor” function). On the receiving end, the interface collects bytes from the Lanes and merges them together into a recombined data 375376stream that restores the original stream sequence (“merger” function).Protocol Layer: At the lowest level, DSI protocol specifies the sequence and value of bits and bytes 377378traversing the interface. It specifies how bytes are organized into defined groups called packets. The 379protocol defines required headers for each packet, and how header information is generated and interpreted.The transmitting side of the interface appends header and error-checking information to data being 380381transmitted. On the receiving side, the header is stripped off and interpreted by corresponding logic in the 382receiver. Error-checking information may be used to test the integrity of incoming data. DSI protocol also383documents how packets may be tagged for interleaving multiple command or data streams to separate384destinations using a single DSI.385Application Layer: This layer describes higher-level encoding and interpretation of data contained in the386data stream. Depending on the display subsystem architecture, it may consist of pixels having a prescribed387format, or of commands that are interpreted by the display controller inside a display module. The DSI 388specification describes the mapping of pixel values, commands and command parameters to bytes in the389packet assembly. See MIPI Alliance Standard for Display Command Set [1].4.2 Command and Video Modes390391DSI-compliant peripherals support either of two basic modes of operation: Command Mode and Video392Mode. Which mode is used depends on the architecture and capabilities of the peripheral. The mode393definitions reflect the primary intended use of DSI for display interconnect, but are not intended to restrict 394DSI from operating in other applications.Typically, a peripheral is capable of Command Mode operation or Video Mode operation. Some Video 395396Mode displays also include a simplified form of Command Mode operation in which the display may 397refresh its screen from a reduced-size, or partial, frame buffer, and the interface (DSI) to the host processor398may be shut down to reduce power consumption.Mode3994.2.1 Command400Command Mode refers to operation in which transactions primarily take the form of sending commands401and data to a peripheral, such as a display module, that incorporates a display controller. The display 402controller may include local registers and a frame buffer. Systems using Command Mode write to, and readfrom, the registers and frame buffer memory. The host processor indirectly controls activity at the 403404peripheral by sending commands, parameters and data to the display controller. The host processor can also 405read display module status information or the contents of the frame memory. Command Mode operationrequires a bidirectional interface.406407Operation4.2.2 VideoMode408Video Mode refers to operation in which transfers from the host processor to the peripheral take the form of409a real-time pixel stream. In normal operation, the display module relies on the host processor to provide410image data at sufficient bandwidth to avoid flicker or other visible artifacts in the displayed image. Video 411information should only be transmitted using High Speed Mode.412Some Video Mode architectures may include a simple timing controller and partial frame buffer, used to413maintain a partial-screen or lower-resolution image in standby or low-power mode. This permits the 414interface to be shut down to reduce power consumption.415To reduce complexity and cost, systems that only operate in Video Mode may use a unidirectional data416path.。
mipi dsi burst 莫得波形详解
mipi dsi burst 莫得波形详解【原创实用版】目录1.MIPI DSI 简介2.MIPI DSI Burst 的特点3.莫得波形的概念和作用4.莫得波形详解5.结论正文1.MIPI DSI 简介MIPI（Mobile Industry Processor Interface）是一种用于移动设备处理器接口的标准，旨在提供一种通用、高效的硬件和软件接口，以实现移动设备处理器与其他硬件组件（如显示器、摄像头等）之间的通信。
MIPI DSI（Display Subsystem Interface）是 MIPI 标准下的一个子集，专门用于显示器子系统的接口。
2.MIPI DSI Burst 的特点MIPI DSI Burst 是 MIPI DSI 的一种传输模式，具有以下特点：- 高数据传输速率：MIPI DSI Burst 支持多种数据传输速率，最高可达 3Gbps，可以满足高分辨率、高帧率的显示需求。
- 动态带宽分配：MIPI DSI Burst 支持动态带宽分配，可以根据显示内容的实际需求自动调整带宽，降低功耗。
- 错误检测与纠正：MIPI DSI Burst 具有错误检测与纠正机制，可以确保数据传输的稳定性和可靠性。
3.莫得波形的概念和作用莫得波形（Moire Pattern）是一种特殊的波形，广泛应用于显示技术中，尤其在 MIPI DSI Burst 中扮演重要角色。
莫得波形的主要作用是检测显示器的像素排列和屏幕分辨率。
4.莫得波形详解莫得波形的生成原理是利用人眼对光的敏感性以及视觉暂留效应，通过特定的图案和时间间隔产生视觉上的运动错觉。
在 MIPI DSI Burst 中，莫得波形主要用于以下几个方面：- 检测屏幕分辨率：莫得波形中的特定图案可以帮助检测屏幕的分辨率，确保显示内容的清晰度和准确性。
- 检测像素排列：莫得波形中的特定图案可以检测屏幕像素的排列方式，如 RGB、RGGB 等，以便正确处理显示数据。
mipi-dsi 三种 video mode 理解
mipi-dsi 三种video mode 理解MIPI DSI（Mobile Industry Processor Interface Display Serial Interface）是一种用于移动设备和其他嵌入式系统中的显示设备的串行接口标准。
在MIPI DSI 中，有三种视频模式，它们分别是Command Mode、Video Mode Type A 和Video Mode Type B。
以下是对这三种模式的简要理解：mand Mode：•Command Mode 是MIPI DSI 的基本模式，用于传输控制命令和配置信息。
在Command Mode 中，数据被发送为控制命令，用于设置显示器的各种参数，例如亮度、颜色模式等。
•Command Mode 主要用于初始化和配置显示设备，以及在显示设备切换到Video Mode 之前的控制操作。
2.Video Mode Type A：•Video Mode Type A 是MIPI DSI 的一种视频传输模式。
在这种模式下，图像数据以像素流的形式传输，像素的颜色和数据以特定的格式组织。
数据的传输速率相对较高，适用于高分辨率的图像和视频传输。
•Video Mode Type A 支持RGB 格式和YCbCr 格式的像素数据传输。
3.Video Mode Type B：•Video Mode Type B 也是MIPI DSI 的视频传输模式之一，与Video Mode Type A 类似。
在这种模式下，像素数据以流的形式传输，但数据的组织和格式可能略有不同。
它也支持高分辨率图像和视频传输。
•Video Mode Type B 与Video Mode Type A 的主要区别在于数据的编码和排列方式。
总体而言，Command Mode 用于传输控制命令和配置信息，而Video Mode 用于传输图像和视频数据。
Video Mode 有两种类型，Type A 和Type B，它们在像素数据的编码和排列方式上略有不同，但都支持高效的视频传输。
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MIPI Alliance Standard for Display Serial InterfaceV1.0MIPI Board approved 5 April 2006* Caution to Implementers *This document is a MIPI Specification formally approved by the MIPI Alliance Board of Directors per the process defined in the MIPI Alliance Bylaws. However, the Display Working Group has identified certain technical issues in this approved version of the specification that are pending further review and which may require revisions of or corrections to this document in the near future. Such revisions, if any, will be handled via the formal specification revision process as defined in the Bylaws.A Release Notes document has been prepared by the Display Working Group and is available to all members. The intent of the Release Notes is to provide a list of known technical issues under further discussion with the working group. This may not be an exhaustive list; its purpose is to simply catalog known issues as of this release date. Implementers of this specification should be aware of these facts, and take them into consideration as they work with the specification.Release Notes for the Display Serial Interface Specification can be found at the following direct, permanent link:https:///members/file.asp?id=4844MIPI Alliance Standard for Display Serial InterfaceVersion 1.00a – 19 April 2006MIPI Board Approved 5-Apr-2006Further technical changes to DSI are expected as work continues in the Display Working GroupNOTICE OF DISCLAIMER12The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled 3by any of the authors or developers of this material or MIPI. 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IN NO EVENT WILL ANY13AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR 14MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE15GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, 16CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER17CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR18ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH1920DAMAGES.21Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the2223contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document;24and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance 25with the contents of this Document. The use or implementation of the contents of this Document may26involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents,27patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any2829IPR or claims of IPR as respects the contents of this Document or otherwise.30Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 31MIPI Alliance, Inc.32c/o IEEE-ISTO33445 Hoes Lane34Piscataway, NJ 0885435Attn: Board SecretaryContents3637Version 1.00 – 13 April 2006 (i)381Overview (8)391.1Scope (8)401.2Purpose (8)412Terminology (Informational) (9)422.1Definitions (9)432.2Abbreviations (10)442.3Acronyms (10)453References (Informational) (13)463.1DBI and DBI-2 (Display Bus Interface Standards for Parallel Signaling) (13)473.2DPI and DPI-2 (Display Pixel Interface Standards for Parallel Signaling) (13)3.3DCS (Display Command Set) (14)48493.4CSI-2 (Camera Serial Interface 2) (14)503.5D-PHY (MIPI Alliance Standard for Physical Layer) (14)514DSI Introduction (15)524.1DSI Layer Definitions (16)534.2Command and Video Modes (17)4.2.1Command Mode (17)54554.2.2Video Mode Operation (17)564.2.3Virtual Channel Capability (18)5DSI Physical Layer (19)57585.1Data Flow Control (19)595.2Bidirectionality and Low Power Signaling Policy (19)605.3Command Mode Interfaces (20)615.4Video Mode Interfaces (20)625.5Bidirectional Control Mechanism (20)5.6.1Clock Requirements (21)64655.6.2Clock Power and Timing (22)666Multi-Lane Distribution and Merging (23)676.1Multi-Lane Interoperability and Lane-number Mismatch (24)686.1.1Clock Considerations with Multi-Lane (25)696.1.2Bi-directionality and Multi-Lane Capability (25)706.1.3SoT and EoT in Multi-Lane Configurations (25)717Low-Level Protocol Errors and Contention (28)727.1Low-Level Protocol Errors (28)737.1.1SoT Error (28)747.1.2SoT Sync Error (29)757.1.3EoT Sync Error (29)7.1.4Escape Mode Entry Command Error (30)76777.1.5LP Transmission Sync Error (30)787.1.6False Control Error (31)797.2Contention Detection and Recovery (31)807.2.1Contention Detection in LP Mode (32)817.2.2Contention Recovery Using Timers (32)7.3Additional Timers (34)82837.3.1Turnaround Acknowledge Timeout (TA_TO) (34)847.3.2Peripheral Reset Timeout (PR_TO) (35)7.4Acknowledge and Error Reporting Mechanism (35)85868DSI Protocol (37)878.1Multiple Packets per Transmission (37)888.2Packet Composition (37)898.3Endian Policy (38)908.4General Packet Structure (38)8.4.2Short Packet Format (40)92938.5Common Packet Elements (40)948.5.1Data Identifier Byte (40)958.5.2Error Correction Code (41)968.6Interleaved Data Streams (41)978.6.1Interleaved Data Streams and Bi-directionality (42)988.7Processor to Peripheral Direction (Processor-Sourced) Packet Data Types (42)998.8Processor-to-Peripheral Transactions – Detailed Format Description (43)1008.8.1Sync Event (H Start, H End, V Start, V End), Data Type = xx 0001 (x1h) (43)1018.8.2Color Mode On Command, Data Type = 00 0010 (02h) (44)1028.8.3Color Mode Off Command, Data Type = 01 0010 (12h) (44)1038.8.4Shutdown Peripheral Command, Data Type = 10 0010 (22h) (44)8.8.5Turn On Peripheral Command, Data Type = 11 0010 (32h) (44)1041058.8.6Generic Short WRITE Packet, 0 to 7 Parameters, Data Type = xx x011 (x3h and xBh) (44)1068.8.7Generic READ Request, 0 to 7 Parameters, Data Type = xx x100 (x4h and xCh) (44)1078.8.8DCS Commands (45)1088.8.9Set Maximum Return Packet Size, Data Type = 11 0111 (37h) (46)1098.8.10Null Packet (Long), Data Type = 00 1001 (09h) (46)8.8.11Blanking Packet (Long), Data Type = 01 1001 (19h) (46)1101118.8.12Generic Non-Image Data (Long), Data Type = 10 1001 (29h) (47)1128.8.13Packed Pixel Stream, 16-bit Format, Long packet, Data Type 00 1110 (0Eh) (47)8.8.14Packed Pixel Stream, 18-bit Format, Long packet, Data type = 01 1110 (1Eh) (48)1131148.8.15Pixel Stream, 18-bit Format in Three Bytes, Long packet, Data Type = 10 1110 (2Eh) (49)1158.8.16Packed Pixel Stream, 24-bit Format, Long packet, Data Type = 11 1110 (3Eh) (50)1168.8.17DO NOT USE and Reserved Data Types (50)1178.9Peripheral-to-Processor (Reverse Direction) LP Transmissions (51)1188.9.1Packet Structure for Peripheral-to-Processor LP Transmissions (51)1198.9.2System Requirements for ECC and Checksum and Packet Format (51)1208.9.3Appropriate Responses to Commands and ACK Requests (52)1218.9.4Format of Acknowledge with Error Report and Read Response Data Types (53)1228.9.5Error-Reporting Format (53)8.10Peripheral-to-Processor Transactions – Detailed Format Description (54)1231248.10.1Acknowledge with Error Report, Data Type 00 0010 (02h) (55)1258.10.2Generic Short Read Response with Optional ECC, Data Type 01 0xxx (10h – 17h) (55)8.10.3Generic Long Read Response with Optional ECC and Checksum, Data Type = 01 1010 126127(1Ah) 551288.10.4DCS Long Read Response with Optional ECC and Checksum, Data Type 01 1100 (1Ch)..56 1298.10.5DCS Short Read Response with Optional ECC, Data Type 10 0xxx (20h – 27h) (56)1308.10.6Multiple-packet Transmission and Error Reporting (56)1318.10.7Clearing Error Bits (56)1328.11Video Mode Interface Timing (56)1338.11.1Traffic Sequences (57)1348.11.2Non-Burst Mode with Sync Pulses (58)1358.11.3Non-Burst Mode with Sync Events (58)1368.11.4Burst Mode (59)1378.11.5Parameters (60)1388.12TE Signaling in DSI (61)1399Error-Correcting Code (ECC) and Checksum (63)1409.1Hamming Code for Packet Header Error Detection/Correction (63)1419.2Hamming-modified Code for DSI (63)9.3ECC Generation on the Transmitter and Byte-Padding (67)1421439.4Applying ECC and Byte-Padding on the Receiver (67)9.5Checksum Generation for Long Packet Payloads (68)14414510Compliance, Interoperability, and Optional Capabilities (70)14610.1Display Resolutions (70)14710.2Pixel Formats (71)14810.3Number of Lanes (71)14910.4Maximum Lane Frequency (71)15010.5Bidirectional Communication (71)15110.6ECC and Checksum Capabilities (72)15210.7Display Architecture (72)15310.8Multiple Peripheral Support (72)154Annex A (Informative) Contention Detection and Recovery Mechanisms (73)A.1PHY Detected Contention (73)155156A.1.1Protocol Response to PHY Detected Faults (73)MIPI Alliance Standard for Display Serial Interface 1571 Overview158The Display Serial Interface (DSI) specification defines protocols between a host processor and peripheral 159160devices that adhere to MIPI Alliance specifications for mobile device interfaces. The DSI specification 161builds on existing standards by adopting pixel formats and command set defined in MIPI Alliance 162standards for DBI-2 [2], DPI-2 [3], and DCS [1].1.1 Scope163Interface protocols as well as a description of signal timing relationships are within the scope of this 164165specification.166Electrical specifications and physical specifications are out of scope for this document. In addition, legacy interfaces such as DPI-2 and DBI-2 are also out of scope for this specification. Furthermore, device usage 167168of auxiliary buses such as I2C or SPI, while not precluded by this specification, are also not within its 169scope.1.2 Purpose170171The Display Serial Interface specification defines a standard high-speed serial interface between a 172peripheral, such as an active-matrix display module, and a host processor in a mobile device. By 173standardizing this interface, components may be developed that provide higher performance, lower power, 174less EMI and fewer pins than current devices, while maintaining compatibility across products from 175multiple vendors.2 Terminology (Informational)176177The MIPI Alliance has adopted Section 13.1 of the IEEE Standards Style Manual, which dictates use of the 178words “shall”, “should”, “may”, and “can” in the development of documentation, as follows:179The word shall is used to indicate mandatory requirements strictly to be followed in order to conform to the standard and from which no deviation is permitted (shall equals is required to).180181The use of the word must is deprecated and shall not be used when stating mandatory requirements; must is 182used only to describe unavoidable situations.183The use of the word will is deprecated and shall not be used when stating mandatory requirements; will is 184only used in statements of fact.185The word should is used to indicate that among several possibilities one is recommended as particularly 186suitable, without mentioning or excluding others; or that a certain course of action is preferred but not 187necessarily required; or that (in the negative form) a certain course of action is deprecated but not 188prohibited (should equals is recommended that).189The word may is used to indicate a course of action permissible within the limits of the standard (may 190equals is permitted).191The word can is used for statements of possibility and capability, whether material, physical, or causal (can 192equals is able to).193All sections are normative, unless they are explicitly indicated to be informative.2.1 Definitions194195Forward Direction: The signal direction is defined relative to the direction of the high-speed serial clock. 196Transmission from the side sending the clock to the side receiving the clock is the forward direction.197Half duplex: Bidirectional data transmission over a Lane allowing both transmission and reception but 198only in one direction at a time.199HS Transmission: Sending one or more packets in the forward direction in HS Mode. A HS Transmission 200is delimited before and after packet transmission by LP-11 states.201Host Processor: Hardware and software that provides the core functionality of a mobile device.Lane: Consists of two complementary Lane Modules communicating via two-line, point-to-point Lane 202203Interconnects. A Lane is used for either Data or Clock signal transmission.204Lane Interconnect: Two-line point-to-point interconnect used for both differential high-speed signaling 205and low-power single ended signaling.206Lane Module: Module at each side of the Lane for driving and/or receiving signals on the Lane.207Link: A complete connection between two devices containing one Clock Lane and at least one Data Lane. 208LP Transmission: Sending one or more packets in either direction in LP Mode or Escape Mode. A LP 209Transmission is delimited before and after packet transmission by LP-11 states.Packet: A group of two or more bytes organized in a specified way to transfer data across the interface. All 210211packets have a minimum specified set of components. The byte is the fundamental unit of data from which 212packets are made.213Payload: Application data only – with all Link synchronization, header, ECC and checksum and other 214protocol-related information removed. This is the “core” of transmissions between host processor and 215peripheral.216PHY: The set of Lane Modules on one side of a Link.217PHY Configuration: A set of Lanes that represent a possible Link. A PHY configuration consists of a 218minimum of two Lanes: one Clock Lane and one or more Data Lanes.219Reverse Direction: Reverse direction is the opposite of the forward direction. See the description for 220Forward Direction.221Transmission: Refers to either HS or LP Transmission. See the HS Transmission and LP Transmission 222definitions for descriptions of the different transmission modes.223Virtual Channel: Multiple independent data streams for up to four peripherals are supported by this 224specification. The data stream for each peripheral is a Virtual Channel. These data streams may be 225interleaved and sent as sequential packets, with each packet dedicated to a particular peripheral or channel. 226Packet protocol includes information that directs each packet to its intended peripheral.227Word Count: Number of bytes.2.2 Abbreviations228229e.g. Forexample2.3 Acronyms230231AM Active matrix (display technology)232ProtocolAIP ApplicationIndependent233ASP Application Specific Protocol234BLLP Blanking or Low Power intervalPixel235perBPP Bits236Turn-AroundBTA Bus237InterfaceCSI CameraSerial238DBI Display Bus InterfaceDI Data239Identifier240DMA Direct Memory Access241DPI Display Pixel InterfaceDSIDisplay Serial Interface242 DT Data Type243 ECC Error-Correcting Code 244 EMI Electro Magnetic interference 245 EoTEnd of Transmission246 ESD Electrostatic Discharge 247 FpsFrames per second248 HS High Speed 249 ISTOIndustry Standards and Technology Organization250 LLP Low-Level Protocol 251 LP Low Power 252 LPI Low Power Interval 253 LPS Low Power State (state of serial data line when not transferring high-speed serial data) 254 LSBLeast Significant Bit255 Mbps Megabits per second256 MIPI Mobile Industry Processor Interface 257 MSBMost Significant Bit258 PE Packet End 259 PF Packet Footer 260 PH Packet Header 261 PHY Physical Layer 262 PI Packet Identifier 263 PPI PHY-Protocol Interface 264 PS Packet Start 265 PT Packet Type 266 PWB Printed Wired Board267 QCIFQuarter-size CIF (resolution 176x144 pixels or 144x176 pixels)268 QVGA Quarter-size Video Graphics Array (resolution 320x240 pixels or 240x320 pixels)269RAM Random Access Memory270271RGB Color presentation (Red, Green, Blue)272SLVS Scalable Low Voltage Signaling273SoT Start of Transmission274SVGA Super Video Graphics Array (resolution 800x600 pixels or 600x800 pixels) 275VGA Video Graphics Array (resolution 640x480 pixels or 480x640 pixels)VSA Vertical276ActiveSync277WVGA Wide VGA (resolution 800x480 pixels or 480x800 pixels)278CountWC Word3 References (Informational)279280[1] MIPI Alliance Standard for Display Command Set, version 1.00, April 2006281[2] MIPI Alliance Standard for Display Bus Interface, version 2.00, November 2005[3] MIPI Alliance Standard for Display Parallel Interface, version 2.00, September 2005282283[4] MIPI Alliance Standard for D-PHY, version 0.65, November 2005284Design and Analysis of Fault Tolerant Digital System by Barry W. Johnson285Error Correcting Codes: Hamming Distance by Don Johnson paper286Intel 8206 error detection and correction unit datasheet287National DP8400-2 Expandable Error Checker/Corrector datasheetMuch of DSI is based on existing MIPI Alliance standards as well as several MIPI Alliance standards in 288289simultaneous development. In the Application Layer, DSI duplicates pixel formats used in MIPI Alliance 290Standard for Display Parallel Interface [3] when it is in Video Mode operation. For display modules with a 291display controller and frame buffer, DSI shares a common command set with MIPI Alliance Standard for 292Display Bus Interface [2]. The command set is documented in MIPI Alliance Standard for Display 293Command Set [1].3.1 DBI and DBI-2 (Display Bus Interface Standards for Parallel Signaling)294295DBI and DBI-2 are MIPI Alliance specifications for parallel interfaces to display modules having display 296controllers and frame buffers. For systems based on these specifications, the host processor loads images to 297the on-panel frame buffer through the display processor. Once loaded, the display controller manages all 298display refresh functions on the display module without further intervention from the host processor. Image 299updates require the host processor to write new data into the frame buffer.300DBI and DBI-2 specify a parallel interface; that is, data is sent to the peripheral over an 8-, 9- or 16-bit-301wide parallel data bus, with additional control signals.302The DSI specification supports a Command Mode of operation. Like the parallel DBI, a DSI-compliant 303interface sends commands and parameters to the display. However, all information in DSI is first serialized 304before transmission to the display module. At the display, serial information is transformed back to parallel 305data and control signals for the on-panel display controller. Similarly, the display module can return status 306information and requested memory data to the host processor, using the same serial data path.3.2 DPI and DPI-2 (Display Pixel Interface Standards for Parallel Signaling)307DPI and DPI-2 are MIPI Alliance specifications for parallel interfaces to display modules without on-panel 308309display controller or frame buffer. These display modules rely on a steady flow of pixel data from host 310processor to the display, to maintain an image without flicker or other visual artifacts. MIPI Alliance 311specifications document several pixel formats for Active Matrix (AM) display modules.312Like DBI and DBI-2, DPI and DPI-2 are specifications for parallel interfaces. The data path may be 16-, 31318-, or 24-bits wide, depending on pixel format(s) supported by the display module. This specification 314refers to DPI mode of operation as Video Mode.Some display modules that use Video Mode in normal operation also make use of a simplified form of 315316Command Mode, when in low-power state. These display modules can shut down the streaming video 317interface and continue to refresh the screen from a small local frame buffer, at reduced resolution and pixel318depth. The local frame buffer shall be loaded, prior to interface shutdown, with image content to be319displayed when in low-power operation. These display modules can switch mode in response to power-320control commands.3.3 DCS (Display Command Set)321322DCS is a specification for the command set used by DSI and DBI-2 specifications. Commands are sent 323from the host processor to the display module. On the display module, a display controller receives andinterprets commands, then takes appropriate action. Commands fall into four broad categories: read 324325register, write register, read memory and write memory. A command may be accompanied by multiple 326parameters.3.4 CSI-2 (Camera Serial Interface 2)327CSI-2 is a MIPI Alliance standard for serial interface between a camera module and host processor. It is 328329based on the same physical layer technology and low-level protocols as DSI. Some significant differencesare:330331•CSI-2 uses unidirectional high-speed Link, whereas DSI is half-duplex bidirectional Link332•CSI-2 makes use of a secondary channel, based on I2C, for control and status functions333CSI-2 data direction is from peripheral (Camera Module) to host processor, while DSI’s primary data334direction is from host processor to peripheral (Display Module).3.5 D-PHY (MIPI Alliance Standard for Physical Layer)335MIPI Alliance Standard for D-PHY [4] provides the physical layer definition for DSI. The functionality 336337specified by the D-PHY standard covers all electrical and timing aspects, as well as low-level protocols, 338signaling, and message transmissions in various operating modes.4 DSI Introduction339340DSI specifies the interface between a host processor and a peripheral such as a display module. It builds on 341existing MIPI Alliance standards by adopting pixel formats and command set specified in DPI-2, DBI-2 342and DCS standards.343Figure 1 shows a simplified DSI interface. From a conceptual viewpoint, a DSI-compliant interface 344performs the same functions as interfaces based on DBI-2 and DPI-2 standards or similar parallel display 345interfaces. It sends pixels or commands to the peripheral, and can read back status or pixel information 346from the peripheral. The main difference is that DSI serializes all pixel data, commands, and events that, in 347traditional or legacy interfaces, are normally conveyed to and from the peripheral on a parallel data bus 348with additional control signals.349From a system or software point of view, the serialization and deserialization operations should be 350transparent. The most visible, and unavoidable, consequence of transformation to serial data and back to 351parallel is increased latency for transactions that require a response from the peripheral. For example, 352reading a pixel from the frame buffer on a display module will have a higher latency using DSI than DBI. 353Another fundamental difference is the host processor’s inability during a read transaction to throttle the 354rate, or size, of returned data.355356Figure 1 DSI Transmitter and Receiver Interface4.1 DSI Layer Definitions357Application Processor Peripheral358Figure 2 DSI Layers359360A conceptual view of DSI organizes the interface into several functional layers. A description of the layers 361follows and is also shown in Figure 2.362PHY Layer: The PHY Layer specifies transmission medium (electrical conductors), the input/output 363circuitry and the clocking mechanism that captures “ones” and “zeroes” from the serial bit stream. This part 364of the specification documents the characteristics of the transmission medium, electrical parameters for 365signaling and the timing relationship between clock and Data Lanes.366The mechanism for signaling Start of Transmission (SoT) and End of Transmission (EoT) is specified, as 367well as other “out of band” information that can be conveyed between transmitting and receiving PHYs. 368Bit-level and byte-level synchronization mechanisms are included as part of the PHY. Note that the 369electrical basis for DSI (SLVS) has two distinct modes of operation, each with its own set of electrical 370parameters.371The PHY layer is described in MIPI Alliance Standard for D-PHY [4].372Lane Management Layer: DSI is Lane-scalable for increased performance. The number of data signals 373may be 1, 2, 3, or 4 depending on the bandwidth requirements of the application. The transmitter side of the 374interface distributes the outgoing data stream to one or more Lanes (“distributor” function). On the receiving end, the interface collects bytes from the Lanes and merges them together into a recombined data 375376stream that restores the original stream sequence (“merger” function).Protocol Layer: At the lowest level, DSI protocol specifies the sequence and value of bits and bytes 377378traversing the interface. It specifies how bytes are organized into defined groups called packets. The 379protocol defines required headers for each packet, and how header information is generated and interpreted.The transmitting side of the interface appends header and error-checking information to data being 380381transmitted. On the receiving side, the header is stripped off and interpreted by corresponding logic in the 382receiver. Error-checking information may be used to test the integrity of incoming data. DSI protocol also383documents how packets may be tagged for interleaving multiple command or data streams to separate384destinations using a single DSI.385Application Layer: This layer describes higher-level encoding and interpretation of data contained in the386data stream. Depending on the display subsystem architecture, it may consist of pixels having a prescribed387format, or of commands that are interpreted by the display controller inside a display module. The DSI 388specification describes the mapping of pixel values, commands and command parameters to bytes in the389packet assembly. See MIPI Alliance Standard for Display Command Set [1].4.2 Command and Video Modes390391DSI-compliant peripherals support either of two basic modes of operation: Command Mode and Video392Mode. Which mode is used depends on the architecture and capabilities of the peripheral. The mode393definitions reflect the primary intended use of DSI for display interconnect, but are not intended to restrict 394DSI from operating in other applications.Typically, a peripheral is capable of Command Mode operation or Video Mode operation. Some Video 395396Mode displays also include a simplified form of Command Mode operation in which the display may 397refresh its screen from a reduced-size, or partial, frame buffer, and the interface (DSI) to the host processor398may be shut down to reduce power consumption.Mode3994.2.1 Command400Command Mode refers to operation in which transactions primarily take the form of sending commands401and data to a peripheral, such as a display module, that incorporates a display controller. The display 402controller may include local registers and a frame buffer. Systems using Command Mode write to, and readfrom, the registers and frame buffer memory. The host processor indirectly controls activity at the 403404peripheral by sending commands, parameters and data to the display controller. The host processor can also 405read display module status information or the contents of the frame memory. Command Mode operationrequires a bidirectional interface.406407Operation4.2.2 VideoMode408Video Mode refers to operation in which transfers from the host processor to the peripheral take the form of409a real-time pixel stream. In normal operation, the display module relies on the host processor to provide410image data at sufficient bandwidth to avoid flicker or other visible artifacts in the displayed image. Video 411information should only be transmitted using High Speed Mode.412Some Video Mode architectures may include a simple timing controller and partial frame buffer, used to413maintain a partial-screen or lower-resolution image in standby or low-power mode. This permits the 414interface to be shut down to reduce power consumption.415To reduce complexity and cost, systems that only operate in Video Mode may use a unidirectional data416path.。