SI4925DDY-T1-GE3;中文规格书,Datasheet资料
SI2301CDS-T1-GE3中文资料

Vishay SiliconixSi2301CDSP-Channel 20-V (D-S) MOSFET FEATURES•Halogen-free Option Available•TrenchFET ® Power MOSFETAPPLICATIONS •Load SwitchMOSFET PRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)a Q g (Typ.)- 200.112 at V GS = - 4.5 V - 3.1 3.3 nC0.142 at V GS = - 2.5 V- 2.7Notes:a. Based on T C = 25 °C.b. Surface Mounted on 1" x 1" FR4 board.c. t = 5 s.d. Maximum under Steady State conditions is 175 °C/W.ABSOLUTE MAXIMUM RATINGS T A = 25°C, unless otherwise notedParameter Symbol Limit U nitDrain-Source Voltage V DS - 20VGate-Source Voltage V GS ± 8Continuous Drain Current (T J = 150 °C)T C = 25 °C I D- 3.1A T C = 70 °C - 2.5T A = 25 °C - 2.3b, c T A = 70 °C - 1.8b, cPulsed Drain Current I DM - 10Continuous Source-Drain Diode CurrentT C = 25 °C I S - 1.3T A = 25 °C - 0.72b, c Maximum Power Dissipation T C = 25 °C P D 1.6WT C = 70 °C 1.0T A = 25 °C 0.86b, c T A = 70 °C 0.55b, cOperating Junction and Storage T emperature Range T J , T stg - 55 to 150°C THERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient b, d ≤ 5 s R thJA 120145°C/WMaximum Junction-to-Foot (Drain)Steady State R thJF 6278Vishay SiliconixSi2301CDSNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MOSFET SPECIFICATIONS T J = 25°C, unless otherwise notedParameter Symbol Test Conditions Min.Typ.Max.U nit StaticDrain-Source Breakdown Voltage V DS V DS = 0 V, I D = - 250 µA- 20VV DS Temperature Coefficient ΔV DS /T J I D = - 250 µA - 18mV/°C V GS(th) T emperature Coefficient ΔV GS(th)/T J 2.2Gate-Source Threshold Voltage V GS(th) V DS = V GS , I D = - 250 µA - 0.4- 1V Gate-Source LeakageI GSS V DS = 0 V , V GS = ± 8 V ± 100nA Zero Gate Voltage Drain Current I DSS V DS = - 20 V , V GS = 0 V - 1µA V DS = - 20 V, V GS = 0 V , T J = 55 °C- 10On-State Drain Current aI D(on) V DS ≤ - 5 V , V GS = - 4.5 V - 6A Drain-Source On-State Resistance aR DS(on) V GS = - 4.5 V, I D = - 2.8 A 0.0900.112ΩV GS = - 2.5 V, I D = - 2.0 A 0.1100.142Forward T ransconductance a g fsV DS = - 5 V , I D = - 2.8 A2.0SDynamic bInput Capacitance C iss V DS = - 10 V , V GS = 0 V , f = 1 MHz405pFOutput CapacitanceC oss 75Reverse Transfer Capacitance C rss 55Total Gate Charge Q g V DS = - 10 V , V GS = - 4.5 V , ID = - 3 A 5.510nC V DS = - 10 V , V GS = - 2.5 V , I D = - 3 A 3.36Gate-Source Charge Q gs 0.7Gate-Drain Charge Q gd 1.3Gate Resistance R g f = 1 MHz6.0ΩTurn-On Delay Time t d(on) V DD = - 10 V, R L = 10 ΩI D = - 1 A, V GEN = - 4.5 V , R G = 1 Ω1120ns Rise Timet r 3560Turn-Off Delay Time t d(off) 3050Fall Timet f1020Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 25 °C- 1.3A Pulse Diode Forward Current a I SM - 10Body Diode VoltageV SD I S = - 0.7 A- 0.8- 1.2V Body Diode Reverse Recovery Time t rr I F = - 3.0 A, dI/dt = 100 A/µs, T J = 25 °C3050ns Body Diode Reverse Recovery Charge Q rr 2550nC Reverse Recovery Fall Time t a 15nsReverse Recovery Rise Timet b15Output CharacteristicsOn-Resistance vs. Drain Current and Gate VoltageTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureThreshold VoltageSingle Pulse PowerVishay SiliconixSi2301CDSTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?68741.Normalized Thermal Transient Impedance, Junction-to-FootDisclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
SI4925中文资料

-0.73
-1.2
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
ON CHARACTERISTICS
Gate Threshold Voltage Gate Threshold Voltage Temp. Coefficient Static Drain-Source On-Resistance
∆VGS(th)/∆TJ
RDS(ON)
Ω
ID(ON) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd IS VSD
1.4
I D= -6A VGS = -10V
I D = -3A
0.08
R DS(ON) , NORMALIZED
1.2
0.06
1
0.04
TA = 125°C 25° C
0.8
0.02
0.6 -50
-25
0
25
50
75
100
125
150
0
2
TJ , JUNCTION TEMPERATURE (° C)
SOT-23
SuperSOTTM-6
SI7116DN-T1-GE3;中文规格书,Datasheet资料

Vishay SiliconixSi7116DNN-Channel 40-V (D-S) Fast Switching MOSFETFEATURES•Halogen-free Option Available •TrenchFET ® Power MOSFET•New Low Thermal Resistance PowerPAK ®Package with Low 1.07 mm Profile •PWM Optimized •100 % R g TestedAPPLICATIONS•Synchronous Rectification •Intermediate Switch •Synchronous BuckPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)400.0078 at V GS = 10 V 16.415 nC0.010 at V GS = 4.5 V14.5Notes:a.Surface Mounted on 1" x 1" FR4 board.b.See Solder Profile (/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection.c.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameterSymbol 10 sSteady StateUnit Drain-Source Voltage V DS 40VGate-Source VoltageV GS ± 20Continuous Drain Current (T J = 150 °C)a T A = 25 °C I D16.410.5AT A = 70 °C13.18.4Pulsed Drain CurrentI DM 60Continuous Source Current (Diode Conduction)a I S 3.21.3Avalanche Current L = 0 1 mH I AS 15Avalanche EnergyE AS 11mJ Maximum Power Dissipation aT A = 25 °C P D 3.8 1.5W T A = 70 °C 2.00.8Operating Junction and Storage T emperature Range T J , T stg- 55 to 150°CSoldering Recommendations (Peak Temperature)b, c260THERMAL RESISTANCE RATINGSParameter Symbol T ypical Maximum UnitMaximum Junction-to-Ambient a t ≤ 10 s R thJA 2433°C/WSteady State 6581Maximum Junction-to-Case (Drain)Steady StateR thJC1.92.4Vishay SiliconixSi7116DNNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.MOSFET SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol T est Conditions Min.T yp.Max.UnitStaticGate Threshold Voltage V GS(th) V DS = V GS , I D = 250 µA 1.52.5VGate-Body LeakageI GSS V DS = 0 V , V GS = ± 20 V ± 100 nAZero Gate Voltage Drain Current I DSS V DS = 40 V , V GS = 0 V 1µA V DS = 40 V, V GS = 0 V , T J = 55 °C5On-State Drain Current aI D(on) V DS ≥ 5 V , V GS = 10 V 40A Drain-Source On-State Resistance a R DS(on) V GS = 10 V , I D = 16.4 A 0.00650.0078ΩV GS = 4.5 V, I D = 14.5 A 0.00830.010Forward T ransconductance a g fs V DS = 15 V , I D = 16.4 A 68S Diode Forward Voltage a V SDI S = 3.2 A, V GS = 0 V0.81.2VDynamic bTotal Gate Charge Q g V DS = 20 V , V GS = 4.5 V , I D = 16.4 A1523nCGate-Source Charge Q gs 6.7Gate-Drain Charge Q gd 5.1Gate Resistance R g f = 1 MHz0.71.42.1ΩTurn-On Delay Time t d(on) V DD = 20 V , R L = 20 ΩI D ≅ 1 A, V GEN = 10 V , R g = 6 Ω1015ns Rise Timet r 1015Turn-Off Delay Time t d(off) 3655Fall Timet f 1015Source-Drain Reverse Recovery Time t rr I F = 3.2 A, di/dt = 100 A/µs 3060Body Diode Reverse Recovery ChargeQ rrI F = 3.2 A, di/dt = 100 A/µs 2652nc Output Characteristics Transfer CharacteristicsVishay SiliconixSi7116DNTYPICAL CHARACTERISTICS 25°C, unless otherwise notedGate ChargeSource-Drain Diode Forward VoltageCapacitanceOn-Resistance vs. Gate-to-Source VoltageSafe Operating AreaVishay SiliconixSi7116DNTYPICAL CHARACTERISTICS 25°C, unless otherwise notedVishay Sil iconix maintains worl dwide manufacturing capabil ity. Products may be manufactured at one of several qual ified l ocations. Rel iabil ity data for Sil icon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?73139.Normalized Thermal Transient Impedance, Junction-to-CaseVishay SiliconixAN822PowerPAK ® 1212 Mounting and Thermal ConsiderationsJohnson ZhaoMOSFETs for switching applications are now available with die on resistances around 1 m Ω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvi-ous that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this,mounting information is presented. Finally, thermal and electrical performance is discussed.THE PowerPAK PACKAGEThe PowerPAK 1212-8 package (Figure 1) is a deriva-tive of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resis-tance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance.(Please refer to application note “PowerPAK SO-8Mounting and Thermal Considerations.”)The PowerPAK 1212-8 has a footprint area compara-ble to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger pack-ages are typically required solely for thermal consider-ation, the PowerPAK 1212-8 is a good option.Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8.The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints.PowerPAK 1212 SINGLE MOUNTINGTo take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document.In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack,experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve-ment in thermal performance.Figure 1.PowerPAK 1212 DevicesVishay SiliconixAN822PowerPAK 1212 DUALTo take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826,Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs . Click on the PowerPAK 1212-8 dual in the index of this doc-ument.The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the Pow-erPAK 1212-8 dual package.This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther-mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to-ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack,experiments have found that adding copper beyond an area of about 0.3 to 0.5 in 2 of will yield little improve-ment in thermal performance.REFLOW SOLDERINGVishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humid-ity, HAST, or pressure pot. The solder reflow tempera-ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see /doc?73257.Ramp-Up Rate+ 6°C /Second Maximum Temperature at 155 ± 15 °C 120 Seconds Maximum Temperature Above 180 °C 70 - 180 Seconds Maximum T emperature240 + 5/- 0 °CTime at Maximum T emperature 20 - 40 Seconds Ramp-Down Rate+ 6 °C/Second MaximumFigure 2. Solder Reflow Temperature ProfileFigure 3.Solder Reflow Temperatures and Time DurationsVishay SiliconixAN822THERMAL PERFORMANCE IntroductionA basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R θjc, or the junction to- foot thermal resistance, R θjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8,standard TSSOP-8 and SO-8 equivalent steady state performance.By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the tempera-ture of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junc-tion-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the Pow-erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the Power-PAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on r DS(ON) whereas a rise of over 40 °C will cause an increase in r DS(ON) as high as 20 %.Spreading CopperDesigners add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper.Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-nal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many appli-cations. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement.A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No signif-icant effect was observed.TABLE 1: EQIVALENT STEADY STATE PERFORMANCEPackage SO-8TSSOP-8TSOP-8PPAK 1212PPAK SO-8ConfigurationSingleDual Single Dual Single Dual Single Dual Single Dual Thermal Resiatance R thJC (C/W)2040528340902.45.51.85.5Figure 4. Temperature of Devices on a PC BoardVishay SiliconixAN822CONCLUSIONSAs a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal perfor-mance while having a footprint that is more than 40 %smaller than the standard TSSOP-8.Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package.The PowerPAK 1212-8 combines small size with attrac-tive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps r DS(ON) low, and permits the device to handle more current than a same- or larger-size MOS-FET die in the standard TSSOP-8 or SO-8 packages.Figure 5. Spreading Copper - Si7401DNFigure 6. Spreading Copper - Junction-to-Ambient Performance分销商库存信息: VISHAYSI7116DN-T1-GE3。
SI4459ADY-T1-GE3;中文规格书,Datasheet资料

3600
1800 Crss
Coss
0.003 0 14 28 42 ID - Drain Current (A) 56 70
0 0 6 12 18 24 VDS - Drain-to-Source Voltage (V) 30
A
mJ
Maximum Power Dissipation
PD
W
Operating Junction and Storage Temperature Range
TJ, Tstg
°C
THERMAL RESISTANCE RATINGS
Parameter Maximum Junction-to-Ambienta, c Maximum Junction-to-Foot Notes: a. Surface mounted on 1" x 1" FR4 board. b. t = 10 s. c. Maximum under steady state conditions is 80 °C/W. d. Based on TC = 25 °C. Document Number: 69979 S11-1813-Rev. B, 12-Sep-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?91000 / 1 t 10 s Steady State Symbol RthJA RthJF Typical 29 13 Maximum 35 16 Unit °C/W
SI1555DL-T1-E3中文资料

FEATURESD TrenchFET rPower MOSFETPb-free AvailableSi1555DLVishay SiliconixDocument Number: 71079S-50245—Rev. D, 21-Feb-051Complementary Low-Threshold MOSFET PairPRODUCT SUMMARYV DS (V)r DS(on) (W )I D (A)0.385 @ V GS = 4.5 V 0.70N-Channel200.630 @ V GS = 2.5 V 0.540.600 @ V GS = −4.5 V −0.60P-Channel −80.850 @ V GS = −2.5 V −0.501.200 @ V GS = −1.8 V−0.42Marking CodeRBXXLot Traceability and Date CodePart # Code Y YOrdering Information:Si1555DL-T1Si1555DL-T1—E3 (Lead (Pb)-Free)SOT-363SC-70 (6-LEADS)Top ViewS 1G 1D 2D 1G 2S 2ABSOLUTE MAXIMUM RATINGS (T A = 25_C UNLESS OTHERWISE NOTED)N-ChannelP-Channel ParameterSymbol5 secs Steady State5 secsSteady StateUnitDrain-Source Voltage V DS 20−8Gate-Source VoltageV GS "12"8VT A = 25_C "0.70"0.66−0.60−0.57Continuous Drain Current (T J = 150_C)a T A = 85_CI D "0.50"0.48−0.43−0.41Pulsed Drain CurrentI DM "1.0AContinuous Source Current (Diode Conduction)a I S 0.250.23−0.25−0.23Maximum Power Dissipation T A = 25_C 0.300.270.300.27aT A = 85_C P D 0.160.140.160.14W Operating Junction and Storage Temperature RangeT J , T stg−55 to 150_CTHERMAL RESISTANCE RATINGSParameterSymbol TypicalMaximumUnitM iJ ti t A bi t t v 5 sec 360415Maximum Junction-to-Ambient a Steady State R thJA 400460_Maximum Junction-to-Foot (Drain)Steady StateR thJF300350C/WNotesa.Surface Mounted on 1” x 1” FR4 Board.Si1555DLVishay Siliconix2Document Number: 71079S-50245—Rev. D, 21-Feb-05SPECIFICATIONS (T J = 25_C UNLESS OTHERWISE NOTED)ParameterSymbol Test Condition Min Typ Max UnitStaticV DS = V GS , I D = 250 m A N-Ch 0.6 1.4Gate Threshold VoltageV GS(th)V DS = V GS , I D = −250 m A P-Ch −0.45−1.0VGate Body Leakage V DS = 0 V, V GS = "12 V N-Ch "100Gate-Body LeakageI GSSV DS = 0 V, V GS = "8 V P-Ch "100nAV DS = 20 V, V GS = 0 VN-Ch 1V DS = −8 V, V GS = 0 V P-Ch −1Zero Gate Voltage Drain CurrentI DSSV DS = 20 V, V GS = 0 V, T J = 85_C N-Ch 5m A V DS = −8 V, V GS = 0 V, T J = 85_CP-Ch −5On State Drain Current D()V DS w 5 V, V GS = 4.5 V N-Ch 1.0On-State Drain Current aI D(on)V DS p −5 V, V GS = −4.5 V P-Ch −1.0A V GS = 4.5 V, I D = 0.66 A N-Ch 0.3200.385V GS = −4.5 V, I D = −0.57 AP-Ch 0.5100.600Drain-Source On-State Resistance ar V GS = 2.5 V, I D = 0.40 A N-Ch 0.5600.630WDS(on)V GS = −2.5 V, I D = −0.48 A P-Ch 0.7200.850V GS = −1.8 V, I D = −0.20 AP-Ch 1.00 1.200Forward Transconductance f V DS = 10 V, I D = 0.66 A N-Ch 1.5ag fs V DS = −4 V, I D = −0.57 A P-Ch 1.2S Diode Forward Voltage I S = 0.23 A, V GS = 0 V N-Ch 0.8 1.2a V SDI S = −0.23 A, V GS = 0 VP-Ch−0.8−1.2VDynamic bN-Ch 0.8 1.2Total Gate ChargeQ gN-ChannelP-Ch 1.5 2.3Gate Source Charge V DS = 10 V, V GS = 4.5 V, I D = 0.66 A N-Ch 0.06Gate-Source ChargeQ gs P-Channel4 V 45 V I 057 AP-Ch 0.17nCGate Drain Charge d V DS = −4 V, V GS = −4.5 V, I D = −0.57 A N-Ch 0.30Gate-Drain ChargeQ gd P-Ch 0.16Turn On Delay Time d()N-Ch 1020Turn-On Delay Timet d(on)P-Ch612N-ChannelN-Ch 1630Rise Timet r V DD = 10 V, R L = 20 WI D ^ 0.5 A, V GEN = 4.5 V, R = 6 W P-Ch 2550Turn Off Delay Time d(ff)g P-Channel V 4 V R 8 WN-Ch 1020Turn-Off Delay Timet d(off)DD = −4 V, R L = 8 I −0.5 A, V −4.5 V, R P-Ch 1020nsD ^ GEN = g = 6 WN-Ch 1020Fall Timet f P-Ch1020Source-DrainI F = 0.23 A, di/dt = 100 A/m s N-Ch 2040Reverse Recovery Timet rrI F = −0.23 A, di/dt = 100 A/m sP-Ch2040Notesa.Pulse test; pulse width v 300 m s, duty cycle v 2%.b.Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Si1555DLVishay SiliconixDocument Number: 71079S-50245—Rev. D, 21-Feb-0530.00.5 1.0 1.5 2.0 2.50.00.51.01.52.02.53.0V DS − Drain-to-Source Voltage (V)V GS − Gate-to-Source Voltage (V)2040608010048121620− O n -R e s i s t a n c e (r D S (o n )W )0.60.81.01.21.41.6−50−2502550751001251500123450.00.20.40.60.80.00.20.40.60.81.00.00.20.40.60.81.0V DS − Drain-to-Source Voltage (V)On-Resistance vs. Drain Current− G a t e -t o -S o u r c e V o l t a g e (V )Q g − Total Gate Charge (nC)C − C a p a c i t a n c e (p F )V G S CapacitanceOn-Resistance vs. Junction TemperatureT J − Junction Temperature (_C)r D S (o n ) − O n -R e s i i s t a n c e (N o r m a l i z e d )Si1555DLVishay Siliconix4Document Number: 71079S-50245—Rev. D, 21-Feb-05TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)N−CHANNEL0.00.20.40.60.81.01.20.00.20.40.60.81.01234510.1− O n -R e s i s t a n c e (r D S (o n )W )V SD − Source-to-Drain Voltage (V)V GS − Gate-to-Source Voltage (V)− S o u r c e C u r r e n t (A )I S 03512P o w e r (W )Single Pulse PowerTime (sec)411006001010−110−210−3−0.4−0.3−0.2−0.1−0.00.10.2−50−250255075100125150210.10.01Threshold VoltageV a r i a n c e (V )V G S (t h )T J − Temperature (_C)Normalized Thermal Transient Impedance, Junction-to-AmbientSquare Wave Pulse Duration (sec)N o r m a l i z e d E f f e c t i v e T r a n s i e n t T h e r m a l I m p e d a n c eSi1555DLVishay SiliconixDocument Number: 71079S-50245—Rev. D, 21-Feb-055TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)N−CHANNEL10−310−211010−110−4210.10.01Normalized Thermal Transient Impedance, Junction-to-FootSquare Wave Pulse Duration (sec)N o r m a l i z e d E f f e c t i v e T r a n s i e n t T h e r m a l I m p e d a n c e0.00.5 1.0 1.5 2.0 2.5V GS − Gate-to-Source Voltage (V)40801201602468− O n -R e s i s t a n c e (r D S (o n )W )0.00.51.01.52.00.00.20.40.60.81.0V DS − Drain-to-Source Voltage (V)I D − Drain Current (A)C − C a p a c i t a n c e (p F )CapacitanceSi1555DLVishay Siliconix6Document Number: 71079S-50245—Rev. D, 21-Feb-050.00.20.40.60.8 1.0 1.2 1.4 1.6Q g − Total Gate Charge (nC)0.00.20.40.60.81.01.20.00.51.01.52.01234510.1− O n -R e s i s t a n c e (r D S (o n )W )V SD − Source-to-Drain Voltage (V)V GS − Gate-to-Source Voltage (V)− S o u r c e C u r r e n t (A )I S 03512P o w e r (W )Single Pulse PowerTime (sec)411006001010−110−210−3−0.2−0.10.00.10.20.30.4−50−250255075100125150Threshold VoltageV a r i a n c e (V )V G S (t h )T J − Temperature (_C)Si1555DLVishay SiliconixDocument Number: 71079S-50245—Rev. D, 21-Feb-057TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)P−CHANNEL210.10.01Normalized Thermal Transient Impedance, Junction-to-AmbientSquare Wave Pulse Duration (sec)N o r m a l i z e d E f f e c t i v e T r a n s i e n t T h e r m a l I m p e d a n c e10−310−211010−110−4210.10.01Normalized Thermal Transient Impedance, Junction-to-FootSquare Wave Pulse Duration (sec)N o r m a l i z e d E f f e c t i v e T r a n s i e n t T h e r m a l I m p e d a n c eVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon T echnology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?71079.Document Number: 91000Revision: 18-Jul-081DisclaimerLegal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
SI7439DP-T1-GE3;中文规格书,Datasheet资料

Min. - 2.0
Typ.
Max. - 4.0 ± 100 -1 - 10
Unit V nA µA A
- 30 0.073 0.077 19 - 0.78 88 - 1.2 135 0.090 0.095
S V
Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time
FEATURES
• Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFETs • Ultra-Low On-Resistance Critical for Application • Low Thermal Resistance PowerPAK®Package with Low 1.07 mm Profile • 100 % Rg and Avalanche Tested • Compliant to RoHS Directive 2002/95/EC
Notes: a. Surface mounted on 1" x 1" FR4 board. b. See solder profile (/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 73106 S10-2246-Rev. E, 04-Oct-10 1
SI2302-TP;中文规格书,Datasheet资料

Revision: A
/
3 of 5
2011/01/01
VGS, Gate to Source Voltage (V) ID, Drain Current (A)
VTH, Normalized Gate-Source Threshold Voltage
RDS(ON), Normalized RDS(ON), On-Resistance(Ohms)
IS, Source-drain current (A)
ID, Drain Current (A)
SI2302
10 25 C
Maximum Ratings @ 25OC Unless Otherwise Specified
Symbol VDS ID IDM VGS
PD R©JA
TJ
TSTG
Parameter Drain-source Voltage Drain Current-Continuous Drain Current-Pulsed a Gate-source Voltage
MCC
TM
Micro Commercial Components
5 VDS=10V ID=3.6A
4
3
2
1
0
0
2
4
6
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
VDD
RL VIN
D
VOUT
VGS
RGEN G
S
Figure 9. Switching Test Circuit
SI2302CDS-T1-E3中文资料

Vishay SiliconixSi2302CDSN-Channel 20-V (D-S) MOSFETFEATURES•Halogen-free Option Available •TrenchFET ® Power MOSFETAPPLICATIONS•Load Switching for Portable Devices •DC/DC ConverterPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)Q g (Typ.)200.057 at V GS = 4.5 V 2.9 3.50.075 at V GS = 2.5 V2.6Notes:a. Surface Mounted on 1" x 1" FR4 board.b. Pulse width limited by maximum junction temperature.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameterSymbol 5 sSteady StateUnit Drain-Source Voltage V DS 20VGate-Source VoltageV GS ± 8Continuous Drain Current (T J = 150 °C)a T A = 25 °C I D 2.9 2.6AT A = 70 °C2.32.1Pulsed Drain Current bI DM 10Continuous Source Current (Diode Conduction)a I S 0.720.6Power Dissipation aT A = 25 °C P D 0.860.71W T A = 70 °C 0.550.46Operating Junction and Storage T emperature RangeT J , T stg- 55 to 150°CTHERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient a t ≤ 5 s R thJA 120145°C/WSteady State 140175Maximum Junction-to-FootSteady StateR thJF6278Vishay SiliconixSi2302CDSNotes:a. Pulse test: Pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximumSPECIFICATIONS T A = 25 °C, unless otherwise notedParameter Symbol Test Conditions LimitsUnitMin.Typ.Max.StaticDrain-Source Breakdown Voltage V DS V GS = 0 V , I D = 250 µA 20VGate-Threshold Voltage V GS(th) V DS = V GS , I D = 250 µA 0.400.85Gate-Body LeakageI GSS V DS = 0 V, V GS = ± 8 V ± 100nAZero Gate Voltage Drain Current I DSS V DS = 20 V , V GS = 0 V 1µA V DS = 20 V , V GS = 0 V , T J = 70 °C75On-State Drain Current a I D(on) V DS ≥ 10 V , V GS = 4.5 V 6A Drain-Source On-Resistance aR DS(on) V GS = 4.5 V, I D = 3.6 A 0.0450.057ΩV GS = 2.5 V, I D = 3.1 A 0.0560.075Forward T ransconductance a g fs V DS = 5 V, I D = 3.6 A 13S Diode Forward Voltage V SDI S = 0.95 A, V GS = 0 V0.71.2VDynamic bTotal Gate Charge Q g V DS = 10 V , V GS = 4.5 V, I D = 3.6 A3.5 5.5nCGate-Source Charge Q gs 0.6Gate-Drain Charge Q gd 0.45Gate Resistance R gf = 1.0 MHz2.04.08.0ΩSwitchingTurn-On Delay Time t d(on) V DD = 10 V , R L = 2.78 ΩI D ≅ 3.6 A, V GEN = 4.5 V , R g = 1 Ω815nsRise Timet r 715Turn-Off Delay Time t d(off) 3045Fall Timet f 715Source-Drain Reverse Recovery Time t rr I F = 3.6 A, dI/dt = 100 A/µs 8.515Body Diode Reverse Recovery ChargeQ rr2.04.0nCTransfer CharacteristicsCapacitanceOn-Resistance vs. Junction TemperatureOn-Resistance vs. Drain CurrentGate ChargeSource-Drain Diode Forward VoltageVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?68645.Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。
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Vishay SiliconixSi4925DDYDocument Number: Dual P-Channel 30-V (D-S) MOSFETFEATURES•Halogen-free•TrenchFET ® Power MOSFET •100 % UIS TestedAPPLICATIONS•Load Switches- Notebook PCs - Desktop PCsPRODUCT SUMMARYV DS (V)R DS(on) (Ω)I D (A)d, eQ g (Typ.)- 300.029 at V GS = - 10 V- 815 nC0.041 at V GS = - 4.5 V- 8Notes:a.Surface mounted on 1" x 1" FR4 board.b.t = 10 s.c.Maximum under Steady State conditions is 85 °C/W.d.Based on T C= 25 °C.e.Limited by package.ABSOLUTE MAXIMUM RATINGS T A = 25 °C, unless otherwise notedParameter Symbol Limit UnitDrain-Source Voltage V DS - 30VGate-Source VoltageV GS ± 20Continuous Drain Current (T J = 150 °C)T C = 25 °C I D- 8.0e AT C = 70 °C - 8.0eT A = 25 °C - 7.3a, b T A = 70 °C - 5.9a, bPulsed Drain CurrentI DM - 32e Continuous Source-Drain Diode CurrentT C = 25 °CI S - 4.1T A = 25 °C - 2.0a, bAvalanche Current L = 0.1 mHI AS - 20Single-Pulse Avalanche Energy E AS 20mJMaximum Power Dissipation T C = 25 °C P D 5.0WT C = 70 °C 3.2T A = 25 °C 2.5a, b T A = 70 °C 1.6a, bOperating Junction and Storage T emperature Range T J , T stg - 55 to 150°CTHERMAL RESISTANCE RATINGSParameter Symbol Typical Maximum UnitMaximum Junction-to-Ambient a, c t ≤ 10 s R thJA 3850°C/WMaximum Junction-to-Foot Steady State R thJF 2025 Document Number: 68969Vishay SiliconixSi4925DDYNotes:a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.b. Guaranteed by design, not subject to production testing.Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.SPECIFICATIONS T J = 25 °C, unless otherwise notedParameter Symbol Test Conditions Min. Typ.Max.UnitStaticDrain-Source Breakdown Voltage V DS V GS = 0 V , I D = - 250 µA- 30V V DS Temperature Coefficient ΔV DS /T J I D = - 250 µA - 31mV/°C V GS(th) T emperature Coefficient ΔV GS(th)/T J 4.5Gate-Source Threshold Voltage V GS(th) V DS = V GS , I D = - 250 µA - 1.0- 3.0V Gate-Source LeakageI GSS V DS = 0 V , V GS = ± 20 V ± 100nA Zero Gate Voltage Drain Current I DSS V DS = - 30 V, V GS = 0 V - 1µA V DS = - 30 V, V GS = 0 V , T J = 55 °C- 5On-State Drain Current aI D(on) V DS ≥ - 10 V , V GS = - 10 V - 30A Drain-Source On-State Resistance a R DS(on) V GS = - 10 V , I D = - 7.3 A 0.0240.029ΩV GS = - 4.5 V , I D = - 6.2 A 0.0330.041Forward T ransconductance a g fs V DS = - 10 V, I D = - 9.1 A23SDynamic bInput Capacitance C iss V DS = - 15 V , V GS = 0 V , f = 1 MHz1350pFOutput CapacitanceC oss 215Reverse Transfer Capacitance C rss 185Total Gate Charge Q g V DS = - 15 V, V GS = - 10 V , ID = - 9.1 A 3250nC V DS = - 15 V , V GS = - 4.5 V , I D = - 9.1 A 1525Gate-Source Charge Q gs 4Gate-Drain Charge Q gd 7.5Gate Resistance R g f = 1 MHz5.8ΩTurn-On Delay Time t d(on) V DD = - 15 V , R L = 15 Ω I D ≅ - 1 A, V GEN = - 10 V , R g = 1 Ω1015ns Rise Timet r 815Turn-Off DelayTime t d(off) 4570Fall Timet f 1225Turn-On Delay Time t d(on) V DD = - 15 V , R L = 15 Ω I D ≅ - 1 A, V GEN = - 4.5 V, R g = 1 Ω4270Rise Timet r 3560Turn-Off DelayTime t d(off) 4070Fall Timet f1630Drain-Source Body Diode Characteristics Continous Source-Drain Diode Current I S T C = 25 °C- 4.1A Pulse Diode Forward Current I SM - 32Body Diode VoltageV SD I S = - 2 A, V GS = 0 V- 0.75- 1.2V Body Diode Reverse Recovery Time t rr I F = - 2 A, dI/dt = 100 A/µs, T J = 25 °C3460ns Body Diode Reverse Recovery Charge Q rr 2240nC Reverse Recovery Fall Time t a 11nsReverse Recovery Rise Timet b23Document Number: Gate ChargeCapacitanceOn-Resistance vs. Junction Temperature Document Number: 68969Threshold VoltageSingle Pulse Power, Junction-to-AmbientVishay SiliconixSi4925DDYDocument Number: TYPICAL CHARACTERISTICS 25°C, unless otherwise noted* The power dissipation P D is based on T J(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.Power, Junction-to-FootPower Derating, Junction-to-Ambient Document Number: 68969Vishay SiliconixSi4925DDYTYPICAL CHARACTERISTICS 25 °C, unless otherwise notedVishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?68969.Normalized Thermal Transient Impedance, Junction-to-FootVishay SiliconixPackage InformationDocument Number: DIM MILLIMETERSINCHESMin Max Min Max A 1.35 1.750.0530.069A 10.100.200.0040.008B 0.350.510.0140.020C 0.190.250.00750.010D 4.80 5.000.1890.196E 3.804.000.1500.157e 1.27 BSC0.050 BSCH 5.80 6.200.2280.244h 0.250.500.0100.020L 0.500.930.0200.037q 0°8°0°8°S0.440.640.0180.026ECN: C-06527-Rev. I, 11-Sep-06DWG: 5498V I S H A Y S I L I C O N I XTrenchFET ® Power MOSFETsMounting LITTLE FOOT ®, SO-8 Power MOSFETsA P P L I C A T I O N N O T EWharton McDanielSurface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (/ppg?72286), for the basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.Figure 1. Single MOSFET SO-8 Pad Pattern With Copper SpreadingFigure 2. Dual MOSFET SO-8 Pad PatternWith Copper SpreadingThe minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically.A final item to keep in mind is the width of the power traces.The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.Application Note 826Vishay SiliconixA P P L I C A T I O N N O T ERECOMMENDED MINIMUM PADS FOR SO-8Legal Disclaimer Notice VishayDisclaimerALL PRODU CT, PRODU CT SPECIFICATIONS AND DATA ARE SU BJECT TO CHANGE WITHOU T NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product.Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein.Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.Material Category PolicyVishay Intertechnology, Inc. hereb y certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.Revision: 12-Mar-121Document Number: 91000分销商库存信息: VISHAYSI4925DDY-T1-GE3。