05_Using_AccelWare_Lab

Using AccelWare LabUsing AccelWare LabIntroductionThis lab exercise will introduce you to the AccelWare™ DSP IP tool kit generators. AccelWareDSP IP tool kit is a library of over fifty IP generators, available in the form of three tool kits thatproduce synthesizable MATLAB® software for common MATLAB software built-in and toolboxfunctions. Each generator offers macro- and micro-architecture selections that allow fullcustomization of the generated model to the target application requirements. ObjectivesAfter completing this lab, you will be able to:Replace a hand-coded Polyphase Decimation Filter with an equivalent AccelWare DSP IPtool kit modelBuild a simple Digital Down Converter using AccelWare DSP IP tool kit models ProcedurePart A – Replacing the Polyphase Decimation Filter with AccelWare FIRdecimIn this part of the lab, you will replace the polyphase decimation filter that you created in the lastlab with an AccelWare DSP IP tool kit FIRdecim model.n Copy the project files developed in the lab MultirateDesign/part_b (for the polyphase decimation by 2 filter) into the folder UsingAccelWare/part_a? 1.What is the cutoff of the non-decimated filter?________________________________________________________________________________________________________________________________ o Create a new function called “ddc.m” with the same inputs and outputs as the decimation filter. Call this function from the streaming loop. Call the decimation filter created in theMultirate Design lab from this new function. Basically, you are pushing the decimation filterdown a level of hierarchy onto a new function. Doing this will allow you to add additionalfunctionality to the ddc.m function in Part B of this lab. Once complete, simulate the model; itshould simulate the samefor n = 1:length(X)[y(n),valid(n)] = ddc(X(n));endp Invoke the AccelDSP™ synthesis tool and click the Project icon on the toolbar. Select the Create AccelWare Core tab, and then select the FIRDecim IP block as shown belowq Enter/Select the following parameters:ParameterValue Filter Coefficients Sourcefrom text file Coefficient fileSelect the “b.txt” file created in the script file b = fir1(NUMTAPS-1,BE); save b.txt –ascii –double b; m (2:65000)2Filter formDirect – Resource Shared Branches auto Programmable Coefficientsno Storage MappingRegister Mapped Number of Channels1 Input StructureSerial Pipeliningno Input word length16 Input fractional length13 Coefficients word length16 Output bitwidthauto Truncation8 Destination folder current project folderr Set the Project Options as follows:OptionValue Frequency (MHz) 100 RTL Simulation ModelsimOnce the AccelWare DSP IP tool kit decimation filter has been generated, a project including a testbench is also created. Perform the floating-point simulation step and look at thegenerated plot. The bottom plot is a comparison of the AccelWare DSP IP tool kit decimation filter response against a MATLAB software behavioral model. The AccelWare DSP IP tool kit model is fixed-point and you can see that the error is on the order of 10e-5. When you replace the synth_filter_decim2 filter with this one, you should expect the max error plot to show a similar max error.s Run the flow through Verify Fixed Point, and then save and close the firdecim projectt When you generated the IP, a new folder was created in the part_a folder called “firdecim_001”. Copy the “firdecim_001.m” and the “firdecim_001.add” files from this folder and place them into the 05_UsingAccelWare/part_a folderNote: The file “firdecim_001.m” is a synthesizable MATLAB software file that will be used in place of the hand-coded decimation filter. The “firdecim_001.add” file is a hierarchical directives file that contains information used by the AccelDSP synthesis tool to generate the RTL model.Note: The hardware architecture used to implement the AccelWare DSP IP tool kit decimation filter has one additional clock cycle of latency than the decimation filter created in the previous lab.In the following steps, you are going to use a text editor to substitute the AccelWare DSP IP tool kit firdecim_001(x) filter for the synth_filter_decin2(x) and then implement the filter using the AccelDSP synthesis tool.n Open the ddc.m file for edit and substitute the AccelWare DSP IP tool kit firdecim_001(x) filter for the synth_filter_decin2(x). The code should look like the following:function [FilterOut,valid] = ddc(FilterIn);%[FilterOut,valid] = synth_filter_decim2(FilterIn);[FilterOut,valid] = firdecim_001(FilterIn);o Use MATLAB software to simulate the AccelWare DSP IP tool kit decimation filter. As shown below, the filter response should be the samep Invoke the AccelDSP synthesis tool. Create a new project and call the project “proj2” and perform the Verify Floating Point, Analyze, Generate Fixed Point, and Verify Fixed Point stepsq Perform the Generate RTL step and record the number of hardware resources from the Generate RTL Report:# of Multipliers# of Adders# of Subtractorsr Perform the Verify RTL step and record the following values from the Verify RTL Report: Startup Clock CyclesCycles per Outputs Perform the Synthesize RTL step and record the following values from the Xilinx XST Synthesis Report:SlicesSlice Flip-Flops4 input LUTsbonded IOBsFIFO16/RAMB16sGCLKsDSP48sEstimated FrequencyInput SamplingPart B – Creating a Simple Digital Down ConverterYou are going to implement a simplified version of the typical digital down converter (shownbelow) by using two decimation filters. DDCs are typically used to perform channel accessfunctions in digital receivers. DDCs accept an input signal sampled at a high rate and downconverts it to a band-of-interest. Often a CIC decimation filter is used to perform a largedownsampling operation followed by two polyphase decimation filters.In this part of the lab, you are going to connect two polyphase decimation filters in series to createa simple down sampler with a total decimation of 4.n Copy the files from the UsingAccelWare/part_a folder into the UsingAccelWare/part_b folder and change the MATLAB software working directory to the UsingAccelWare/part_bfoldero Copy the files “firdecim_001.m” and “firdecim_001.add” to create a second file pair “firdecim_002.m” and “firdecim_002.add”. Because the M-file uses MATLAB softwarepersistent variables, you cannot simply instantiate the same file twice—you need to create aunique file name for each instantiationp Edit the “ddc.m” file to connect the two polyphase decimation filters in series to realize a total downsample of 4. Use the valid signals from each function to control this operation. Thesecond decimation filter should only be called when the valid signal from the first decimationfilter is active-High. Example code is shown below:[y1,valid1] = firdecim_001(x_sum);if valid1 == 1[y,valid] = firdecim_002(y1);elsey = 0;valid = 0;endNote: In the next section of the lab, you are going to complete the simple digital down converter by adding a direct digital frequency synthesis function to the down sampler. The DDS consists of a phase accumulator block feeding a sin function. A standard function call to the MATLAB software sin() will be used but the AccelDSP synthesis tool kit will use IP Explorer to automatically select and generate a specific hardware architecture for the sin function.PhaseInq To support the functionality of a DDS, add a new input to the design function “ddc” called “PhaseIn” as shown below:for n = 1:length(X)[y(n),valid(n)] = ddc(X(n),PhaseIn);endr In the top-level script file, define the input “PhaseIn” as shown below:% Set the Phase In to 14 MHz for the DDS, assuming L = 20 bitsDDS_Frequency = 100;% MHzDesiredFreq = 14; % MHzPhaseIn = floor(DesiredFreq/DDS_Frequency*2^20);s In the design function “ddc.m”, add the following code at the top of the file to model the DDS function. The output of the DDS function is “Sine”. Note the use of the standard function“sin()”% Create Direct Digital Synthesizerpersistent phase_accumif isempty(phase_accum)phase_accum = 0;end% The scaling for theta and phase_accum is related to% the word-length of L (20 bits)theta = floor(phase_accum/2^11)*pi/2^8;phase_accum = phase_accum + PhaseIn;Sine = sin(theta);t Add the variable “Sine” to the design function output argument list. You want to plot the sine wave values over time from the script fileu Modify the MATLAB software language in the “ddc” function to multiply the output of the sine wave generator “Sine” with the DDC function input “x”. This is shown belowsymbolically as the multiply operation:v Modify the output analysis in the script file, as shown below, because you want to show the effects of the DDC in a meaningful way% Generate power spectral density of the filter outputs[Pout,Wout]=aw_psd(y,256,100e6);[Pout2,Wout2]=aw_psd(Sine,1024,100e6);% Plot the PSD Responsesubplot(2,1,1);plot(Wout,10*log10(Pout),'r');title('DDC PSDResponse')In the following steps you are going to implement the filter using the AccelDSP synthesis tool. n Simulate the algorithm to ensure that there are no coding errors. The following waveform should appear:o Load the project for this design into the AccelDSP synthesis tool and perform the Verify Floating Point, Analyze, and Generate Fixed Point stepsp Expand the project browser, select the instantiation of the sin function, and view the propertiesq Expand down into the sin function and double-click any of the objects. This will allow you to view the MATLAB software source code for the sin function. The AccelDSP synthesis toolhas automatically generated a sin function and swapped it into the design. The architecturethat was selected was CORDIC. This is based in the input bit widthsr Set a quantize directive on the variable “theta” and set it to a word length = 20, fractional width = 15s Perform the Generate Fixed Point step again? 2.Which hardware macro-architecture did IP Explorer select for the sin function?________________________________________________________________________________________________________________________________ ConclusionAccelWare DSP IP tool kit modules can be auto-inferred or manually generated. Each moduleprovides multiple silicon architectures that you can customize. By default, IP Explorer selects anappropriate architecture for an AccelWare DSP IP tool kit instance; however, the designer canoverride the default selection.。