C0940中文资料
CD4029中文资料
5.0 10.0 15.0 5.0 10.0 15.0 5.0 10.0 15.0 5.0 10.0 15.0
5.0 10.0 15.0
规范值
最小
最大
500
240
180
560
260
190
200
100
80
200
100
80
2.0
-
4.0
5.5
-
180
90
60
-
15
15
15
60
20
12
340
140
100
动态特性（TA＝25℃）： 参数
测试条件
CP 操作
tPLH、tPHL 传输 延迟时间
CP → Q
CP → CO
CL＝50pF RL＝200k tr＝20ns tf＝20ns
tTLH、tTHL 输出 转换时间
CP → Q
CP → CO
fcp
CP 频率（对 CO）
tw
CP 脉冲宽度
tr、tf
CP 上升或下降时 间
电子工程师之家
CC4029------4位二进制/十进制加减计数器 简要说明：
CC4029 是由具有预进位功能的 4 位二进制或 BCD 码十进制加减计数器构成。 LD 为高电平时，D0～D3 预置计数器为任何状态，为低电平时，对计数器清零。当 CI 和 LD 均为低电平时，在时钟上升沿计数器计数。CO 一般为高电平，只有在加至最 大或减至最小时，为低电平。计数器闲置时， CI 端需与 Vss 相连，当 B/ D 为高电 平时，以二进制计数；反之，为十进制。U/ D 为高电平时，为加计数器；反之，为 减计数器。
FPGA可编程逻辑器件芯片EP4CE40F29I7N中文规格书
Chapter 5:Clock Networks and PLLs in Arria II DevicesPLLs in Arria II Devices Arria II Device Handbook Volume 1: Device Interfaces and IntegrationBypassing PLLBypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9 counters) factor of one.Table 5–20 lists the settings for bypassing the counters in Arria II PLLs.f For more information about how to use the PLL scan chain bit settings, refer to thePhase Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide .1To bypass any of the PLL counters, set the bypass bit to 1, causing the values on theother bits to be ignored. To bypass the VCO post-scale counter (K ), set thecorresponding bit to 0.Dynamic Phase-ShiftingThe dynamic phase-shifting feature allows the output phases of individual PLLoutputs to be dynamically adjusted relative to each other and to the reference clock without having to send serial data through the scan chain of the corresponding PLL. This feature simplifies the interface and allows you to quickly adjust clock-to-out (t CO ) delays by changing the output clock phase-shift in real time. This adjustment isachieved by incrementing or decrementing the VCO phase-tap selection to a given C counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a time. The output clocks are active during this phase-reconfiguration process.Table 5–21 lists the control signals that are used for dynamic phase-shifting.Table 5–20.PLL Counter Settings for Arria II Devices PLL Scan Chain Bits [0..8] SettingsLSBMSB Description 0(1), X (2)X X X X X X X 1 (3)PLL counter bypassed X X X X X X X X 0 (3)PLL counter not bypassed because bit 8 (MSB ) is set to 0Notes to Table 5–20:(1)For Arria II GX devices.(2)For Arria II GZ devices(3)Counter-bypass bit.Table 5–21.Dynamic Phase-Shifting Control Signals for Arria II Devices (Part 1 of 2)Signal Name DescriptionSource Destination PHASECOUNTERSELECT[3:0]Counter select. Four bits decoded to selecteither the M or one of the C counters for phaseadjustment. One address maps to select allC counters. This signal is registered in the PLLon the rising edge of scanclk .Logic array or I/O pins PLL reconfiguration circuit PHASEUPDOWN Selects dynamic phase shift direction;1=UP;0=DOWN. Signal is registered in thePLL on the rising edge of scanclk .Logic array or I/O pin PLL reconfiguration circuit PHASESTEPLogic high enables dynamic phase shifting.Logic array or I/O pin PLL reconfigurationcircuitChapter 6:I/O Features in Arria II DevicesI/O StructureI/O registers are composed of the input path for handling data from the pin to thecore, the output path for handling data from the core to the pin, and the output enablepath for handling the OE signal to the output buffer. These registers allow fastersource-synchronous register-to-register transfers and resynchronization. You canbypass each block of the output and output enable paths. Figure6–3 and Figure6–4show the Arria II IOE structure.Figure6–3.IOE Structure for Arria II GX DevicesArria II Device Handbook Volume 1: Device Interfaces and IntegrationChapter 2:Logic Array Blocks and Adaptive Logic Modules in Arria II DevicesLogic Array Blocks Arria II Device Handbook Volume 1: Device Interfaces and Integration The LAB of the Arria II device has a derivative called memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB. The MLAB supports a maximum of 640bits of simple dual-port SRAM. You can configure each ALM in an MLAB as either a 64 × 1 or 32 × 2 block, resulting in a configuration of 64 × 10 or32 × 20 simple dual-port SRAM blocks. MLAB and LAB blocks always coexist as pairs in Arria II devices. MLAB is a superset of the LAB and includes all LAB features.Figure 2–2 shows an overview of LAB and MLAB topology.f For more information about MLABs, refer to the TriMatrix Memory Blocks in Arria IIDevices chapter.Figure 2–B and MLAB Structure in Arria II DevicesNote to Figure 2–2:(1)You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM.MLABLAB。
EP3C25Q240C8中文资料(Altera)中文数据手册「EasyDatasheet - 矽搜」
—
1.71 1.8 1.89
V
—
1.425 1.5 1.575 V
电源电压为输出缓冲器,1.2-V
手术
—
1.14 1.2 1.26
V
VCCA (3)
VCCD_PLL (3) VI VO
供应（模拟）电压PLL
调节器
供应（数字）电压PLL
输入电压 输出电压
TJ
工作结温
tRAMP IDiode
电源斜坡时间
电源电压为输出缓冲器,3.3-V
手术
—
1.15 1.2 1.25
V
—
3.135 3.3 3.465 V
电源电压为输出缓冲器,3.0-V
手术
—
2.85
3
3.15
V
VCCIO (3), (4)
电源电压为输出缓冲器,2.5-V
手术
电源电压为输出缓冲器,1.8-V
手术
电源电压为输出缓冲器,1.5-V
手术
—
2.375 2.5 2.625 V
直流电流幅度
当启用PCI-钳位二极管
—
— — —
对于商业用途 工业用 对于扩展温度 对于汽车使用 标准上电复位
(POR) (5) 快速POR (6)
—
2.375 2.5 2.625 V
1.15 1.2 1.25
V
–0.5 —
3.6
V
0
—
VCCIO
V
0
—
85
°C
–40 — 100 °C
–40 — 125 °C
表1-4 列出I / O引脚泄漏 目前Cyclone III器件.
f
有关功耗估算工具更多信息 ,请参
CD4019中文资料
TL F 5940CD4002M CD4002C Dual 4-Input NOR Gate CD4012M CD4012C Dual 4-Input NAND GateMarch 1988CD4002M CD4002C Dual 4-Input NOR Gate CD4012M CD4012C Dual 4-Input NAND GateGeneral DescriptionThese NOR and NAND gates are monolithic complementa-ry MOS (CMOS)integrated circuits The N-and P-channel enhancement mode transistors provide a symmetrical cir-cuit with output swings essentially equal to the supply volt-age This results in high noise immunity over a wide supply voltage range No DC power other than that caused by leak-age current is consumed during static conditions All inputs are protected against static discharge and latching condi-tionsFeaturesY Wide supply voltage range 3 0V to 15V Y Low power10nW (typ )YHigh noise immunity0 45V DD (typ )ApplicationsY Automotive Y Alarm system Y Data terminals Y Industrial controls Y Instrumentation Y Remote metering YMedical ElectronicsYComputersConnection DiagramsCD4002Dual-In-Line PackageTL F 5940–1Top ViewCD4012Dual-In-Line PackageTL F 5940–2Top ViewOrder Number CD4002or CD4012C 1995National Semiconductor Corporation RRD-B30M105 Printed in U S AAbsolute Maximum Ratings(Note1)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin V SS b0 3V to V DD a0 3V Operating Temperature RangeCD4002M CD4012M b55 C to a125 C CD4002C CD4012C b40 C to a85 C Storage Temperature Range(T S)b65 C to a150 C Power Dissipation(P D)Dual-In-Line700mW Small Outline500mW Operating Range(V DD)V SS a3 0V to V SS a15V Lead Temperature(T L)(Soldering 10seconds)260 CDC Electrical Characteristics CD4002M CD4012MLimitsSymbol Parameter Conditions b55 C a25 C a125 C UnitsMin Max Min Typ Max Min MaxI DD Quiescent V DD e5 0V0 050 0010 053 0m ADevice Current V DD e10V0 10 0010 16m A P D Quiescent Device V DD e5 0V0 250 0050 2515m W Dissipation Package V DD e10V1 00 011 060m W V OL Output Voltage V DD e5 0V V I e V DD I O e0A0 0500 050 05V Low Level V DD e10V V I e V DD I O e0A0 0500 050 05V V OH Output Voltage V DD e5 0V V I e V SS I O e0A4 954 955 04 95V High Level V DD e10V V I e V SS I O e0A9 959 95109 95V V NL Noise Immunity V DD e5 0V V O e3 6V I O e0A1 51 52 251 4V (All Inputs)V DD e10V V O e7 2V I O e0A3 03 04 52 9V V NH Noise Immunity V DD e5 0V V O e0 95V I O e0A1 41 52 251 5V (All Inputs)V DD e10V V O e2 9V I O e0A2 93 04 53 0V I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 50 401 00 28mAN-Channel(4002)V DD e10V V O e0 5V V I e V DD1 10 92 50 65mA (Note2)I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 62b0 5b2 0b0 35mAP-Channel(4002)V DD e10V V O e9 5V V I e V SS b0 62b0 5b1 0b0 35mA (Note2)I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 310 250 50 175mAN-Channel(4012)V DD e10V V O e0 5V V I e V DD0 630 50 60 35mA (Note2)I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 31b0 25b0 5b0 175mAP-Channel(4012)V DD e10V V O e9 5V V I e V SS b0 75b0 6b1 2b0 4mA (Note2)I I Input Current10pANote1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operationNote2 I D N and I D P are tested one output at a time2DC Electrical Characteristics CD4002C CD4012CLimitsSymbol Parameter Conditions b55 C a25 C a85 C UnitsMin Max Min Typ Max Min MaxI DD Quiescent V DD e5 0V0 50 0050 515m ADevice Current V DD e10V5 00 0055 030m A P D Quiescent Device V DD e5 0V2 50 0252 575m W Dissipation Package V DD e10V500 0550300m W V OL Output Voltage V DD e5 0V V I e V DD I O e0A0 0500 050 05V Low Level V DD e10V V I e V DD I O e0A0 0500 050 05V V OH Output Voltage V DD e5 0V V I e V SS I O e0A4 954 955 04 95V High Level V DD e10V V I e V SS I O e0A9 959 95109 95V V NL Noise Immunity V DD e5 0V V O t3 6V I O e0A1 51 52 251 4V (All Inputs)V DD e10V V O t7 2V I O e0A3 03 04 52 9V V NH Noise Immunity V DD e5 0V V O s0 95V I O e0A1 41 52 251 5V (All Inputs)V DD e10V V O s2 9V I O e0A2 93 04 53 0V I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 350 31 00 24mAN-Channel(4002)V DD e10V V O e0 5V V I e V DD0 720 62 50 48mA (Note2)I D N Output Drive Current V DD e5 0V V O e0 4V V I e V DD0 1450 120 50 095mAN-Channel(4012)V DD e10V V O e0 5V V I e V DD0 30 250 60 2mA (Note2)I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 35b0 3b2 0b0 24mAP-Channel(4002)V DD e10V V O e9 5V V I e V SS b0 3b0 25b1 0b0 2mA (Note2)I D P Output Drive Current V DD e5 0V V O e2 5V V I e V SS b0 145b0 12b0 5b0 095mAP-Channel(4012)V DD e10V V O e9 5V V I e V SS b0 35b0 3b1 2b0 24mA (Note2)I I Input Current10pANote1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operationNote2 I D N and I D P are tested one output at a time3AC Electrical Characteristics T A e25 C C L e15pF and input rise and fall times e20ns Typical temperature coefficient for all values of V DD e0 3% CSymbol Parameter Conditions Min Typ Max Units CD4002Mt PHL Propagation Delay Time V DD e5 0V3550ns High to Low Level V DD e10V2540ns t PLH Propagation Delay Time V DD e5 0V3550ns Low to High Level V DD e10V2540ns t THL Transition Time High V DD e5 0V65175ns to Low Level V DD e10V3575ns t TLH Transition Time Low V DD e5 0V65125ns to High Level V DD e10V3570nsC IN Input Capacitance Any Input5 0pFCD4002Ct PHL Propagation Delay Time V DD e5 0V35120ns High to Low Level V DD e10V2565ns T PLH Propagation Delay Time V DD e5 0V3580ns Low to High Level V DD e10V2555ns t THL Transition Time High V DD e5 0V65300ns to Low Level V DD e10V35125ns t TLH Transition Time Low V DD e5 0V65200ns to High Level V DD e10V35115nsC IN Input Capacitance Any Input5 0pFAC Parameters are guaranteed by DC correlated testingAC Electrical Characteristics T A e25 C C L e15pF and input rise and fall times e20ns Typical temperature coefficient for all values of V DD e0 3% CSymbol Parameter Conditions Min Typ Max Units CD4012Mt PHL Propagation Delay Time V DD e5 0V5075ns High to Low Level V DD e10V2540ns t PLH Propagation Delay Time V DD e5 0V5075ns Low to High Level V DD e10V2540ns t THL Transition Time High V DD e5 0V75125ns to Low Level V DD e10V5075ns t TLH Transition Time Low V DD e5 0V75100ns to High Level V DD e10V4060nsC IN Input Capacitance Any Input5 0pFCD4012Ct PHL Propagation Delay Time V DD e5 0V50100ns High to Low Level V DD e10V2550ns T PLH Propagation Delay Time V DD e5 0V50100ns Low to High Level V DD e10V2550ns t THL Transition Time High V DD e5 0V75150ns to Low Level V DD e10V50100ns t TLH Transition Time Low V DD e5 0V75125ns to High Level V DD e10V4075nsC IN Input Capacitance Any Input5 0pFAC Parameters are guaranteed by DC correlated testingNote1 ‘‘Absolute Maximum Ratings’’are those values beyond which the safety of the device cannot be guaranteed Except for‘‘Operating Temperature Range’’they are not meant to imply that the devices should be operated at these limits The table of‘‘Electrical Characteristics’’provides conditions for actual device operation4Physical Dimensions inches(millimeters)Ceramic Dual-In-Line Package(J)Order Number CD4002MJ CD4002CJ CD4012MJ or CD4012CJNS Package Number J14A5C D 4002M C D 4002C D u a l 4-I n p u t N O R G a t e C D 4012M C D 4012C D u a l 4-I n p u t N A N D G a t ePhysical Dimensions inches (millimeters)(Continued)Molded Dual-In-Line Package (N)Order Number CD4002MN CD4002CN CD4012MN or CD4012CNNS Package Number N14ALIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor National Semiconductor National Semiconductor CorporationEuropeHong Kong LtdJapan Ltd1111West Bardin RoadFax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309。
cd4020中文资料
ｆｐ
输入电压……－0.5V~VDD+0.5V
． 输入电流…………….±10mA ｗｗ 储存稳定…………－65℃～150℃
逻辑符号：
ｗ
引出端排列（俯视）：
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ｍ
ｏ
ｃ
．
ｍ
ｒ
ａ
－
ａ
ｇ
ｐ
功能表：
．ｆ
ｗ
ｗ
ｗ
逻辑图：
静态特性：
海纳电子资讯网ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ为您提供各种ＩＣ的应用资料
参数
测试条件
规范值
VO
VI VDD -55℃ -40℃
（V） （V） （V）
25℃
85℃ 125℃ 单位
VOL 输出低
-
5/0 5.0
0.05
V
电平电压
10/0 10.0
（最大）
15/0 15.0
VOH 输出高
-
5/0 5.0
4.95
电平电压
10/0 10.0
9.95
V ｍ
（最小）
15/0 15.0
海纳电子资讯网ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ为您提供各种ＩＣ的应用资料
CC4020-----14位二进制串行计数器
简要说明：
CC4020 是 14 位二进制串行计数器。所有的计数器为主从触发器。计数器在时
钟下降沿进行计数。CR 为高电平时，对计数器进行清零。由于在时钟输入端使用斯
密特触发器，对脉冲上升和下降时间无限制，所有输入和输出均经过缓冲。 CC4020 提供了 16 引线多层陶瓷双列直插（D）、熔封陶瓷双列直插（J）、塑料
AP4409AGEM中文资料
D D D D
SO-8
G S SS
Description
Advanced Power MOSFETs from APEC provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness.
-35 -
-
V
-
- 7.5 mΩ
-
- 15 mΩ
-1 - -3 V
-
7
-
S
-
- -10 uA
-
- -25 uA
-
- ±30 uA
- 58 90 nC
-
7
- nC
- 37 - nC
- 15 - ns
- 13 - ns
- 76 - ns
- 60 - ns
- 4100 6600 pF
- 640 - pF
- 530 - pF
BVDSS RDS(ON)
VGS(th) gfs IDSS
IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Drain-Source Breakdown Voltage Static Drain-Source On-Resistance2
Gate Threshold Voltage Forward Transconductance
0.01 0.01
0.1
1
10
-V DS , Drain-to-Source Voltage (V)
1s DC
MSDS_ACT940
灭火方法和灭火剂：泡沫、二氧化碳、干的化学制品
灭火注意事项：穿戴正压呼吸器和备有抗化学物的全副保护衣。
第六部分 泄漏应急处理
应急处理：大量外漏时，迅速报警、疏散有关人员、隔离污染区，排除所有易燃的根源（火焰、信号灯火焰及电火花）。慎防与排出的液体、下水沟、水道或其他水源接触。如果发生水污染，通知有关当局。
医生须知：
这一种吸入性危险物料。在决定是否以呕吐方法时，必须考虑吸入性物料引起口腔中毒的潜在可能性（参第3部分-吞食）。以下器官（或器官系统）的紊乱可能会因接触该物料而恶化；器官包括皮肤、肺（如气喘病）、肝及肾。
第五部分 消防措施
危险特性：水汽较空气重并可以沿地面进行或被空气流动而移动及因受热、信号灯、其他火焰或在物料处理点以外的火源而着火。不要在钢筒（就算是空置的）上或附近使用焊接或切断手电筒，因为物品（尽管只剩下一点）会爆发性地着火。
避免接触的条件：无资料
聚合危害：不会进行危险性聚合作用
分解产物：二氧化碳及一氧化碳，各种碳氢化合物
第十一部分 毒理学资料
急性毒性：无资料
亚急性和慢性毒性：--
刺激性：无资料
致敏性：--
致突变性：--
致畸性：--
致癌性：并没有相关资料。因该种物料导致致癌症的可能性不明。此物料并未被列入国际癌症研究机构的全国毒物计划或职业安全卫生署内。
OSHA VPEL 5.000ppm-TWA（皮肤） ACGIH TLV 5.000ppm-TWA（皮肤）
监测方法：无资料
工程控制：提供重要的技术性通分系统以将曝光机会保持在低于TLV 水平
呼吸系统防护：如果工作地点的物品及成分超过标准，在无法完善控制环境时，建议使用符合NIOSH/MAHA规格的呼吸防护具。在特定情况下，OSHA规格同时包括其他NIOSH/MSHA氧气口罩（负压式设计）（请查询卫生安全指导）。应实施技术及行政上的监控以减少曝露的机会。
电子器件中文资料
下边资料的次序是纳米盘上的自动排列，请需要者自己看着找吧。
最后还有07年全年的《读者》E书下载，及几个小游戏。
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Electronics
Computer Cable
Product Construction:
Conductor:
• 28 and 24 AWG fully annealed stranded
tinned copper per ASTM B-33
Insulation:
• Premium-grade, coIor-coded S-R PVC
per UL 1061
• Color Code: See charts below
Shield:
• 100% Flexfoil®aluminum/polyester
with 25% overlap, minimum, foil facing out
• Stranded tinned copper drain wire
(28 AWG only)
• 65% tinned copper braid
Jacket:
• PVC, gray
• Temperature Range: –20˚C to +80˚C
Applications:
• Computers
• Industrial equipment
• Data transmission
• Control circuits
• Suitable for EIA RS-232 applications
• Suggested voltage rating: 300 volts
Features:
• Braid shield provides good flexibility
• Superior shielding where noise rejection
is critical
• Assists system designers in meeting FCC
Docket 20780 demands
Compliances:
• NEC Article 725 Type CL2 - 28 AWG
(UL: 75˚C)
• NEC Article 800 Type CM - 24 AWG
(UL: 75˚C)
• UL Style 2464 (UL: 80°C, 300V)
• CSA CMG (CSA: 60˚C)
• Designed to meet UL 70,000 BTU Vertical
Tray Flame Test
• Passes CSA CMG Flame Test
Packaging:
• Please contact Customer Service for
packaging and color options Multi-Conductor, Foil/Braid Shield
UL 2464, NEC Type CL2 or CM (UL) c(UL), CSA CMG
**B - Capacitance between one conductor and other conductors connected to shield
*Color Code Chart 1. Remaining items Color Code Chart 2
元器件交易网
41
Computer Cable Electronics Multi-Conductor, Foil/Braid Shield
UL 2464, NEC Type CM (UL) c(UL), CSA CMG
Product Construction:
Conductor:
• 22 AWG fully annealed stranded tinned
copper per ASTM B-33
Insulation:
• Premium-grade, coIor-coded S-R PVC
per UL 1061
• Color Code: See chart below
Shield:
• 100% Flexfoil®aluminum/polyester
with 25% overlap, minimum, foil facing out
• 65% tinned copper braid
Jacket:
• PVC, gray
• Temperature Range: –20°C to +80˚C
Applications:
• Computers
• Industrial equipment
• Data transmission
• Control circuits
• Suitable for EIA RS-232 applications
• Suggested voltage rating: 300 volts
Features:
• Braid shield provides good flexibility
• Superior shielding where noise rejection
is critical
• Assists system designers in meeting FCC
Docket 20780 demands
Compliances:
• NEC Article 800 Type CM (UL: 75˚C)
• UL Style 2464 (UL: 80°C, 300V)
• CSA CMG (CSA: 60˚C)
• Designed to meet UL 70,000 BTU Vertical
Tray Flame Test
• Passes CSA CMG Flame Test
Packaging:
• Please contact Customer Service for
packaging and color options
*B - Capacitance between one conductor and other conductors connected to shield 元器件交易网
42。