Automatic Multi Channel Serial IO Interface using FPGA

SICE Annual Conference 2011 September 13-18, 2011, Waseda University, Tokyo, JapanAutomatic Multi Channel Serial I/O Interface using FPGATheerapong Fongjun, Apicit Tantaworrasilp, Phanuphan Kwansud, Pished Bunnun and Chonlada TheerawornNational Electronics and Computer Technology Center 112 Phahon Yothin Rd., Klong 1, Klong Luang, Pathumthani 12120,Thailand (E-mail: theerapong.fongjun@nectec.or.th) Abstract: The Digital input and output signal interface (DIO) is an important component for a machine wanted to be interacted with its environment. Although a main processing unit (MPU) used in the machine has its own DIO channel, for some cases, the machine needs to use more DIO channel than those the MPU can provide. To avoid this problem, a DIO board interfaced directly to the MPU via serial communication is designed. If the MPU connect to multiple DIO boards directly, it will waste sometime to process of communication data, for example processing time is check ready to receive or sending signals. To reduce the unnecessary processing time of the MPU and possibility to have many DIO boards connected, a serial interface unit based on FPGA is developed to help the MPU to communicate with DIO boards. The FPGA unit automatically reads serial signals from each DIO boards and save interpreted data to share registers for MPU to read. The FPGA unit also spontaneously reads registers written by MPU and send registers values to DIO boards automatically. The FPGA unit is XC3S400-4PQ208 chip programmed by VHDL language and has been tested with 3 DIO boards simultaneously. The experiment result shows that the FPGA unit is able to receive and send data between the MPU and DIO boards. Keywords: FPGA, serial communication, digital input and output interface, main processing unit In general, a machine has at least one digital input or output unit to interact with other machines or its environment. Most the time, MPU has a limit number of input and output channel, which is normally less than the machine needs. One way to avoid this problem is to have a DIO board connecting to the MPU via serial communication. Instead of using 32 pins for 32 input channels, only 4 pins for a serial communication are needed for MPU to interface with DIO board. A communication using serial protocol is time consuming. The communication between MPU and DIO boards in signal hand checking before receiving or sending data sometimes consumes a lot of time from the MPU. To avoid these problems, a middleware unit has been implemented on FPGA to handle communication tasks between the MPU and DIO boards. While the FPGA unit communicates with DIO boards via serial interfaces, share registers are used to link between the FPGA unit and MPU. FPGA is widely used to implement a middleware unit. It is implemented to be a SPI master for a microcontroller unit (MCU) to communicate with SPI Slave [1]. By using SPI protocol, it links between DSP and wireless radio [2]. It is used to read 4 channels ADC using 4 different protocols, which are parallel, SPI, I2C and one-wire protocol, and communicate with PC by USB controller [3]. Flexray controller on FPGA for intravehicular communication is implemented [4]. An interface for scale-free network using I2C bus protocol is also implemented on FPGA [5]. In this paper, we introduce a development of FPGA unit, which automatically write and read data from multiple DIO boards via serial communications and the MPU via share registers. Having the FPGA unit, it helps to reduce the burden of a serial communications1. INTRODUCTIONbetween the MPU and DIO boards and also increase a number of DIO boards that the MPU can connect to. We chose to implement the FPGA unit on XC3S400-4PQ208 chip and program it by VHDL language. In this article, Part 2 will explain protocol to communicate with DIO board. Part 3 will introduce implementation of automatic multi channel serial I/O interface on FPGA. Part 4 will shows experiment result and conclusion at the end.In industrial machine, most of MPU pins are used to communicate with many peripheral components. Therefore, there is not much MPU pin left for other use. To control machine with many input-output (I/O) channels, the number of I/O to control I/O device is needed to be sufficiently increased. Instead of directly connecting between MPU pins and I/O pins, DIO boards will communicate with MPU via FPGA by using serial protocol as showed in Fig. 1.2. INCREASING INPUT-OUTPUT CHANNEL BY USING SERIAL INTERFACE- 864 -PR0001/11/0000-0864 ¥400 © 2011 SICEInput and output signal diagrams are shown in Fig 3. To send out data (Data Out), a most significant bit (MSB) is firstly sent. 0-bit to 31-bit are raw data sent from the FPGA unit to DIO board while 32-bit to 35-bit are checking bits (Check Sum) for data correction. To get data (Data In), MSB is received before a low significant bit (LSB). 0-bit to 7-bit are Check Sum, while 8-bit to 39-bit are raw data sent from DIO board to the FPGA unit. Addr-signals in Fig 4. shows sequence of communication in 3 DIO boards.Fig. 1 Structure of Serial Interface between FPGA and DIO board.3. IMPLEMENTATION OF AUTOMATIC MULTI CHANNEL SERIAL I/O INTERFACE ON FPGAFig. 5 Sequential Counter Fig. 2 Serial protocol between FPGA and each DIO board. In Fig. 2 The Dir-signal defines a direction of a communication signal. Dir is 1 as FPGA send data to DIO board. Dir is 0 as FPGA receive data from DIO board. CLK-signal defines a synchronize of communication and works at rising edge. Whilst Dout-signal is used to send data from FPGA to DIO boards, Din-signal is used to receive data from DIO boards to FPGA. Addr-signals represent an address of DIO board that the FPGA unit wants to communicate with. In implementation of automatic multi channel serial I/O interface on FPGA, we generate sequential counter which are “BrdOrderCnt” and “BrdCnt”. The “BrdOrderCnt” is sequential counter of 3 DIO boards, which mean “BrdOrderCnt” counts 0 to 5. The “BrdCnt” is sequential counter of serial state machine, in this propose state of serial in each board have 124 states.WRBrd1[31:0] FetData RDBrd1[31:0] GetData WRBrd2[31:0] FetData RDBrd2[31:0] GetData WRBrd3[31:0] CE [31:0] [31:0] CE [31:0] CE [31:0] [31:0] [31:0]Encode Check Sum[35:0] [39:0]Dir Dout Din CLK AddrDecode Check SumEncode Check Sum[35:0] [39:0]Serial ManagerDecode Check SumFig. 3 Input and Output Signal Diagram.FetData RDBrd3[31:0] GetDataEncode Check Sum[35:0] [39:0] FetData GetDataDecode Check SumBrdOrderCnt[3:0] DeClkFig. 4 Serial protocol between FPGA and 3 DIO boards.Fig. 6 Automatic multi channel serial I/O interface with 3 DIO boards on FPGA.- 865 -BrdCnt FetData Dout Clk0 0 0 01 0 0 0Table 1 Counter sequence of “SerialOut36b” show value 0 to 20 of maximum is 123 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (35) (34) (33) 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 018 0 (32) 019 0 120 0 0BrdCnt GetData Din Clk78 0 (5) 0Table 2 Counter sequence of “SerialIn40b” show value 78 to 97 of maximum is 123 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (4) (3) (2) (1) (0) 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 095 0 096 0 097 0 0In Fig. 6 shows structure of Automatic multi channel serial I/O interface with 3 DIO boards on FPGA. The “WRBrd1” is 32-bit register of output data on board1. We latch “WRBrd1” register by rising edge of “FetData” signal from “Serial Manager” and then send to “Encode Check Sum” for adding check sum to output data so that it becomes 36 bits. The “RDBrd1” is 32-bit register of input data on board1. The “RDBrd1” is 32-bit register coming from “Decode Check Sum”, which is for check sum decoding of 40-bit input data and input data correction. We latch “RDBrd1” register by using two signals. The two signals are rising edge of “GetData” signal from “Serial manager” and check sum correction signal. The check sum correction signal enables the latch.shows in table 1 and Fig. 10. In “SerialIn40b” has 124 states from 0 to 123 for serial input signal generating as shows in table 2 and Fig. 11.Fig. 8 procedure of “SerialOut36b” 1 procedure SerialIn40b 2( 3 signal BrdCnt : in integer range 0 to 127; 4 signal DIN : in std_logic; 5 signal RDBrd1 : out std_logic_vector(39 downto 0); 6 signal GetData : out std_logic; 7 signal Clk : out std_logic 8 ); Fig. 9 procedure of “SerialIn40b”Fig. 10 timing diagram of Table 1Fig. 7 Serial Manager The “Serial Manager” manages sequence of DIO board. In this propose, We have 3 DIO boards. We manage sequence of DIO board by “BrdOrderCnt” as shows in Fig. 7. The “SerialOut36b” and “SerialIn40b” are procedured in VHDL language as shows in Fig. 8 and Fig. 9 respectively. In “SerialOut36b” has 124 states from 0 to 123 for serial output signal generating asFig. 11 timing diagram of table 2- 866 -“CSout” in Fig. 12 is a correction checking of the output data. “CSin” in Fig. 13 is correction checking of the input data. The FPGA unit will accept the input data only if “CSin” is zero.1 CSout(0) := Dout(28) xor Dout(24) xor 2 Dout(20) xor Dout(16) xor 3 Dout(12) xor Dout(8) xor 4 Dout(4) xor Dout(0); 5 CSout(1) := Dout(29) xor Dout(25) xor 6 Dout(21) xor Dout(17) xor 7 Dout(13) xor Dout(9) xor 8 Dout(5) xor Dout(1); 9 CSout(2) := Dout(30) xor Dout(26) xor 10 Dout(22) xor Dout(18) xor 11 Dout(14) xor Dout(10) xor 12 Dout(6) xor Dout(2); 13 CSout(3) := Dout(31) xor Dout(27) xor 14 Dout(23) xor Dout(19) xor 15 Dout(15) xor Dout(11) xor 16 Dout(7) xor Dout(3);Fig.12 “Encode Check Sum” for correction checking of the output data by adding check sum.Fig.13 “Decode Check Sum” for correction checking of the input data by decoding check sum. We use XC3S400-4PQ208 to develop the FPGA unit in our experiment. The FPGA unit is connected between a MPU and 3 DIO boards. The frequency CLK is set 55 kHz for the serial protocol. It take 13.38 milliseconds to receive and send data to all of the 3 DIO boards. The experimental result shows FPGA unit works practically as a middleware to link between the MPU and 3 DIO boards. We have developed the FPGA unit for linking between the MPU and DIO boards. It communicates with DIO boards via the serial protocol. Whereas share registers is used to communicate with the MPU the FPGA unit automatically reads serial signals from each DIO boards and save interpreted data to share registers for MPU to read. The FPGA unit also spontaneously reads registers written by MPU and send registers values to DIO board automatically. Processing time for handling the serial protocol in the MPU is reduced and also the MPU can connect to multiple DIO boards at the same time.4. EXPERIMENTAL RESULT[1] Chen Run, Huang Shi-zhen, Lin Wei and Li Lei, “Design and Implementation of a Reused Interface”, The 1st International Conference on Information Science and Engineering (ICISE2009), pp. 2603-2605, 26-28 Dec 2009. [2] Mohamad Yusri Mohamad Yusof, Devi Prasad and Smruti Santosh Palai, “A System Bus – SPI Bridge Architecture for Wireless Radio”, Proceeding IMCAS'09 Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems, 2009. [3] S. Thanee S. Somkuarnpanit and K. Saetang, “FPGA-Based Multi Protocol Data Acquisition System with High Speed USB Interface”, Proceedings of the International MultiConference of Engineers and Computer Scientists (IMECS 2010), Vol II, March 17-19, 2010 [4] Awani Gaidhane1 M.M .Khanapurkar2 Dr. P. R. Bajaj3, “Design Approach For FPGA Implementation Of Flexray Controller Using VHDL For Intra Vehicular Communication Application”, First International Conference on Emerging Trends in Engineering and Technology (ICETET 2008), pp. 1002-1006, 16-18 July 2008. [5] P.Venkateswaran, Madhumita Mukherjee, Arindam Sanyal, Snehasish Das and R.Nandi, “Design and Implementation of FPGA Based Interface Model for Scale-Free Network using I2C Bus Protocol on Quartus II 6.0”, 4th International Conference on Computers and Devices for Communication (CODEC 2009), pp. 1-4, 14-16 Dec 2009. [6] Hans Kristian Otnes Berge and Philipp H¨afliger, “High-Speed Serial AER on FPGA”, IEEE International Symposium on Circuits and Systems (ISCAS 2007), pp. 857-860, 27-30 May 2007.REFERENCES5. CONCLUSION- 867 -。