FSA4157A中文资料
常用稳压管型
常用稳压管型 The manuscript was revised on the evening of 2021常用稳压型号参数查询DZ是稳压管的电器编号，1N4148就是一个的稳压管，下面是稳压管上的编号对应的稳压值，有些小的稳压管也会在管体上直接标稳压电压，如5V6就是的稳压管。
美标稳压二极管型号：HITACHI(日立)：HITACHI(日立)稳压二极管型号参数稳压HZ3A1 ~HZ3A2 ~HZ3A3 ~HZ3B1 ~HZ3B2 ~HZ3B3 ~线性稳压器件(输入输出电流相等,压降3V以上) 型号稳压(V) 最大输出电流可替代型号79L05 -5V 100mA79L06 -6V 100mA79L08 -8V 100mALM7805 5V 1A L7805,LM340T5LM7806 6V 1A L7806LM7808 8V 1A L7808LM7809 9V 1A L7809LM7812 12V 1A L7812,LM340T12LM7815 15V 1A L7815,LM340T15LM7818 18V 1A L7815LM7824 24V 1A L7824LM7905 -5V 1A L7905LM7906 -6V 1A L7906,KA7906LM7908 -8V 1A L7908LM7909 -9V 1A L7909LM7912 -12V 1A L7912LM7915 -15V 1A L7915LM7918 -18V 1A L7918LM7924 -24V 1A L792478L05 5V 100mA78L06 6V 100mA78L08 8V 100ma78L09 9V 100ma78L12 12V 100ma78L15 15V 100ma78L18 18V 100ma78L24 24V 100ma开关稳压器件(电压转换效率高)型号说明最大输出电流简易开关电源稳压器 1A5V简易开关电源稳压器 1ALM1575T-12 12V简易开关电源稳压器 1ALM1575T-15 15V简易开关电源稳压器 1ALM1575T-ADJ 简易开关电源稳压器(可调~37V) 1A简易开关电源稳压器 1A5V简易开关电源稳压器 1ALM1575HVT-12 12V简易开关电源稳压器 1A LM1575HVT-15 15V简易开关电源稳压器 1A LM1575HVT-ADJ 简易开关电源稳压器(可调~37V) 1A 简易开关电源稳压器 1A5V简易开关电源稳压器 1ALM2575T-12 12V简易开关电源稳压器 1A LM2575T-15 15V简易开关电源稳压器 1A LM2575T-ADJ 简易开关电源稳压器(可调~ 37V) 1A简易开关电源稳压器 1A5V简易开关电源稳压器 1ALM2575HVT-12 12V简易开关电源稳压器 1A LM2575HVT-15 15V简易开关电源稳压器 1A LM2575HVT-ADJ 简易开关电源稳压器(可调~37V) 1A 简易开关电源稳压器 3A简易开关电源稳压器 3ALM2576T-12 12V简易开关电源稳压器 3A LM2576T-15 15V简易开关电源稳压器 3A LM2576T-ADJ 简易开关电源稳压器(可调~37V) 3A简易开关电源稳压器 3A简易开关电源稳压器 3ALM2576HVT-12 12V简易开关电源稳压器 3A LM2576HVT-15 15V简易开关电源稳压器 3A LM2576HVT-ADJ 简易开关电源稳压器(可调~37V) 3A。
ao4407a
ao4407a1. IntroductionThe ao4407a is a power MOSFET designed for high-speed switching applications. This document provides an overview of the ao4407a, discussing its features, specifications, and applications. The document also includes information on how to properly use and handle the device.2. Features•Low on-resistance•High-speed switching capability•Low gate charge•RoHS compliant•Low threshold voltage•Avalanche energy specified•Lead-free, halogen-free, and green device3. SpecificationsHere are the key specifications of the ao4407a:•Drain-Source Voltage (Vds): 30V•Gate-Source Voltage (Vgs): ±20V •Continuous Drain Current (Id): 12A •Continuous Drain Current Pulsed (Idm): 48A •Power Dissipation (Pd): 2W•Drain-Source Breakdown Voltage (Bvdss): 30V •Gate-Threshold Voltage (Vgs(th)): 0.3V - 1.5V •Drain Current - Continuous (Is): 15A•Input Capacitance (Ciss): 850pF•Output Capacitance (Coss): 350pF •Reverse Transfer Capacitance (Crss): 230pF •Total Gate Charge (Qg): 19nC•Gate-Source Charge (Qgs): 4.2nC•Gate-Drain Charge (Qgd): 6.7nC4. Pin ConfigurationThe ao4407a has a compact dual-inline package (SOT-23) with three pins. The pin configuration is as follows: ---------------------| o o || o || o o |---------------------•Pin 1: Drain•Pin 2: Gate•Pin 3: Source5. ApplicationsThe ao4407a is commonly used in various high-speed switching applications, including:•Power management circuits•DC-DC converters•Power supplies•Motor control•LED driver circuits•Battery charging circuits•Audio amplifiers•Computer peripherals6. How to UseTo ensure proper usage and handling of the ao4407a, the following guidelines should be followed:1.Proper grounding: Connect the source pin to theground reference of the circuit.2.Gate voltage: Apply the recommended gate voltagebased on the desired operating conditions.3.Thermal considerations: Adequate cooling measuresshould be taken to prevent overheating of the device. Asuitable heatsink may be required.4.Current and voltage ratings: Ensure that the draincurrent and drain-source voltage do not exceed the device’s maximum specified ratings.5.ESD protection: Take necessary precautions to avoiddamage from electrostatic discharge (ESD) during device handling.7. PrecautionsWhen using the ao4407a, the following precautions should be taken:1.Avoid exceeding the specified maximum ratings.2.Operate within the recommended operatingconditions to ensure reliable performance.3.Do not expose the device to excessive moisture orharsh environmental conditions.4.Take precautions to prevent short circuits betweenthe pins.5.Follow appropriate ESD protection measures duringdevice handling and storage.8. ConclusionThe ao4407a is a high-performance power MOSFET with excellent switching capabilities and low on-resistance. Its compact size and wide range of applications make it a versatile choice for various electronic circuits. By following the guidelines and precautions mentioned in this document, users can fully utilize the potential of the ao4407a and ensure its reliable and efficient operation.。
NLAS4157DFT2G中文资料
NLAS4157SPDT, 1 W R ON SwitchThe NLAS4157 is a low R ON SPDT analog switch. This device is designed for low operating voltage, high current switching of speaker output for cell phone applications. It can switch a balanced stereo o u t p u t. T h e N L A S4157 c a n h a n d l e a b a l a n c e d microphone/speaker/ringtone generator in a monophone mode. The device contains a break−before−make (BBM) feature.Features•Single Supply Operation:1.65 V to 5.5 V V CCFunction Directly from LiON Battery•Tiny SC88 6−Pin Pb−Free Package:Meets JEDEC MO−220 Specifications•R ON Typical = 0.8 W @ V CC = 4.5 V•Low Static Power•This is a Pb−Free DeviceTypical Applications•Cell Phone Speaker/Microphone Switching•Ringtone−Chip/Amplifier Switching•Stereo Balanced (Push−Pull) SwitchingImportant Information•Ringtone−Chip/Amplifier Switching•Continuous Current Rating Through each Switch ±300 mA •Conforms to: JEDEC MO−220, Issue H, Variation VEED−6•Pin for Pin Compatible with FSA4157SC−88 (SOT−363)CASE 419BSee detailed ordering and shipping information in the packagedimensions section on page 8 of this data sheet.ORDERING INFORMATION(Top View)B1GNDB0SV CCAPIN ASSIGNMENTSAN M16MARKING DIAGRAMAN= Specific Device CodeM= Date CodeFigure 1. Input Equivalent Circuit B1S B0APIN DESCRIPTIONTRUTH TABLEH = HIGH Logic Level. L = LOW Logic Level.MAXIMUM RATINGSMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.1.Defined as 10% ON, 90% off duty cycle.RECOMMENDED OPERATING CONDITIONSAnalog Signal Rangeof the voltages on the two (A or B Ports).3.Parameter is characterized but not tested in production.4.D R ON = R ON max − R ON min measured at identical V CC, temperature and voltage levels.5.Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions.6.Guaranteed by Design.7.This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the OnResistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).9.This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the OnResistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).10.Off Isolation = 20 log10 [V A/V Bn].CAPACITANCE (Note 11)AFigure 2. t BBM (Time Break−Before−Make)V CC Figure 3. t ON /t OFFONOFFOutputInputV CC0 VFigure 4. t ON /t OFFInputONOFF0.1 m FV OLV CC V OUT0.1 mChannel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. V ISO , Bandwidth and V ONL are independent of the input signal direction.V ISO = Off Channel Isolation = 20 Log for V IN at 100 kHz V ONL = On Channel Loss = 20 Log for V IN at 100 kHz to 50 MHzBandwidth (BW) = the frequency 3 dB below V ONLV CT = Use V ISO setup and test to all other switch analog input/outputs terminated with 50 WWTransmittedFigure 5. Off Channel Isolation/On Channel Loss (BW)/Crosstalk(On Channel to Off Channel)/V ONL50 WǒV OUTINǓǒV OUTV INǓV CC GNDOutput V INC LFigure 6. Charge Injection: (Q)T H D (%)Figure 7. Cross Talk vs. Frequency@ V CC = 4.5 VFREQUENCY (MHz)0−10−70X T (d B )1.01000100100.1−20−30−40−50−60−80Figure 8. Bandwidth vs. FrequencyFREQUENCY (MHz)B W (d B )0.11000101.00−2−4−6−8−10−12100Figure 11. On−Resistance vs. Input Voltage@ V CC = 4.5 V00.20.40.6R O N (W )V IN (V)0.10.30.50.01.02.03.04.05.0V IN (V)Figure 12. On−Resistance vs. Input Voltage0.810.70.9DEVICE ORDERING INFORMATIONSpecifications Brochure, BRD8011/D.PACKAGE DIMENSIONSSC−88/SC70−6/SOT−363CASE 419B−02ISSUE V*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.419B−01 OBSOLETE, NEW STANDARD 419B−02.DIM MIN NOM MAX MILLIMETERS A 0.800.95 1.10A10.000.050.10A3b 0.100.210.30C 0.100.140.25D 1.80 2.00 2.200.0310.0370.0430.0000.0020.0040.0040.0080.0120.0040.0050.0100.0700.0780.086MIN NOM MAX INCHES0.20 REF 0.008 REFH EE 1.15 1.25 1.35e 0.65 BSC L 0.100.200.302.00 2.10 2.200.0450.0490.0530.026 BSC0.0040.0080.0120.0780.0820.086ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
BCT4157规格书
April, 2008, REV0.0BCT4157Low-Voltage, 4.5Ω SPDT Analog SwitchGeneral DescriptionThe BCT4157 is a high-bandwidth, fast single-pole double-throw (SPDT) CMOS switch. It can be used as an analog switch or as a low-delay bus switch. Specified over a wide operating power supply voltage range, 1.65V to 5.5V, the BCT4157 has a maximum ON resistance of 10.5-ohms at 1.65V, 8-ohms at 2.3V & 4.5-ohms at 4.5V.Break-before-make switching prevents both switches being enabled simultaneously. This eliminates signal disruption during switching.The control input, S, tolerates input drive signals up to 5.5V, independent of supply voltage. BCT4157 is an improved direct replacement for the NC7SB4157ApplicationsCell Phones PDAsPortable InstrumentationBattery Powered Communications Computer PeripheralsConnection DiagramDVFeatures♦CMOS Technology for Bus and Analog Applications♦ Low ON Resistance: 7-ohms at 3.0V ♦ Wide VCC Range: 1.65V to 5.5V ♦ Rail-to-Rail Signal Range♦ Control Input Overvoltage Tolerance: 5.5V min. ♦ Fast Transition Speed: 5.2ns max. at 5V ♦ High Off Isolation: 57dB at 10MHz♦ 54dB (10MHz) Crosstalk Rejection Reduces Signal Distortion♦ Break-Before-Make Switching ♦ High Bandwidth: 300 MHz♦ Extended Industrial Temperature Range: –40°C to 85°C♦ Improved Direct Replacement for NC7SB4157 ♦ Packaging (Pb-free & Green available):Pin DescriptionLogic Function TableLogic Input (S)Function 0 B0 Connected to A 1B1 Connected to AOrdering Code Package Description Temp Range Top MarkingBCT4157EXT 6-pin SC70 .–40°C to +85°C AAX BCT4157ETT 6-pin TDFN 1.45X1.–40°C to +85°CABXNotes: X=monthPin Number Name Description 1 B1 Data Port 2 GND Ground3 B0 Data Port (Normally Closed)4 A Common Output/Data Port5 V CC Positive Power Supply 6SLogic ControlOrdering InformationLow-Voltage,4.5Ω SPDT Analog SwitchABSOLUTE MAXIMUM RATINGS(1)RECOMMENDED OPERATING CONDITIONS (3)Supply Voltage V CC .........................................–0.5V to +7VDC Switch Voltage (V S )(2).…….......…..–0.5V to V CC +0.5V DC Input Voltage (V IN ) (2).…..…….....….......–0.5V to +7.0V DC V CC or Ground Current (I CC /I GND )..................±100mA DC Output Current (V OUT ) .......................................128mA Storage Temperature Range (T STG ) ....... –65°C to +150°C Junction Temperature under Bias (T J ) .......…............ 150°C Junction Lead Temperature (T L )(Soldering, 10 seconds) .................................... 260°C Power Dissipation (P D ) @ +85°C .............................180mW Supply Voltage Operating (V CC )………………1.65V to 5.5V Control Input Voltage (V IN )………………………..0V to V CC Switch Input Voltage (V IN )…………………………0V to V CC Output Voltage (V OUT )…………………………….0V to V CC Operating Temperature (T A )………………...–40°C to +85°C Thermal Resistance (θJA)…………………………..350°C/WNote 1:Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating andoperation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.Note 2:The input and output negative voltage ratings may be exceeded if the input and output diode current ratingsare observed.Note 3:Control input must be held HIGH or LOW; it must not float.DC ELECTRICAL CHARACTERISTICS (TA = - 40°C to +85°C)Parameter Description Test ConditionsSupply Voltage Temp (ºC) Min. Typ Max. Units V IAR Analog Input Signal RangeV CC T A = 25°C & –40°C to 85°C0 V CC VI O = 30mA, V IN = 0V2.9 4.5 R ON I O = –30mA, V IN = 2.4V 4.5V T A = 25°C4 6 I O = –30mA, V IN = 4.5V 6 10 I O = 30mA, V IN = 0V4.5 R ON I O = –30mA, V IN = 2.4V 4.5V T A = –40°C to85°C 6I O = –30mA, V IN = 4.5V10I O = 24mA, V IN = 0V3.3 6.5 R ONI O = –24mA, V IN = 3.0V 3.0V T A = 25°C6.5 13 I O = 24mA, V IN = 0V6.5 R ON ONResistance (4)I O = –24mA, V IN = 3.0V 3.0VT A = –40°C to85°C13I O = 8mA, V IN = 0V3.9 6 R ONI O = –8mA, V IN = 2.3V 2.3V T A = 25°C9 16 I O = 30mA, V IN = 0V6 R ONI O = –30mA, V IN = 2.4V 2.3VT A = –40°C to85°C16I O = 4mA, V IN = 0V5.1 8 R ONI O = –4mA, V IN = 1.65V 1.65V T A = 25°C18 26 I O = 4mA, V IN = 0V8 R ONI O = –4mA, V IN = 1.65V1.65VT A = –40°C to85°C26ΩLow-Voltage,4.5Ω SPDT Analog SwitchDC ELECTRICAL CHARACTERISTICS(continued) (TA = - 40°C to +85°C)Parameter DescriptionTest Conditions Supply Voltage Temp (ºC) Min Typ Max. UnitsON ResistanceI A = –30mA, V Bn = 3.15V 4.5V0.15 ∆R ON Match Between I A = –24mA, V Bn = 2.1V 3.0V T A = 25°C0.2 Channels (4,5,6) I A = –8mA, V Bn = 1.6V 2.3V 0.3 I A = –4mA, V Bn = 1.15V 1.65V 0.3 ΩI A = –30mA, 0 ≤V Bn ≤V CC 5.0V6R ONF ONResistance (4,5,7) Flatness I A = –24mA, 0 ≤V Bn ≤V CC 3.3V T A = 25°C12I A = –8mA, 0 ≤V Bn ≤V CC 2.5V 22I A = –4mA, 0 ≤V Bn ≤V CC1.8V90 ΩV CC = 1.65V to 1.95V 0.75V CCV IHInput High VoltageLogic High LevelV CC = 2.3V to 5.5V T A = 25°C & –40°C to85°C 0.7V CCV V CC = 1.65V to 1.95V 0.25V CCV IL Input LowVoltageLogic Low LevelV CC = 2.3V to 5.5V0.25V CC VT A = 25°C ±0.1Input Leakage Current0 ≤V IN ≤5.5VV CC = 0V to5.5VT A = –40°C to 85°C ±1.0 T A = 25°C ±0.1I OFFOFF State Leakage Current0 ≤VIN ≤5.5VV CC = 1.65V to 5.5VT A = –40°C to 85°C ±10 T A = 25°C1 I CCQuiescentSupply CurrentAll channels ON or OFF, V IN = V CC or GND, I OUT = 0V CC = 5.5VT A = –40°C to 85°C10µANote 4: Measured by voltage drop between A and B pins at the indicated current through the device. ON resistance isdetermined by the lower of the voltages on two ports (A or B)Note 5: Parameter is characterized but not tested in production.Note 6: DR ON = R ON max – R ON min. measured at identical V CC , temperature and voltage levels.Note 7: Flatness is defined as difference between maximum and minimum value of ON resistance over the specifiedrange of conditions..Note 8: Guaranteed by design.CAPACITANCE (12)Parameter DescriptionTestConditions Supply VoltageTemp (ºC)Min. Typ Max. Units C IN Control Input2.3 C IO-B For B Port,Switch OFFV CC = 5.0VT A = 25°C6.5 C IOA-ON For A Port, Switch ONf= 1 MHz (12)18.5pFLow-Voltage,4.5Ω SPDT Analog SwitchSWITCH AND AC CHARACTERISTICSParameter DescriptionTest ConditionsSupply Voltage Temp (ºC)Min. Typ Max. Units V CC = 2.3V to 2.7V1.2V CC = 3.0V to 3.6V 0.8 t PLH t PHLPropagation Delay: A to Bn See test circuitdiagrams 1 and 2. V I Open (10)V CC = 4.5V to 5.5VT A = 25°C & –40 to 85°C0.3V CC = 1.65V to 1.95V7 23 t PZL V CC = 2.3V to 2.7V T A = 25°C 3.5 13 t PZH V CC = 3.0V to 3.6V 2.5 6.9 OutputEnable Turn ON Time: A to Bndiagrams 1 & 2. Seetest circuitV I = 2V CC for T PZL ,V I = 0V for t PZHV CC = 4.5V to 5.5V1.7 5.2 V CC =2.5V24 t PZL V CC = 3.3V 14 t PZH V CC = 3.0V to 3.6V 7.6 OUTPUTENABLE TURN NOTIME: A TO BNSee test circuit diagrams 1 and 2. V I = 2V CC for T PZL , V I = 0V for t PZHV CC = 4.5V to 5.5VT A = 25°C & –40 to 85°C 5.7 V CC = 1.65V to 1.95V3 12.5 t PLZ V CC = 2.3V to 2.7V T A = 25°C 2 7 t PHZ V CC = 3.0V to 3.6V 1.5 5 Output Disable TurnOFF Time: A to BnSee test circuit diagrams 1 and 2. V I = 2V CC for T PZL , V I = 0V for t PZHV CC = 4.5V to 5.5V0.8 3.5 V CC = 2.5V13 t PLZ V CC = 3.3V 7.5 t PHZ V CC = 3.0V to 3.6V 5.3 Output Disable TurnOFF Time: A to Bn See test circuit diagrams 1 and 2. V I = 2V CC for T PZL , V I = 0V for t PZH V CC = 4.5V to 5.5V T A = –40 to 85°C 3.8V CC = 2.5V0.5 V CC = 3.3V 0.5t BM Break BeforeMake Time See test circuit diagram 9.(9) V CC = 3.0V to 3.6V T A = 25°C & –40 to 85°C 0.5VCC = 4.5V to 5.5V0.5 nsV CC = 5.0V7QCharge InjectionC L = 0.1nF, V GEN = 0V, R GEN = 0Ω. See test circuit 4.VCC = 3.3VT A = 25°C3pCOIRR Off IsolationR L = 50Ω, V GEN = 0V,R GEN = 0Ω. See test circuit 5. (11)V CC = 1.65V to 5.5V T A = 25°C–57X TALKCrosstalk Isolation See test circuit 6.V CC = 1.65V to 5.5VT A = 25°C–54dB f 3dB–3dBBandwidthSee test circuit 9V CC = 1.65V to 5.5VT A = 25°C300MHzNote 6: Guaranteed by designNote 7: Guaranteed by design but not production tested. The device contributes no other propagation delay other thanthe RC delay of the switch ON resistance and the 50pF load capacitance, whne driven by an ideal voltage source with zero output impedance.Low-Voltage,4.5Ω SPDT Analog SwitchTEST CIRCUITS AND TIMING DIAGRAMSFigure 1. AC Test CircuitFigure 2. AC WaveformsFigure 3. Break Before Make Interval TimingLow-Voltage,4.5Ω SPDT Analog SwitchTEST CIRCUITS AND TIMING DIAGRAMS(continued)Figure 4. Charge Injection Test Figure 5. Off Isolation Figure 6. CrosstalkFigure 7. Channel Off CapacitanceFigure 8. Channel On CapacitanceLow-Voltage,4.5Ω SPDT Analog Switch TEST CIRCUITS AND TIMING DIAGRAMS(continued)Figure 9. BandwidthLow-Voltage,4.5Ω SPDT Analog SwitchPackaging Mechanical: 6-Pin SC70 (C)Packaging Mechanical: 6-Pin TDFN。
ADF4157BCPZ-RL71资料
High Resolution 6 GHz Fractional-NFrequency SynthesizerADF4157Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, N orwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.FEATURESRF bandwidth to 6 GHz25-bit fixed modulus allows subhertz frequency resolution 2.7 V to 3.3 V power supplySeparate V P allows extended tuning voltage Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down modePin compatible with the following frequency synthesizers: ADF4110/ADF4111/ADF4112/ADF4113/ ADF4106/ADF4153/ADF4154/ADF4156 Cycle slip reduction for faster lock timesAPPLICATIONSSatellite communications terminals, radar equipment Instrumentation equipment Personal mobile radio (PMR) Base stations for mobile radio Wireless handsetsGENERAL DESCRIPTIONThe ADF4157 is a 6 GHz fractional-N frequency synthesizer with a 25-bit fixed modulus, allowing subhertz frequency resolution at 6 GHz. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT and FRAC registers define an overallN divider, N = INT + (FRAC/225). The ADF4157 features cycle slip reduction circuitry, which leads to faster lock times without the need for modifications to the loop filter.Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.FUNCTIONAL BLOCK DIAGRAMDATA LECLK REF ININ A IN BMUXOUT05874-001Figure 1.ADF4157Rev. 0 | Page 2 of 20TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Timing Specifications..................................................................4 Absolute Maximum Ratings............................................................5 Thermal Resistance......................................................................5 ESD Caution..................................................................................5 Pin Configurations and Function Descriptions...........................6 Typical Performance Characteristics.............................................7 Circuit Description...........................................................................8 Reference Input Section...............................................................8 RF Input Stage...............................................................................8 RF INT Divider.............................................................................8 25-Bit Fixed Modulus..................................................................8 INT, FRAC, and R Relationship.................................................8 RF R Counter................................................................................8 Phase Frequency Detector (PFD) and Charge Pump..............9 MUXOUT and LOCK Detect.. (9)Input Shift Registers......................................................................9 Program Modes.............................................................................9 Register Maps..................................................................................10 FRAC/INT Register (R0) Map..................................................11 LSB FRAC Register (R1) Map..................................................12 R Divider Register (R2) Map....................................................13 Function Register (R3) Map.....................................................15 Test Register (R4) Map..............................................................16 Applications Information..............................................................17 Initialization Sequence..............................................................17 RF Synthesizer: A Worked Example........................................17 Reference Doubler and Reference Divider.............................17 Cycle Slip Reduction for Faster Lock Times...........................17 Spur Mechanisms.......................................................................18 Low Frequency Applications....................................................18 Filter Design—ADIsimPLL.......................................................18 Interfacing...................................................................................18 PCB Design Guidelines for the Chip Scale Package..............18 Outline Dimensions.......................................................................19 Ordering Guide.. (19)REVISION HISTORY7/07—Revision 0: Initial RevisionADF4157Rev. 0 | Page 3 of 20SPECIFICATIONSAV DD = DV DD = 2.7 V to 3.3 V; V P = AV DD to 5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwise noted; dBm referred to 50 Ω. Table 1.Parameter B Version 1Unit Test Conditions/Comments RF CHARACTERISTICS (3 V)RF Input Frequency (RF IN ) 0.5/6.0 G Hz min/max−10 dBm/0 dBm min/max. For lower frequencies, ensure slew rate (SR) > 400 V/μs.REFERENCE CHARACTERISTICS REF IN Input Frequency 10/300 MHz min/max For f < 10 MHz, ensure slew rate > 50 V/μs. REF IN Input Sensitivity 0.4/AV DD V p-p min/max For 10 MHz < REF IN < 250 MHz. Biased at AV DD /22. 0.7/AV DD V p-p min/max For 250 MHz < REF IN < 300 MHz. Biased at AV DD /22. REF IN Input Capacitance 10 pF max REF IN Input Current ±100 μA max PHASE DETECTORPhase Detector Frequency 332 MHz max CHARGE PUMP I CP Sink/Source Programmable. High Value 5 mA typ With R SET = 5.1 kΩ. Low Value 312.5 μA typ Absolute Accuracy 2.5 % typ With R SET = 5.1 kΩ. R SET Range 2.7/10 kΩ min/maxI CP Three-State Leakage Current 1 nA typ Sink and source current.Matching 2 % typ 0.5 V < V CP < V P – 0.5. I CP vs. V CP 2 % typ 0.5 V < V CP < V P – 0.5. I CP vs. Temperature 2 % typ V CP = V P /2. LOGIC INPUTS V INH , Input High Voltage 1.4 V min V INL , Input Low Voltage 0.6 V max I INH /I INL , Input Current ±1 μA max C IN , Input Capacitance 10 pF max LOGIC OUTPUTS V OH , Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V. V OH , Output High Voltage VDD – 0.4 V min CMOS output chosen. V OL , Output Low Voltage 0.4 V max I OL = 500 μA. POWER SUPPLIES AV DD 2.7/3.3 V min/V max DV DD AV DD V P AV DD /5.5 V min/V max I DD 29 mA max 23 mA typical. Low Power Sleep Mode 10 μA typ NOISE CHARACTERISTICSPhase Noise Figure of Merit 4−207 dBc/Hz typADF4157 Phase Noise Floor 5−137 dBc/Hz typ @ 10 MHz PFD frequency. −133 dBc/Hz typ @ 25 MHz PFD frequency.Phase Noise Performance 6@ VCO output.5800 MHz Output 7−87 dBc/Hz typ @ 2 kHz offset, 25 MHz PFD frequency.1 Operating temperature of B version is −40°C to +85°C. 2AC-coupling ensures AV DD /2 bias. 3Guaranteed by design. Sample tested to ensure compliance. 4This figure can be used to calculate phase noise for any application. Use the formula –207 + 10log(f PFD ) + 20logN to calculate in-band phase noise performance as seen at the VCO output. 5The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 6The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system. 7f REFIN = 100 MHz; f PFD = 25 MHz; offset frequency = 2 kHz; RF OUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.ADF4157Rev. 0 | Page 4 of 20TIMING SPECIFICATIONSAV DD = DV DD = 2.7 V to 3.3 V; V P = AV DD to 5.5 V; AGND = DGND = 0 V; T A = T MIN to T MAX , unless otherwise noted; dBm referred to 50 Ω. Table 2.Parameter Limit at T MIN to T MAX (B Version) UnitTest Conditions/Comments t 1 20 ns min LE setup timet 2 10 ns min DATA to CLOCK setup time t 3 10 ns min DATA to CLOCK hold time t 4 25 ns min CLOCK high duration t 5 25 ns min CLOCK low duration t 610 ns min CLOCK to LE setup time t 7 20ns minLE pulse widthCLKDATALELE05874-002Figure 2. Timing DiagramADF4157Rev. 0 | Page 5 of 20ABSOLUTE MAXIMUM RATINGST A = 25°C, GND = AGND = DGND = 0 V , V DD = AV DD = DV DD , unless otherwise noted. THERMAL RESISTANCETable 3.Parameter Rating θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. V DD to GND −0.3 V to +4 V V DD to V DD −0.3 V to +0.3 VTable 4. Thermal Resistance V P to GND −0.3 V to +5.8 VV P to V DD −0.3 V to +5.8 VPackage Type θJA Unit Digital I/O Voltage to GND −0.3 V to V DD + 0.3 V TSSOP 112 °C/W Analog I/O Voltage to GND −0.3 V to V DD + 0.3 V LFCSP (Paddle Soldered) 30.4 °C/W REF IN , RF IN to GND −0.3 V to V DD + 0.3 V ESD CAUTION Operating Temperature Range Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C Reflow SolderingPeak Temperature 260°CTime at Peak Temperature 40 secStresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ADF4157Rev. 0 | Page 6 of 20PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSCP CPGND AGND AV DD RF IN A RF IN B R SET DV DD MUXOUT LE CE REF INDGNDCLK DATA V P 05874-0031CPGND 2AGND 3AGND 4RF IN B 5RF IN A13DATA 14LE 15MUXOUT 12CLK 11CE6A V D D 7A V D D 8R E F I N 10D G N D 9D G N D 18V P19R S E T20C P 17D V D D 16D V D D05874-004Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin ConfigurationADF4157Rev. 0 | Page 7 of 20TYPICAL PERFORMANCE CHARACTERISTICSPFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, I CP = 313 μA, phase noise measurements taken on the Agilent E5052A phase noise system.10–409FREQUENCY (GHz)P O W E R (d B m )50–5–10–15–20–25–30–351234567805874-0166.005.65–100900TIME (µs)F R E Q U E N C Y (GH z )5.955.905.855.805.755.700100200300400500600700800Figure 5. RF Input SensitivityFigure 8. Lock Time for 200 MHz Jump from 5705 MHz to 5905 MHzwith CSR On and Off–400500 5.655.605.955.905.855.805.755.70–100900TIME (µs)F R E Q U E N C Y (GH z )FREQUENCY (MHz)P O W E R (d B m )100200300400V DD = 3V –5–10–15–20–25–30–3505874-0170100200300400500600700800.0Figure 9. Lock Time for 200 MHz Jump from 5905 MHz to 5705 MHzwith CSR On and OffFigure 6. Reference Input Sensitivity1k10MFREQUENCY (Hz)P H A S E N O I S E (d B c /H z )10k 100k1M 05874-0186–60505874-021V CP (V)I C P (m A )42–2–40.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5Figure 10. Charge Pump Output Characteristics, Pump Up and Pump DownFigure 7. Phase Noise and Spurs(Note that the 250 kHz spur is an integer boundary spur; see the SpurMechanisms section for more information.)ADF4157Rev. 0 | Page 8 of 20CIRCUIT DESCRIPTIONINT, FRAC, AND R RELATIONSHIPREFERENCE INPUT SECTIONThe INT and FRAC values, in conjunction with the R counter, make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF IN pin on power-down.RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RF OUT ) equation isRF OUT = f PFD × (INT + (FRAC/225)) (1)POWER-DOWN 05874-005where:RF OUT is the output frequency of the external voltage controlled oscillator (VCO).INT is the preset divide ratio of the binary 12-bit counter (23 to 4095).FRAC is the numerator of the fractional division (0 to 225 − 1).Figure 11. Reference Input Stagef PFD = REF IN × [(1 + D )/(R × (1+T))] (2)RF INPUT STAGEwhere:REF IN is the reference input frequency. D is the REF IN doubler bit.R is the preset divide ratio of the binary 5-bit programmable reference counter (1 to 32).T is the REF IN divide-by-2 bit (0 or 1).The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler.RF IN BRF INA05874-006RF R COUNTERThe 5-bit RF R counter allows the input reference frequency (REF IN ) to be divided down to produce the reference clock to the PFD. Division ratios from 1 to 32 are allowed.05874-007Figure 12. RF Input StageRF INT DIVIDERFigure 13. RF N DividerThe RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed.25-BIT FIXED MODULUSThe ADF4157 has a 25-bit fixed modulus. This allows output frequencies to be spaced with a resolution off RES = f PFD /225where f PFD is the frequency of the phase frequency detector (PFD). For example, with a PFD frequency of 10 MHz, frequency steps of 0.298 Hz are possible.ADF4157Rev. 0 | Page 9 of 20PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMPINPUT SHIFT REGISTERSThe ADF4157 digital section includes a 5-bit RF R counter, a 12-bit RF N counter, and a 25-bit FRAC counter. Data isclocked into the 32-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of five latches on the rising edge of LE. The destination latch is determined by the state of the three control bits (C3, C2, and C1) in the shift register. These are the three LSBs, DB2, DB1, and DB0, as shown in The PFD takes inputs from the R counter and the N counter and produces an output proportional to the phase andfrequency difference between them. Figure 14 is a simplified schematic of the phase frequency detector. The PFD includes a fixed delay element that sets the width of the antibacklash pulse, which is typically 3 ns. This pulse ensures that there is no dead zone in the PFD transfer function and gives a consistent reference spur level.Figure 2. The truth table for these bits is shown in Table 6. Figure 16 shows a summary of how the latches are programmed.CP05874-008PROGRAM MODESTable 6 and Figure 16 through Figure 21 show how to set up the program modes in the ADF4157.Several settings in the ADF4157 are double-buffered. Theseinclude the LSB FRAC value, R counter value, reference doubler, and current setting. This means that two events have to occur before the part uses a new value of any of the double-buffered settings. First, the new value is latched into the device bywriting to the appropriate register. Second, a new write must be performed on Register R0.Figure 14. PFD Simplified SchematicFor example, updating the fractional value can involve a write to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should be written to first, followed by the write to R0. The frequency change begins after the write to R0. Double buffering ensures that the bits written to in R1 do not take effect until after the write to R0.MUXOUT AND LOCK DETECTThe output multiplexer on the ADF4157 allows the user toaccess various internal points on the chip. The state ofMUXOUT is controlled by M4, M3, M2, and M1 (see Figure 17). Figure 15 shows the MUXOUT section in block diagram form.Table 6. C3, C2, and C1 Truth TableControl Bits05874-009ANALOG LOCK DETECT DV DD THREE-STATE OUTPUTN DIVIDER OUTPUT DGNDR DIVIDER OUTPUT DIGITAL LOCK DETECT SERIAL DATA OUTPUT CLK DIVIDER OUTPUTR DIVIDER/2N DIVIDER/2C3 C2 C1 Register 0 0 0 Register R0 0 0 1 Register R1 0 1 0 Register R2 0 1 1 Register R3 1 0 0 Register R4Figure 15. MUXOUT SchematicADF4157Rev. 0 | Page 10 of 20REGISTER MAPSFRAC/INT REGISTER (R0)FUNCTION REGISTER (R3)NOTES1. DBB = DOUBLE BUFFERED BIT(S).05874-010Figure 16. Register SummaryADF4157FRAC/INT REGISTER (R0) MAPWith R0[2, 1, 0] set to [0, 0, 0], the on-chip Frac/Int register is programmed as shown in Figure 17.Reserved BitThe reserved bit should be set to 0 for normal operation.MUXOUTThe on-chip multiplexer is controlled by DB[30], DB[29], DB[28] and DB[27] on the ADF4157. See Figure 17 for the truth table.12-Bit INT ValueThese twelve bits control what is loaded as the INT value. This is used to determine the overall feedback division factor. It isused in Equation 1. See the INT, FRAC, and R Relationship section for more information.12-Bit MSB FRAC ValueThese twelve bits, along with Bits DB[27:15] in the LSB FRACregister (R1), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determines the overall feedback division factor. It is also used in Equation 1. These 12 bits are the most significant bits (MSB) of the 25-bit FRAC value, and Bits DB[27:15] in the LSB FRAC register (R1) are the least significant bits (LSB). See the RF Synthesizer: A Worked Example section for more information.Figure 17. FRAC/INT Register (R0) MapADF4157LSB FRAC REGISTER (R1) MAPWith R1[2, 1, 0] set to [0, 0, 1], the on-chip LSB FRAC register is programmed as shown in Figure 18.13-Bit LSB FRAC ValueThese thirteen bits, along with Bits DB[14:3] in the INT/FRAC register (R0), control what is loaded as the FRAC value into the fractional interpolator. This is part of what determinesthe overall feedback division factor. It is also used in Equation 1. These 13 bits are the least significant bits of the 25-bit FRACvalue, and Bits DB[14:3] in the INT/FRAC register are the most significant bits. See the RF Synthesizer: A Worked Example section for more information.Reserved BitsAll reserved bits should be set to 0 for normal operation.*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.05874-012Figure 18. LSB FRAC Register (R1) MapADF4157 R DIVIDER REGISTER (R2) MAPWith R1[2, 1, 0] set to [0, 1, 0], the on-chip R divider register is programmed as shown in Figure 19.CSR EnableSetting this bit to 1 enables cycle slip reduction. This is a method for improving lock times. Note that the signal at the PFD must have a 50% duty cycle in order for cycle slip reduction to work. In addition, the charge pump current setting must be set to a minimum. See the Cycle Slip Reduction for Faster Lock Times section for more information.Note also that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is set to negative.Charge Pump Current SettingDB[27], DB[26], DB[25], and DB[24] set the charge pump current setting. This should be set to the charge pump current that the loop filter is designed with (see Figure 19). Prescaler (P/P + 1)The dual-modulus prescaler (P/P + 1), along with the INT, FRAC, and MOD counters, determines the overall division ratio from the RF IN to the PFD input.Operating at CML levels, it takes the clock from the RF input stage and divides it down for the counters. It is based ona synchronous 4/5 core. When set to 4/5, the maximum RF frequency allowed is 3 GHz. Therefore, when operatingthe ADF4157 above 3 GHz, the prescaler must be set to 8/9. The prescaler limits the INT value.With P = 4/5, N MIN = 23.With P = 8/9, N MIN = 75.RDIV2Setting this bit to 1 inserts a divide-by-2 toggle flip flop between the R counter and the PFD. This can be used to provide a 50% duty cycle signal at the PFD for use with cycle slip reduction. Reference DoublerSetting DB[20] to 0 feeds the REF IN signal directly to the 5-bit RF R counter, disabling the doubler. Setting this bit to 1 multiplies the REF IN frequency by a factor of 2 before feeding into the 5-bit R counter. When the doubler is disabled,the REF IN falling edge is the active edge at the PFD input to the fractional synthesizer. When the doubler is enabled, both the rising edge and falling edge of REF IN become active edges at the PFD input.The maximum allowed REF IN frequency when the doubler is enabled is 30 MHz.5-Bit R CounterThe 5-bit R counter allows the input reference frequency (REF IN) to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from1 to 32 are allowed.Reserved BitsAll reserved bits should be set to 0 for normal operation.ADF4157Figure 19. R Divider Register (R2) MapADF4157 FUNCTION REGISTER (R3) MAPWith R2[2, 1, 0] set to [0, 1, 1], the on-chip function register is programmed as shown in Figure 20.Reserved BitsAll reserved bits should be set to 0 for normal operation.Σ-Δ ResetFor most applications, DB14 should be set to 0. When DB14 is set to 0, the Σ-Δ modulator is reset on each write to Register 0. If it is not required that the Σ-Δ modulator be reset on each Register 0 write, this bit should be set to 1.Lock Detect Precision (LDP)When DB[7] is programmed to 0, 24 consecutive PFD cycles of 15 ns must occur before digital lock detect is set. When this bit is programmed to 1, 40 consecutive reference cycles of 15 ns must occur before digital lock detect is set.Phase Detector PolarityDB[6] in the ADF4157 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0.RF Power-DownDB[5] on the ADF4157 provides the programmable power-down mode. Setting this bit to 1 performs a power-down. Setting this bit to 0 returns the synthesizer to normal operation. While in software power-down mode, the part retains all information in its registers. Only when supplies are removed are the register contents lost.When a power-down is activated, the following events occur:1. All active dc current paths are removed.2. The synthesizer counters are forced to their load stateconditions.3. The charge pump is forced into three-state mode.4. The digital lock detect circuitry is reset.5. The RF IN input is debiased.6. The input register remains active and capable of loadingand latching data.RF Charge Pump Three-StateDB[4] puts the charge pump into three-state mode when programmed to 1. It should be set to 0 for normal operation. RF Counter ResetDB[3] is the RF counter reset bit for the ADF4157. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0.Figure 20. Function Register (R3) MapADF4157TEST REGISTER (R4) MAPReserved BitsWith R3[2, 1, 0] set to [1, 0, 0], the on-chip test register (R4) is programmed as shown in Figure 21.DB[31:3] should be set to 0 in this register.05874-015Figure 21. Test Register (R4) MapADF4157APPLICATIONS INFORMATIONINITIALIZATION SEQUENCEAfter powering up the part, this programming sequence must be followed: 1. Test Register (R4)2. Function Register (R3)3. R Divider Register (R2)4. LSB FRAC Register (R1)5.FRAC/INT Register (R0)RF SYNTHESIZER: A WORKED EXAMPLEThe following equation governs how the synthesizer should be programmed:RF OUT = [N + (FRAC/225)] × [f PFD ] (3) where:RF OUT is the RF frequency output.N is the integer division factor.FRAC is the fractionality.f PFD = REF IN × [(1 + D )/(R × (1 + T))] (4)where:REF IN is the reference frequency input.D is the RF REF IN doubler bit.R is the RF reference division factor.T is the reference divide-by-2 bit (0 or 1).For example, in a system where a 5.8002 GHz RF frequencyoutput (RF OUT ) is required and a 10 MHz reference frequencyinput (REF IN ) is available, the frequency resolution isf RES = REF IN /225f RES = 10 MHz/225 = 0.298 Hz From Equation 4,f PFD = [10 MHz × (1 + 0)/1] = 10 MHz5.8002 GHz = 10 MHz × (N + FRAC/225) Calculating N and FRAC values,N = int (RF OUT /f PFD ) = 580 FRAC = F MSB × 213 + F LSBF MSB = int (((RF OUT /f PFD ) − N) × 212) = 81F LSB = int (((((RF OUT /f PFD ) − N) × 212) − F MSB ) × 213) = 7537 where:F MSB is the 12-bit MSB FRAC value in Register R0. F LSB is the 13-bit LSB FRAC value in Register R1. int () makes an integer of the argument in brackets.REFERENCE DOUBLER AND REFERENCE DIVIDERThe reference doubler on-chip allows the input reference signal to be doubled. This is useful for increasing the PFD comparison frequency. Making the PFD frequency higher improves the noise performance of the system. Doubling the PFD frequencyusually improves noise performance by 3 dB. It is important tonote that the PFD cannot be operated above 32 MHz due to a limitation in the speed of the Σ-Δ circuit of the N divider.CYCLE SLIP REDUCTION FOR FASTER LOCK TIMESIn fast-locking applications, a wide loop filter bandwidth is required for fast frequency acquisition, resulting in increased integrated phase noise and reduced spur attenuation. Using cycle slip reduction, the loop bandwidth can be kept narrow to reduce integrated phase noise and attenuate spurs while still realizing fast lock times.Cycle SlipsCycle slips occur in integer-N/fractional-N synthesizers when the loop bandwidth is narrow compared to the PFD frequency.The phase error at the PFD inputs accumulates too fast for the PLLto correct, and the charge pump temporarily pumps in the wrong direction, slowing down the lock time dramatically. The ADF4157 contains a cycle slip reduction circuit to extend the linear range of the PFD, allowing faster lock times without loop filter changes. When the ADF4157 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. This outputs a constantcurrent to the loop filter or removes a constant current from theloop filter (depending on whether the VCO tuning voltage needsto increase or decrease to acquire the new frequency). The effect isthat the linear range of the PFD is increased. Stability is main-tained because the current is constant and is not a pulsed current.If the phase error increases again to a point where another cycleslip is likely, the ADF4157 turns on another charge pump cell.This continues until the ADF4157 detects that the VCOfrequency has gone past the desired frequency. It then begins to turn off the extra charge pump cells one by one until they are allturned off and the frequency is settled. Up to seven extra charge pump cells can be turned on. In most applications, it is enough to eliminate cycle slips altogether, giving much faster lock times.Setting Bit DB28 in the R Divider register (R2) to 1 enables cycle slip reduction. Note that a 45% to 55% duty cycle is needed on the signal at the PFD in order for CSR to operate correctly. The reference divide-by-2 flip-flop can help toprovide a 50% duty cycle at the PFD. For example, if a 100 MHz reference frequency is available, and the user wants to run the PFD at 10 MHz, setting the R divide factor to 10 results in a 10 MHz PFD signal that is not 50% duty cycle. By setting the R divide factor to 5 and enabling the reference divide-by-2 bit, a 50% duty cycle 10 MHz signal can be achieved.Note that the cycle slip reduction feature can only be operated when the phase detector polarity setting is positive (DB6 in Register R3). It cannot be used if the phase detector polarity is set to negative.。
FSA5157中文资料
November 2005Revised November 2005FSA5157 0.4:Low Voltage SPDT Analog Switch (Preliminary) FSA51570.4: Low Voltage SPDT Analog Switch (Preliminary)General DescriptionThe FSA5157 is a low ON Resistance, low power Single PoleDouble Throw (SPDT) analog switch. This product has beendesigned for switching audio signals in applications such as cellphones and portable media players. The ultra-low 0.4 Ohmimpedance, sub 1P A current consumption, and 1.65V to 4.3Voperating voltage range makes this product ideal for batterypower applications. The FSA5157 also features bi-directionaloperation and make-before-break functionality. This device isfully specified for operation at 1.8V, 2.5V and 3.3V.A growing number of applications require the voltage applied tothe select input to be lower then the V CC applied. Under thiscondition, most switches would typically consume over 100P Aof current. This would be an unacceptable level for battery pow-ered applications. The FSA5157 has been designed to minimizecurrent consumption under this condition. The I CCT is specifiedfor 12P A under a worse case condition of V CC = 4.3V andV IN=1.8V.FeaturesO Typical 0.4: On Resistance (R ON) for 2.7V supplyO FSA5157 features less than 12P A I CCT currentwhen S input is lower than V CCO0.25: maximum R ON flatness for 2.7V supplyO1.0mm x 1.45mm 6-Lead Pb-Free MicroPak¥ packageO Broad V CC operating range: 1.65V to 4.3VO Low THD (0.02% typical for 32: load)O High current handling capability(350mA continuous current under 3.3V supply)O Control logic is 1.8V CMOS logic compatibleApplicationsO Cellular phoneO PDAO Portable Media PlayerOrdering Code:Pb-Free package per JEDEC J-STD-020B.Applications DiagramMicroPak¥ is a trademark of Fairchild Semiconductor Corporation.ProductPackage Description Supplied As Order Package CodeNumber Number Top MarkFSA5157P6X MAA06A A576-Lead SC70, EIAJ SC88, 1.25mm Wide3K Units on Tape and ReelFSA5157P6X_NL MAA06A A57Pb-Free 6-Lead SC70, EIAJ SC88,1.25mm Wide3K Units on Tape and Reel FSA5157L6X MAC06A FT Pb-Free 6-Lead MicroPak, 1.0mm Wide5K Units on Tape and Reel© 2005 Fairchild Semiconductor Corporation 2F S A 5157Analog SymbolsPin Assignment for SC70(Top View)Pin Assignment for MicroPak(Top Through View)Truth TableH = HIGH Logic Level L = LOW Logic LevelPin DescriptionsControl Input(s)FunctionL B 0 Connected to A HB 1 Connected to APin NamesFunctionA, B 0, B 1Data Ports SControl InputFSA5157Absolute Maximum Ratings (Note 1)Recommended Operating ConditionsNote 1: The “Absolute Maximum Ratings” are those values beyond which the safetyof the device cannot be guaranteed. The device should not be operated at these lim-its. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Condi-tions” table will define the conditions for actual device operation.Note 2: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed.Note 3: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical Characteristics (All typical values are @ 25q C unless otherwise specified)Supply Voltage (V CC ) 0.5V to 4.6V Switch Voltage (V S ) (Note 2) 0.5V to V CC 3.0VInput Voltage (V IN ) (Note 2) 0.5V to 4.6VInput Diode Current 50 mA Switch Current350 mAPeak Switch Current (Pulsed at 1 ms duration, 10% Duty Cycle)500 mAStorage Temperature Range (T STG ) 65q C to 150q CMaximum Junction Temperature (T J ) 150q C Lead Temperature (T L )Soldering, 10 seconds 260q CESDHuman Body Model8000V Supply Voltage (V CC )1.65V to 4.3VControl Input Voltage (V IN ) (Note 3)0V to V CCSwitch Input Voltage (V IN )0V to V CCOperating Temperature (T A )40q C to 85q CSymbol ParameterV CC T A = 25q CT A = 40q C to 85q C UnitsConditions(V)MinTypMaxMin MaxV IHInput Voltage High3.6 to4.3 1.4V2.7 to3.6 1.32.3 to 2.7 1.11.65 to 1.950.9V ILInput Voltage Low3.6 to4.30.7V 2.7 to 3.60.52.3 to 2.70.41.65 to 1.950.4I IN Control Input Leakage 1.65 to 4.3 0.50.5P A V IN = 0V to V CC I NO(OFF),OFF-Leakage Current 1.95 to 4.3-10.010.050.050.0nAA = 0.3V, V CC 0.3VI NC(OFF)of Port B 0 and B 1B 0 or B 1 = 0.3V, V CC 0.3V or Floating I A(ON)ON Leakage Current 1.95 to 4.320.020.0100100nAA = 0.3V, V CC 0.3Vof Port AB 0 or B 1 = 0.3V, V CC 0.3V or Floating R ONSwitch On Resistance 4.30.360.6:I OUT = 100 mA, B 0 or 0.7V, 3.6V (Note 4)B 0 or B 1 = 0V, 0.7V, 3.6V, 4.3V 2.70.40.7I OUT = 100 mA, B 0 or B 1 = 0V,0.7V, 2.0V, 2.7V2.30.550.8I OUT = 100 mA, 0V or Delete 0.7V, 2.0V, 2.3V1.651.52.53.0I OUT = 100 mA, B 0 or B 1 = 0.7V'R ONOn Resistance Matching 4.30.040.75:I OUT = 100 mA, B 0 or B 1 = 0.7V Between Channels 2.70.060.13(Note 5)2.30.120.21.651.0R FLAT(ON)On Resistance Flatness 4.30.25:I OUT = 100 mA, B 0 or B 1 = 0V to V CC(Note 6)2.70.252.30.31.650.3I CC Quiescent Supply Current 4.3 100.030.0100.0 500500nA V IN = 0V or V CC , I OUT = 0V I CCTIncrease in I CC per 4.37.012.015.0P AV IN = 1.8Control Input3.06.07.0V IN = 2.6 4F S A 5157DC Electrical Characteristics (Continued)Note 4: On Resistance is determined by the voltage drop between A and B pins at the indicated current through the switch.Note 5: 'R ON = R ONmax R ONmin measured at identical V CC , temperature, and voltage.Note 6: Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions.AC Electrical Characteristics (All typical value are @ 25q C unless otherwise specified)CapacitanceSymbol Parameter V CC T A = 25q CT A = 40q C to 85q C UnitsConditionsFigure (V)MinTypMax MinMax Numbert ONTurn ON Time3.6 to4.355.060.0nsFigure 42.7 to3.660.065.0B 0 or B 1 = 1.5V, 2.3 to 2.765.070.0R L = 50:, C L = 35 pF1.65 to 1.9570.090.0t OFFTurn OFF Time3.6 to4.330.035.0nsFigure 42.7 to3.635.040.0B 0 or B 1 = 1.5V, 2.3 to 2.740.045.0R L = 50:, C L = 35 pF1.65 to 1.9540.055.0t B-MBreak-Before-Make 3.6 to 4.3 5.0nsFigure 5Time2.7 to3.6 5.0B 0 or B 1 = 1.5V, 2.3 to 2.7 5.0R L = 50:, C L = 35 pF1.65 to 1.955.0QCharge Injection3.6 to4.3 6.0pCC L = 1.0 nF, V GEN = 0V, R GEN = 0:Figure 72.7 to3.6 6.02.3 to 2.7 6.01.65 to 1.95OIRROFF-Isolation3.6 to4.3 75.0dBf = 100kHz, R L = 50:, C L = 5 pF (Stray)Figure 62.7 to3.6 75.02.3 to 2.7 75.01.65 to 1.9575.0XtalkCrosstalk3.6 to4.3 75.0dBf = 100kHz, R L = 50:, C L = 5 pF (Stray)Figure 62.7 to3.6 75.02.3 to 2.7 75.01.65 to 1.9570.0BW 3db Bandwidth 1.65 to 4.380.0MHzR L = 50:Figure 9THDTotal Harmonic 3.6 to 4.3%Figure 10Distortion2.7 to3.60.02R L = 32:, V IN = 2V P .P , f= 20Hz to 20kHz 2.3 to 2.70.036R L = 32:, V IN = 1.5V P .P , f= 20Hz to 20kHz 1.65 to 1.950.01R L = 32:, V IN = 1.2V P .P , f= 20Hz to 20kHzSymbol Parameter V CC T A = 25q CT A = 40q C to 85q C UnitsConditions(V)MinTyp MaxMinMaxC IN Control Pin Input Capacitance 0.0 1.5pF f = 1MHz (see Figure 8)C OFF B Port OFF Capacitance 4.521.0pF f = 1MHz (see Figure 8)C ONA Port ON Capacitance4.590.0pFf = 1MHz (see Figure 8)FSA5157FIGURE 1. R ONSwitch On Resistance, I ON = 100mA, V CC = 2.3VFIGURE 2. R ON Switch On Resistance, I ON = 100mA, V CC = 2.7VFIGURE 3. R ON Switch On Resistance, I ON = 100mA, V CC = 4.3V 6F S A 5157AC Loading and WaveformsC L includes Fixture and Stray CapacitanceLogic Input Waveforms Inverted for Switchesthat have the Opposite Logic SenseFIGURE 4. Turn-On/Turn-Off TimingC L Includes Fixture and Stray CapacitanceFIGURE 5. Break-Before-Make TimingFIGURE 6. OFF Isolation and CrosstalkFSA5157AC Loading and Waveforms(Continued)Q = ('V OUT )(C L )FIGURE 7. Charge InjectionFIGURE 8. ON/OFF Capacitance Measurement SetupFIGURE 9. BandwidthFIGURE 10. Harmonic Distortion 8F S A 5157Tape and Reel SpecificationTape Format For Micropak 6REEL DIMENSIONS inches (millimeters)Package Tape Number Cavity Cover Tape DesignatorSectionCavitiesStatusStatusLeader (Start End)125 (typ)Empty Sealed L6XCarrier 5000Filled Sealed Trailer (Hub End)75 (typ)EmptySealedTape SizeABCDNW1W2W38 mm7.00.0590.5120.795 2.1650.331 0.059/ 0.0000.567W1 0.078/ 0.039(177.8)(1.50)(13.00)(20.20)(55.00)(8.40 1.50/ 0.00)(14.40)(W1 2.00/ 1.00) FSA5157Physical Dimensions inches (millimeters) unless otherwise noted6-Lead SC70, EIAJ SC88, 1.25mm WidePackage Number MAA06A 10F S A 5157Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)Pb-Free 6-Lead MicroPak, 1.0mm WidePackage Number MAC06AFSA5157 0.4:Low Voltage SPDT Analog Switch (Preliminary)DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITYARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES ITCONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICESOR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATIONAs used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reason-ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONSDefinition of termsDatasheet Identification Product Status DefinitionAdvance Information Formative or In Design This datasheet contains the design specifications for product develop-ment. Specifications may change in any manner without notice.Preliminary First Production This datasheet contains preliminary data, and supplementary data willbe published at a later date. Fairchild Semiconductor reserves the rightto make changes at any time without notice in order to improve design.No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductorreserves the right to make changes at any time without notice in orderto improve design.Obsolete Not In Production This datasheet contains specifications on a product that has been dis-continued by Fairchild Semiconductor. The datasheet is printed for ref-erence information only.元器件交易网。
制冷剂r507a参数
制冷剂r507a参数制冷剂R507A是一种常用的制冷剂，广泛应用于商业和工业领域。
它是由R125和R143a两种制冷剂按一定比例混合而成的。
R507A具有较低的臭氧破坏潜能和较高的制冷效能，因此在制冷系统中得到了广泛应用。
R507A的化学组成为50%的R125和50%的R143a。
R125是一种氟代烃，化学式为C2HF5，具有较低的臭氧破坏潜能，属于臭氧层友好制冷剂。
而R143a是一种氟代烃，化学式为C2H3F3，同样具有较低的臭氧破坏潜能。
由于R507A是由这两种制冷剂按比例混合而成，因此其整体臭氧破坏潜能也较低。
R507A具有良好的制冷性能。
它的蒸汽化热和比容较低，使得制冷系统能够更高效地运行。
同时，R507A的温度滑移较小，即在不同温度下，其蒸汽和液体的温度差异不大，这有助于提高制冷系统的稳定性和性能。
R507A具有较低的毒性和燃烧性。
它的毒性系数为1，属于低毒制冷剂，使用时对人体安全性较高。
同时，R507A的燃烧潜能也较低，不易引发火灾，保证了制冷系统的安全性。
然而，R507A也存在一些局限性。
首先，由于R507A是一种混合制冷剂，其组分会发生分离现象。
在长期使用过程中，R507A的成分会发生变化，导致制冷效果下降。
其次，R507A的工作压力较高，对制冷系统的设计和制造提出了一定的要求。
此外，R507A的价格相对较高，使用成本也较高。
为了克服R507A的一些局限性，人们也在不断研发新的制冷剂。
例如，一些研究者正在开发具有更低臭氧破坏潜能和更高制冷效能的制冷剂。
同时，也有研究者在研究如何减少制冷系统对制冷剂的依赖性，以降低使用成本。
R507A作为一种常用的制冷剂，具有较低的臭氧破坏潜能和良好的制冷性能。
虽然它存在一些局限性，但通过不断的研发和改进，相信可以找到更好的替代品。
制冷行业在选择制冷剂时，需要综合考虑其环境友好性、制冷性能和使用成本等因素，以寻求最佳的解决方案。
APCH样本
直接式自然冷却系统
间接式自然冷却系统
5
i-MASTER 微处理控制系统
AIRFACT 功能强大的 I-MASTER 电脑控制系统控制机组的运行，它根据系统需求负荷的大小，启动/关闭压缩 机的运行，或使压缩机工作在一定的负荷输出下。电脑控制其监测每一个系统以及每一个压缩机的运行状态， 当机组发生故障时，关闭故障单元的运行。
冷媒与制冷回路
机组采用 R22 或 R134A 冷媒，每 一台机组具有两个独立的制冷回 路，他们包括了螺杆式制冷压缩 机、冷凝器、蒸发器、干燥过滤器、 具有湿度指示的视液镜、液体管路 电磁阀、电子膨胀阀等。机组在出 厂时已经经过了压力检验，并灌注 了冷媒。所有的低温管道都包有保 温隔热层。
3
带有自然冷却的 APCH-FD/FS 机组
AIRFACT 不断致力于为市场提供节 能、环保，以及高可靠性和低费用的 新技术和新产品。APCH 系列风冷冷 水机组及自然冷却机组专为 IT 和工 业制冷应用而设计
AIRFACT
1959 年，AIRFACT 创立于澳大利亚悉尼。它是澳大 利亚最早的本土制冷空调产品品牌。 创立以后的 AIRFACT，生产制造了大量的屋顶式空调 机组、分体式空调机组、风管式空调机组、整装式冷 水机组等。这些产品在澳大利亚制冷空调市场占据了 重要的地位。 2000 年悉尼奥运会，AIRFACT 和全球最大螺杆压缩 机制造商 BITZER 合作成为悉尼奥运会合作伙伴，再 次发挥了重要的作用，为大量的奥运会设施提供了高 质量的制冷空调设备。 2003 年，AIRFACT 在中国深圳建立了一个新的工厂， 并将业务范围从商用空调市场扩展到了新兴的 IT 领 域，为 IT 应用提供包括冷却系统和机架系统在内的 IT 物理基础设施产品。 今天，有着超过 50 年历史的 AIRFACT，继续不断创 新和探索新技术，为顾客提供节能、节省费用的高质 量产品。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
SC70 6-lead surface mount packages
The FSA4157A features very low quiescent current even when the control voltage is lower than the VCC supply. This feature services the mobile handset applications very well allowing for the direct interface with baseband processor general purpose I/Os.
■ Broad VCC operating range: – FSA4157: 1.65V to 5.5V – FSA4157A: 2.7V to 5.5V
■ Fast turn-on and turn-off time
■ Break-before-make enable circuitry
■ Over-voltage tolerant TTL compatible control circuitry
(All typical values are @ 25°C unless otherwise specified)
Symbol
Parameter
Conditions
VCC (V)
TA=
+25°C
-40°C to +85°C
Min. Typ. Max. Min. Max.
Units
VIH
Input Voltage High
A57
6-Lead SC70, EIAJ SC88, 3k Units on Tape and Reel
1.25mm Wide
A57
Pb-Free 6-Lead SC70,
3k Units on Tape and Reel
EIAJ SC88, 1.25mm Wide
EG
Pb-Free 6-Lead MicroPak, 5k Units on Tape and Reel
Symbol
Parameter
Rating
VCC VIN
PD
TSTG TJ TL
Supply Voltage DC Switch Voltage(2) DC Input Voltage(2) DC Input Diode Current Switch Current Peak Switch Current (Pulse at 1mS duration, <10% Duty Cycle) Power Dissipation @ 85°C
Function Data Ports Control Input
2 FSA4157, FSA4157A Rev. 1.0.1
FSA4157, FSA4157A Low Voltage 1Ω SPDT Analog Switch
元器件交易网
SC70 6L Package MicroPak 6L Package Storage Temperature Range Maximum Junction Temperature Lead Temperature (Soldering, 10 seconds) ESD (Human Body Model) FSA4157A
FSA4157, FSA4157A Low Voltage 1Ω SPDT Analog Switch
元器件交易网
Analog பைடு நூலகம்ymbols
Pin Assignment for SC70
B1 1
6S
GND 2
5 VCC
B0 3
(Top View)
4A
Pin Assignment for MicroPak
2.7 to 3.6 –
–
–
2.0
–
V
4.5 to 5.5 –
–
–
2.4
–
VIL
Input Voltage Low
(FSA4157A Only)
2.7 to 3.6 –
–
–
–
0.4
V
2.7 to 3.6 –
–
–
–
0.6
4.5 to 5.5 –
–
–
–
0.8
IIN
Control Input Leakage VIN = 0V to VCC
Rating
1.65V to 5.5V 2.7V to 5.5V 0V to VCC 0V to VCC
−40°C to +85°C
350°C/W 330°C/W (estimated)
Notes: 2. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. 3. Control input must be held HIGH or LOW and it must not float.
3 FSA4157, FSA4157A Rev. 1.0.1
FSA4157, FSA4157A Low Voltage 1Ω SPDT Analog Switch
元器件交易网
DC Electrical Characteristics
FSA4157L6X
MAC06A
FSA4157AP6
MAA06A
FSA4157AP6X
MAA06A
FSA4157AP6X_NL(1) MAA06A
FSA4157AL6X
MAC06A
A57
6-Lead SC70, EIAJ SC88, 250 Units on Tape and Reel
1.25mm Wide
Ordering Information
Package Product Code
Order Number Number Top Mark
Package Description
Supplied As
FSA4157P6
MAA06A
FSA4157P6X FSA4157P6X_NL(1)
MAA06A MAA06A
3k Units on Tape and Reel
EIAJ SC88, 1.25mm Wide
EU
Pb-Free 6-Lead MicroPak, 5k Units on Tape and Reel
1.0mm Wide
Pb-Free package per JEDEC J-STD-020B.
Note: 1. “_NL” indicates lead-free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Parameter Supply Voltage
FSA4157 FSA4157A Control Input Voltage Switch Input Voltage Operating Temperature Thermal Resistance θJA in still air SC70 6L Package MicroPak 6L Package
General Description
FSA4157 and FSA4157A are high performance Single Pole/Double Throw (SPDT) analog switches. Both devices feature ultra low RON of 1.15Ω maximum at 4.5V VCC and will operate over the wide VCC range of 1.65V to 5.5V for FSA4157, and 2.7V to 5.5V for FSA4157A. The device is fabricated with sub-micron CMOS technology to achieve fast switching speeds and is designed for break-before-make operation. The select input is TTL level compatible.
S1
6 B1
VCC 2
5 GND
A3
4 B0
(Top Through View)
Truth Table
Control Input(s) L H
H = HIGH Logic Level L = LOW Logic Level
Pin Descriptions
Pin Names A, B0, B1 S
Function B0 Connected to A B1 Connected to A
元器件交易网
FSA4157, FSA4157A Low Voltage 1Ω SPDT Analog Switch
March 2006
FSA4157, FSA4157A Low Voltage 1Ω SPDT Analog Switch
Features
■ FSA4157A features lower ICC when the S input is lower than VCC
Absolute Maximum Ratings