MC10H113FN中文资料
MC10E111FN中文资料
MC10E111 MC100E111
1:9 DIFFERENTIAL CLOCK DRIVER
• • • • • • •
Low Skew Guarateed Skew Spec Differential Design VBB Output Enable Extended 100E VEE Range of –4.2 to –5.46V 75kΩ Input Pulldown Resistors
MC10E111 MC100E111
DC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
–40°C Symbol VBB Characteristic Output Reference Voltage 10E 100E Input HIGH Current Power Supply Current 10E 100E Input Sensitivity Commom Mode Range 50 –1.6 –0.4 48 48 Min –1.43 –1.38 Typ Max –1.30 –1.26 150 Min –1.38 –1.38 0°C Typ Max –1.27 –1.26 150 Min –1.35 –1.38 25°C Typ Max –1.25 –1.26 150 Min –1.31 –1.38 85°C Typ Max –1.19 –1.26 150 µA mA 60 60 50 –1.6 –0.4 48 48 60 60 50 –1.6 –0.4 48 48 60 60 50 –1.6 –0.4 48 55 60 69 mV V 1 2 Unit V Cond
元器件交易网
MOTOROLA
MC10H641FNR2G;MC10H641FNG;MC10H641FNR2;MC100H641FN;MC100H641FNG;中文规格书,Datasheet资料
MC10H641, MC100H641 Single Supply PECL to TTL 1:9 Clock Distribution ChipDescriptionThe MC10H/100H641 is a single supply, low skew translating 1:9 clock driver. Devices in the ON Semiconductor H641 translator series utilize the PLCC−28 for optimal power pinning, signal flow through and electrical performance.The device features a 24 mA TTL output stage, with AC performance specified into a 50 pF load capacitance. A latch is provided on−chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldown) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. Both the LEN and EN pins are positive ECL inputs.The V BB output is provided in case the user wants to drive the device with a single−ended input. For single−ended use, the V BB should be connected to the D input and bypassed with a 0.01 m F capacitor.The 10H version of the H641 is compatible with positiveMECL 10H™ logic levels. The 100H version is compatible with positive 100K levels.Features•PECL − TTL Version of Popular ECLinPS E111•Low Skew•Guaranteed Skew Spec•Latched Input•Differential ECL Internal Design•V BB Output for Single−Ended Use•Single +5.0 V Supply•Logic Enable•Extra Power and Ground Supplies•Separate ECL and TTL Supply Pins•Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.MARKING DIAGRAM*xxx= 10 or 100A= Assembly LocationWL= Wafer LotYY= YearWW= Work WeekG=Pb−Free PackagePLCC−28FN SUFFIXCASE 776MCxxxH641GAWLYYWW1*For additional marking information, refer toApplication Note AND8002/D.See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.ORDERING INFORMATIONV BB D D VE LEN GE EN1GT Q5VT Q4VT Q3GTGT Q6VT Q7VT Q8GT GTQ2VTQ1VTQ0GT5678910112524232221201926272823418171615141312Figure 1. Pinout: PLCC −28 (Top View)TTL OutputsQ0Q1Q2Q3Q4Q5Q6Q7Q8Figure 2. Logic DiagramTable 2. 10H PECL DC CHARACTERISTICSSymbol Characteristic Condition0°C25°C85°CUnit Min Max Min Max Min MaxI INH Input HIGH Current255175175m A I IL Input LOW Current0.50.50.5m A V IH Input HIGH Voltage V E = 5.0 V (Note 1) 3.83 4.16 3.87 4.19 3.94 4.28V V IL Input LOW Voltage V E = 5.0 V (Note 1) 3.05 3.52 3.05 3.52 3.05 3.55V V BB Output Reference Voltage V E = 5.0 V (Note 1) 3.62 3.73 3.65 3.75 3.69 3.81V NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.1.PECL V IH, V IL, and V BB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0 V.Table 3. 100H PECL DC CHARACTERISTICSSymbol Characteristic Condition0°C25°C85°CUnit Min Max Min Max Min MaxI INH Input HIGH Current255175175m A I INL Input LOW Current0.50.50.5m A V IH Input HIGH Voltage V E = 5.0 V (Note 2) 3.835 4.120 3.835 4.120 3.835 4.120V V IL Input LOW Voltage V E = 5.0 V (Note 2) 3.190 3.525 3.190 3.525 3.190 3.525V V BB Output Reference Voltage V E = 5.0 V (Note 2) 3.62 3.74 3.62 3.74 3.62 3.74V NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.2.PECL V IH, V IL, and V BB are referenced to VE and will vary 1:1 with the power supply. The levels shown are for VE = 5.0 V.Table 4. DC CHARACTERISTICS (V T = V E = 5.0 V ± 5%)Symbol CharacteristicT A = 0°C T A = + 25°C T A = + 85°CUnit Min Typ Max Min Typ Max Min Typ MaxI EE Power Supply CurrentPECL243024302430mA I CCH TTL243024302430mA I CCL273527352735mA NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.Table 5. TTL DC CHARACTERISTICS (V T = V E = 5.0 V ± 5%)Symbol0°C25°C85°C Characteristic Condition Min Max Min Max Min Max UnitV OH Output HIGH Voltage I OH = −15 mA 2.5 2.5 2.5V V OL Output LOW Voltage I OL = 24 mA0.50.50.5V I OS Output Short Circuit Current V OUT = 0 V−100−225−100−225−100−225mA NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.Table 6. AC CHARACTERISTICS (V T = V E = 5.0 V ± 5%)Characteristic T J = 0°C T J = + 25°C T J = + 85°CSymbol Condition Min Typ Max Min Typ Max Min Typ Max Unitt PLH t PHL Propagation DelayD to QCL = 50 pF (Note 3) 5.005.365.505.866.006.364.865.275.365.775.866.275.085.435.585.936.086.43nst skew Device SkewPart−to−PartSingle V CCOutput−to−Output CL = 50 pF (Note 4)CL = 50 pF (Note 5)CL = 50 pF (Note 6)100075035010007503501000750350pst PLH t PHL Propagation DelayLEN to QCL = 50 pF 4.9 6.9 4.9 6.9 5.07.0nst PLH t PHL Propagation DelayEN to QCL = 50 pF 5.07.0 4.9 6.9 5.07.0nst r t f Output Rise/Fall0.8 V to 2.0 VCL = 50 pF 1.71.61.71.61.71.6nsf MAX Max Input Frequency CL = 50 pF (Note 7)656565MHz t S Setup Time0.750.500.750.500.750.50ns t H Hold Time0.750.500.750.500.750.50ns NOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.3.Propagation delay measurement guaranteed for junction temperatures. Measurements performed at 50 MHz input frequency.4.Skew window guaranteed for a single temperature across a V CC = V T = V E of 4.75 V to5.25 V (See Application Note in this data sheet).5.Skew window guaranteed for a single temperature and single V CC = V T = V E6.Output−to−output skew is specified for identical transitions through the device.7.Frequency at which output levels will meet a 0.8 V to 2.0 V minimum swing.Determining Skew for a Specific ApplicationThe H641 has been designed to meet the needs of very low skew clock distribution applications. In order to optimize the device for this application special considerations are necessary in the determining of the part−to−part skew specification limits. Older standard logic devices are specified with relatively slack limits so that the device can be guaranteed over a wide range of potential environmental conditions. This range of conditions represented all of the potential applications in which the device could be used. The result was a specification limit that in the vast majority of cases was extremely conservative and thus did not allow for an optimum system design. For non−critical skew designs this practice is acceptable, however as the clock speeds of systems increase overly conservative specification limits can kill a design.The following will discuss how users can use the information provided in this data sheet to tailor a part−to−part skew specification limit to their application. The skew determination process may appear somewhat tedious and time consuming, however if the utmost in performance is required this procedure is necessary. For applications which do not require this level of skew performance a generic part−to−part skew limit of 2.5 ns can be used. This limit is good for the entire ambient temperature range, the guaranteed V CC (V T, V E) range and the guaranteed operating frequency range.Temperature DependenceA unique characteristic of the H641 data sheet is that the AC parameters are specified for a junction temperature rather than the usual ambient temperature. Because very few designs will actually utilize the entire commercial temperature range of a device a tighter propagation delay window can be established given the smaller temperature range. Because the junction temperature and not the ambient temperature is what affects the performance of the device the parameter limits are specified for junction temperature. In addition the relationship between the ambient and junction temperature will vary depending on the frequency, load and board environment of the application. Since these factors are all under the control of the user it is impossible to provide specification limits for every possible application. Therefore a baseline specification was established for specific junction temperatures and the information that follows will allow these to be tailored to specific applications.Since the junction temperature of a device is difficult to measure directly, the first requirement is to be able to “translate” from ambient to junction temperatures. The standard method of doing this is to use the power dissipation of the device and the thermal resistance of the package. For a TTL output device the power dissipation will be a function of the load capacitance and the frequency of the output. The total power dissipation of a device can be described by the following equation:P D (watts) = I CC (no load) * V CC +V S* V CC * f * C L * # Outputswhere:V S= Output V oltage Swing = 3.0 Vf = Output FrequencyC L = Load CapacitanceI CC = I EE + I CCHFigure 1 plots the I CC versus Frequency of the H641 with no load capacitance on the output. Using this graph and the information specific to the application a user can determine the power dissipation of the H641.Figure 1. I CC versus f (No Load)01020304050607080FREQUENCY (MHz)NORMALIZEDICC12345Figure 2 illustrates the thermal resistance (in °C/W) for the PLCC−28 under various air flow conditions. By reading the thermal resistance from the graph and multiplying by the power dissipation calculated above the junction temperature increase above ambient of the device can be calculated.02004006008001000AIRFLOW (LFPM)THERMALRESISTANCE(3040506070C/W)°Figure 2. j JA versus Air FlowFinally taking this value for junction temperature and applying it to Figure 3 allows the user to determine thepropagation delay for the device in question. A more common use would be to establish an ambient temperature range for the H641’s in the system and utilize the above methodology to determine the potential increased skew of the distribution network. Note that for this information if the T PD versus Temperature curve were linear the calculations would not be required. If the curve were linear over all temperatures a simple temperature coefficient could be provided.Figure 3. T PD versus Junction Temperature−30JUNCTION TEMPERATURE (P R O P A G A T I O N D E L A Y (n s )5.2−101030507090110130°C)5.45.65.86.06.26.4V CC DependenceTTL and CMOS devices show a significant propagationdelay dependence with V CC . Therefore the V CC variation in a system will have a direct impact on the total skew of the clock distribution network. When calculating the skew between two devices on a single board it is very likely an assumption of identical V CC ’s can be made. In this case the number provided in the data sheet for part −to −part skew would be overly conservative. By using Figure 4 the skew given in the data sheet can be reduced to represent a smaller or zero variation in V CC . The delay variation due to the specified V CC variation is ≈ 270 ps. Therefore, the 1 ns window on the data sheet can be reduced by 270 ps if the devices in question will always experience the same V CC .The distribution of the propagation delay ranges given in the data sheet is actually a composite of three distributions whose means are separated by the fixed difference inpropagation delay at the typical, minimum and maximum V CC .Figure 4. D T PD versus V CC4.75VCC (V)T −1404.85 4.955.05 5.15 5.25−100−60−202060100140ΔP D (p s )Capacitive Load DependenceAs with V CC the propagation delay of a TTL output is intimately tied to variation in the load capacitance. The skew specifications given in the data sheet, of course, assume equal loading on all of the outputs. However situations could arise where this is an impossibility and it may be necessary to estimate the skew added by asymmetric loading. In addition the propagation delay numbers are provided only for 50 pF loads, thus necessitating a method of determining the propagation delay for alternative loads.Figure 5 shows the relationship between the two propagation delays with respect to the capacitive load on the output. Utilizing this graph and the 50 pF limits the specification of the H641 can be mapped into a spec for either a different value load or asymmetric loads.Figure 5. T PD versus LoadCAPACITIVE LOAD (pF)M O R M A L I Z E D P R O P A G A T I O N D E L A Y (n s )0.751020304050607080901000.800.850.900.951.001.051.101.15Rise/Fall Skew DeterminationThe rise−to−fall skew is defined as simply the difference between the T PLH and the T PHL propagation delays. This skew for the H641 is dependent on the V CC applied to the device. Notice from Figure 4 the opposite relationship of T PD versus V CC between T PLH and T PHL. Because of this the rise−to−fall skew will vary depending on V CC. Since in all likelihood it will be impossible to establish the exact value for V CC, the expected variation range for V CC should be used. If this variation will be the ± 5% shown in the data sheet the rise−to−fall skew could be established by simply subtracting the fastest T PLH from the slowest T PHL; this exercise yields 1.41 ns. If a tighter V CC range can be realized Figure 4 can be used to establish the rise−to−fall skew. Specification Limit Determination ExampleThe situation pictured in Figure 6 will be analyzed as an example. The central clock is distributed to two different cards; on one card a single H641 is used to distribute the clock while on the second card two H641’s are required to supply the needed clocks. The data sheet as well as the graphical information of this section will be used to calculate the skew between H641a and H641b as well as the skew between all three of the devices. Only the T PLH will be analyzed, the T PHL numbers can be found using the same technique. The following assumptions will be used:−All outputs will be loaded with 50 pF−All outputs will toggle at 30 MHz−The V CC variation between the two boards is ± 3 %−The temperature variation between the threedevices is ± 15°C around an ambient of 45°C.−500 lfpm air flowThe first task is to calculate the junction temperature for the devices under these conditions. Using the power equation yields:P D=I CC (no load) * V CC +V CC * V S * f * C L * # outputs=4.3 * 48m A * 5.0 V + 5.0 V * 3.0 V * 30 MHz *50 pF * 9=432 mW + 203 mW = 635 mWUsing the thermal resistance graph of Figure 2 yields a thermal resistance of 41°C/W which yields a junction temperature of 71°C with a range of 56°C to 86°C. Using the T PD versus Temperature curve of Figure 3 yields a propagation delay of 5.42 ns and a variation of 0.19 ns. Since the design will not experience the full ± 5% V CC variation of the data sheet the 1.0 ns window provided will be unnecessarily conservative. Using the curve of Figure 4 shows a delay variation due to a ± 3% V CC variation of ± 0.075 ns. Therefore the 1.0 ns window can be reduced to 1.0 ns − (0.27 ns − 0.15 ns) = 0.88 ns. Since H641a and H641b are on the same board we will assume that they will always be at the same V CC; therefore the propagation delay window will only be 1 ns − 0.27 ns = 0.73 ns.Putting all of this information together leads to a skew between all devices of0.19 ns + 0.88 ns(temperature + supply, and inherent device),while the skew between devices A and B will be only 0.19 ns + 0.73 ns(temperature + inherent device only).In both cases, the propagation delays will be centered around 5.42 ns, resulting in the following t PLH windows: T PLH = 4.92 ns − 5.99 ns; 1.07 ns window(all devices)T PLH= 5.00 ns − 5.92 ns; 0.92 ns window(devices a & b)Of course the output−to−output skew will be as shown in the data sheet since all outputs are equally loaded.This process may seem cumbersome, however the delay windows, and thus skew, obtained are significantly better than the conservative worst case limits provided at the beginning of this note. For very high performance designs, this extra information and effort can mean the difference between going ahead with prototypes or spending valuableFigure 6. Example ApplicationORDERING INFORMATIONDevice Package Shipping†MC10H641FN PLCC−2837 Units / Rail37 Units / RailMC10H641FNG PLCC−28(Pb−Free)MC10H641FNR2PLCC−28500 / Tape & Reel500 / Tape & ReelMC10H641FNR2G PLCC−28(Pb−Free)MC100H641FN PLCC−2837 Units / Rail37 Units / RailMC100H641FNG PLCC−28(Pb−Free)MC100H641FNR2PLCC−28500 / Tape & Reel500 / Tape & ReelMC100H641FNR2G PLCC−28(Pb−Free)†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.Resource Reference of Application NotesAN1405/D−ECL Clock Distribution TechniquesAN1406/D−Designing with PECL (ECL at +5.0 V)AN1503/D−ECLinPS t I/O SPiCE Modeling KitAN1504/D−Metastability and the ECLinPS FamilyAN1568/D−Interfacing Between LVDS and ECLAN1672/D−The ECL Translator GuideAND8001/D−Odd Number Counters DesignAND8002/D−Marking and Date CodesAND8020/D−Termination of ECL Logic DevicesAND8066/D−Interfacing with ECLinPSAND8090/D−AC Characteristics of ECL DevicesPACKAGE DIMENSIONSPLCC −28FN SUFFIXPLASTIC PLCC PACKAGECASE 776−02ISSUE ESL−M S 0.010 (0.250) NST VIEW SNOTES:1.DATUMS −L−, −M−, AND −N− DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.2.DIMENSION G1, TRUE POSITION TO BEMEASURED AT DATUM −T−, SEATING PLANE.3.DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.4.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.5.CONTROLLING DIMENSION: INCH.6.THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012(0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.7.DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037(0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.4850.49512.3212.57B 0.4850.49512.3212.57C 0.1650.180 4.20 4.57E 0.0900.110 2.29 2.79F 0.0130.0190.330.48G 0.050 BSC 1.27 BSC H 0.0260.0320.660.81J 0.020−−−0.51−−−K 0.025−−−0.64−−−R 0.4500.45611.4311.58U 0.4500.45611.4311.58V 0.0420.048 1.07 1.21W 0.0420.048 1.07 1.21X 0.0420.056 1.07 1.42Y −−−0.020−−−0.50Z 2 10 2 10 G10.4100.43010.4210.92K10.040−−− 1.02−−−____ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATIONECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).MECL 10H is a trademark of Motorola, Inc.分销商库存信息:ONSEMIMC10H641FNR2G MC10H641FNG MC10H641FNR2 MC100H641FN MC100H641FNG MC100H641FNR2 MC100H641FNR2G MC10H641FN。
MC100系列说明书(DOC)
MC100系列智能多媒体控制系统Intelligent Multimedia Control System（适用于MC100系列机型）用户安装手册User’s Manual* *请在安装使用前认真阅读本说明书**尊敬的用户：感谢您选购我们生产的这个系列多媒体中央控制器。
该产品具有外观设计小巧高档大方；使用简单方便；功能强大；可直接外接其他厂家的设备；二个可编程232口最多可同时控制两个不同厂家的投影机或其他设备；可对各接口重新定义和单独控制；投影机一键切换；投影幕自动升降；开机即是电脑画面等等多种实用功能。
为了您能安全地使用本设备，发挥其最大的功能，强烈建议在安装使用前先仔细阅读本说明书。
若有任何技术问题或对产品的意见和建议，请与本公司技术服务部联系。
联系方法如下：电话：（020）33534881 61087188传真：（020）61087188-8002地址：广州市天河软件园建工路9号4楼南区A1邮编：510665E-mail：laitong@http：//特别提醒：1. 在使用本系统的时候，严禁在开机时对各个部件进行插拔（特别是通讯口及VGA接口，这可能会人为损坏设备）。
2. 本控制器为智能开关设计，在雷雨天气或长时间不使用时，请关闭电源总闸。
3. 本控制器内有强电模块，严禁带电自行维修。
4．因中控本身已做好接地处理，为有效保护中控及设备，请在强电输入部分做好接地措施！目录一．系统说明1，中控简介 (5)2，简单使用说明 (5)二，硬件连接1，连线说明 (6)三，系统设置1，系统通讯协议 (8)2，开机状态设置 (10)3，开关机流程设置 (11)4，开关延时设置 (12)5，投影机设置 (12)6，红外学习 (14)7，按键面板设置 (15)8，其它设置 (16)四，常见故障处理1，按控制面板“系统开”无法开机 (18)2，红外学习不成功或显示成功却不能遥控 (18)3，有些设备红外遥控不灵 (19)4，投影机打不开 (19)5，中控与电脑连接失败 (19)一、系统说明1. 中控简介智能多媒体控制器为简单电化教室、会议室及家居提供了很好的解决方案。
H3N技术应用手册第4版
2.1 外形尺寸及安装尺寸 ......................................................................................... 4 2.2 安装环境 ........................................................................................................... 5 2.3 驱动器连接端子................................................................................................. 6 2.4 安装和配线时的注意事项 .................................................................................. 7
3.2.1 CN1 外形 ................................................................................................... 8 3.2.2 CN1 定义 ................................................................................................... 9 3.3 CN2 接口 .......................................................................................................... 9 3.3.1 CN2 外形 ................................................................................................... 9 3.3.2 CN2 定义 ................................................................................................. 10 3.4 输入输出接口类型 ........................................................................................... 11 3.4.1 数字信号输入接口.................................................................................... 11 3.4.2 数字信号输出接口.................................................................................... 11 3.4.3 脉冲指令输入接口.................................................................................... 12 3.4.4 模拟量输入接口 ....................................................................................... 13 3.4.5 编码器信号输出接口 ................................................................................ 13 3.4.6 编码器 Z 信号集电极开路输出接口.......................................................... 15 3.4.7 光电编码器信号输入接口......................................................................... 15 3.5 标准接线方式 .................................................................................................. 15 3.5.1 位置控制下标准接线图 ............................................................................ 15 3.5.2 速度/转矩模拟量控制下标准接线图 ......................................................... 17
MC10E016中文资料
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8 Bit Synchronous Binary Up Counter
The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture and operation are the same as the MC10H016 in the MECL 10H family, extended to 8-bits, as shown in the logic symbol. The counter features internal feedback of TC, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.
悍马主板说明书
环境安全性须知 z 灰尘、潮湿以及剧烈的温度变化都会影响主板的使用寿命,请尽量避免在这些恶劣环
境地方放置和使用。 z 本产品的标准使用环境温度为 0 度～40 度 (数据来自于主芯片要求)。 z 一般情况下，当环境温度变化过大, 可能导致接插件 (CONNECTOR) 之间产生接触性
- II -
安全指导
1. 请仔细阅读这些安全指导。 2. 请保留这份用户手册以便日后参考。 3. 在您开始安装之前请将设备放置于稳定可靠的平台上面。 4. 在您将设备连接电源供应器之前请确保电源电压合乎标准。 5. 设备上所有的警告,警示您都应该注意。 6. 在安装附加的接口与模块之前请将设备与连接器间的连接断开。 7. 决不能让任何液体流入机箱的开口处,这样的行为有可能会引起火灾或电击。 8. 不正确的电池替换可能会引起爆炸.请使用制造厂商建议的电池类型作替换。 9. 如果发生下列情形,请专职的服务人员为您检查您的设备：
商标布告 (按字母表的顺序排列)
所有的品牌,产品,徽标,商标和公司名称都是属于商标或注册商标各自的拥有者。 AMD, Phenom™ II x 4；Phenom™ II x 3；Phenom™ II x2；Athlon II™ x4；Athlon II™ x3；Athlon II™ x2；Sempron™是AMD有限公司的注册商标。 AMI ® 是American Megatrend, Inc.的注册商标。 Kensington 和 MicroSaver 是Kensington 科技集团的注册商标。 Microsoft 是Microsoft有限公司的注册商标。 Netware® 是Novell, Inc的注册商标。 AMD, AMD徽标是AMD有限公司在美国和其它国家的注册商标。 PS/2 和 OS®/2 是International Business Machines有限公司的注册商标。 PCMCIA 和 CardBus 是个人电脑存储卡国际联合会的注册商标。 Windows® 98/2000/ /XP/Vista/7 是Microsoft有限公司的注册商标。
MC10H116中文资料
VBB* When input pin with bubble goes positive it’s respective output pin with bubble goes positive. *VBB to be used to supply bias to the MC10H116 only and bypassed (when used) with 0.01 µF to 0.1 µF capacitor to ground (0 V). VBB can source < 1.0 mA. The MC10H116 is designed to be used in sensing differential signals over long lines. The bias supply (VBB) is made available to make the device useful as a Schmitt trigger, or in other applications where a stable reference voltage is necessary. Active current sources provide these receivers with excellent common–mode noise rejection. If any amplifier in a package is not used, one input of that amplifier must be connected to VBB to prevent unbalancing the current–source bias network. The MC10H116 does not have internal–input pulldown resistors. This provides high impedance to the amplifier input and facilitates differential connections. Applications: • Low Level Receiver • Voltage Level • Schmitt Trigger Interface VCC1 = Pin 1 VCC2 = Pin 16 VEE = Pin 8
Parker Hannifin 产品目录说明书
16
Parker Hanni�n Corporation
Parker Canada Division
Milton, ON Canada
PCD2005-5
Parker Pneumatic Vortex Flow Meter
17
Parker Hanni�n Corporation
Parker Canada Division
22
Parker Hanni�n Corporation
Parker Canada Division
Milton, ON Canada
PCD2005-5
Parker Pneumatic Vortex Flow Meter
23
Parker Hanni�n Corporation
Parker Canada Division
Milton, ON Canada
PCD2005-5
Parker Pneumatic Water Retract Actuator
8
Parker Hannifin Corporation
Parker Canada Division
Milton, ON Canada
PCD2005-5
Parker Pneumatic P8S-G Sensors
Milton, ON Canada
PCD2005-5
Parker Pneumatic Vortex Flow Meter
21
Parker Hanni�n Corporation
Parker Canada Division
Milton, ON Canada
PCD2005-5
Parker Pneumatic Vortex Flow Meter
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° Characteristic Power Supply Current Input Current High Pins 5, 7, 11, 13 Pins 4, 6, 10, 12 Pin 9 Input Current Low High Output Voltage Low Output Voltage High Input Voltage Low Input Voltage Symbol IE IinH — — — IinL VOH VOL VIH VIL tpd 0.4 0.5 tr tf 0.5 0.5 1.7 2.3 1.8 1.8 0.4 0.5 0.6 0.6 1.8 2.4 1.9 1.9 0.5 0.6 0.6 0.6 1.9 2.5 2.0 2.0 ns ns VCC1 AOUT BOUT AIN AIN BIN BIN VEE 0.5 430 510 1100 — — — — 0.5 270 320 740 — — — — 0.3 270 320 740 — –0.735 –1.60 –0.735 –1.45 µA Vdc Vdc Vdc Vdc 12 13 15 Min — Max 46 Min — 25° Max 42 Min — 75° Max 46 Unit mA µA 10 11 14 6 7 3
AC PARAMETERS
Propagation Delay Data Enable Rise Time Fall Time ns
DIP PIN ASSIGNMENT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 DOUT COUT DIN DIN CIN CIN ENABLE
H H X
–1.02 –0.84 –0.98 –0.81 –0.92 –1.95 –1.63 –1.95 –1.63 –1.95 –1.17 –0.84 –1.13 –0.81 –1.07 –1.95 –1.48 –1.95 –1.48 –1.95
VCC1 = PIN 1 VCC2 = PIN 16 VEE =MICONDUCTOR TECHNICAL DATA
Quad Exclusive OR Gate
The MC10H113 is a Quad Exclusive OR Gate with an enable common to all four gates. The outputs may be wire–ORed together to perform a 4–bit comparison function (A = B). The enable is active LOW. • Propagation Delay, 1.3 ns Typical • Power Dissipation 175 mW Typ/Pkg (No Load) • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K–Compatible MAXIMUM RATINGS
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 –––
Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D).
–T–
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
T B
S
0.25 (0.010)
T A
S
–A–
0.007 (0.180) M T L–M U
S
N
S S
0.007 (0.180) M T L–M
N
S
20
1
X V VIEW D–D
G1
0.010 (0.250)
S
T L–M
S
N
S
A Z R
0.007 (0.180) M T L–M 0.007 (0.180) M T L–M
S
N N
S
S
S
H
0.007 (0.180) M T L–M
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 –––
MC10H113
L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02
LOGIC DIAGRAM
E 9
2
L L
TRUTH TABLE IN L H L H X E OUTPUT L L L L L H H H L L
MOTOROLA
2–214
MECL Data DL122 — Rev 6
元器件交易网
MC10H113
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V
9
–A–
16
–B–
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L–M J –T–
SEATING PLANE
K1 K F VIEW S 0.007 (0.180)
M
VIEW S
S
T L–M
S
N
S
N
S
NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).