DDR

TMS320C642x DSP DDR2Memory ControllerUser's GuideLiterature Number:SPRUEM4ANovember20072SPRUEM4A–November2007Submit Documentation FeedbackPreface (6)1Introduction (7)1.1Purpose of the Peripheral (7)1.2Features (7)1.3Functional Block Diagram (8)1.4Supported Use Case Statement (8)1.5Industry Standard(s)Compliance Statement (8)2Peripheral Architecture (9)2.1Clock Control (9)2.2Memory Map (10)2.3Signal Descriptions (11)2.4Protocol Description(s) (12)2.5Memory Width and Byte Alignment (20)2.6Endianness Support (21)2.7Address Mapping (22)2.8DDR2Memory Controller Interface (26)2.9Refresh Scheduling (29)2.10Self-Refresh Mode (29)2.11Reset Considerations (30)2.12VTP IO Buffer Calibration (31)2.13Auto-Initialization Sequence (31)2.14Interrupt Support (34)2.15DMA Event Support (34)2.16Power Management (34)2.17Emulation Considerations (35)3Supported Use Cases (36)3.1Connecting the DDR2Memory Controller to DDR2Memory (36)3.2Configuring Memory-Mapped Registers to Meet DDR2-400Specification (36)4DDR2Memory Controller Registers (41)4.1SDRAM Status Register(SDRSTAT) (42)4.2SDRAM Bank Configuration Register(SDBCR) (43)4.3SDRAM Refresh Control Register(SDRCR) (45)4.4SDRAM Timing Register(SDTIMR) (46)4.5SDRAM Timing Register2(SDTIMR2) (47)4.6Peripheral Bus Burst Priority Register(PBBPR) (48)4.7Interrupt Raw Register(IRR) (49)4.8Interrupt Masked Register(IMR) (50)4.9Interrupt Mask Set Register(IMSR) (51)4.10Interrupt Mask Clear Register(IMCR) (52)4.11DDR PHY Control Register(DDRPHYCR) (53)4.12VTP IO Control Register(VTPIOCR) (54)4.13DDR VTP Register(DDRVTPR) (55)4.14DDR VTP Enable Register(DDRVTPER) (55)Appendix A Revision History (56)SPRUEM4A–November2007Table of Contents3 Submit Documentation Feedback1Data Paths to DDR2Memory Controller (8)2DDR2Memory Controller Clock Block Diagram (9)3DDR2Memory Controller Signals (11)4Refresh Command (13)5DCAB Command (14)6DEAC Command (15)7ACTV Command (16)8DDR2READ Command (17)9DDR2WRT Command (18)10DDR2MRS and EMRS Command (19)11Byte Alignment(Little-Endian Mode) (20)12Logical Address-to-DDR2SDRAM Address Map (24)13DDR2SDRAM Column,Row,and Bank Access (25)14DDR2Memory Controller FIFO Block Diagram (26)15DDR2Memory Controller Reset Block Diagram (30)16DDR2Memory Controller Power Sleep Controller Diagram (34)17Connecting DDR2Memory Controller for32-Bit Connection (37)18Connecting DDR2Memory Controller for16-Bit Connection (37)19SDRAM Status Register(SDRSTAT) (42)20SDRAM Bank Configuration Register(SDBCR) (43)21SDRAM Refresh Control Register(SDRCR) (45)22SDRAM Timing Register(SDTIMR) (46)23SDRAM Timing Register2(SDTIMR2) (47)24Peripheral Bus Burst Priority Register(PBBPR) (48)25Interrupt Raw Register(IRR) (49)26Interrupt Masked Register(IMR) (50)27Interrupt Mask Set Register(IMSR) (51)28Interrupt Mask Clear Register(IMCR) (52)29DDR PHY Control Register(DDRPHYCR) (53)30VTP IO Control Register(VTPIOCR) (54)31DDR VTP Register(DDRVTPR) (55)32DDR VTP Enable Register(DDRVTPER) (55)4List of Figures SPRUEM4A–November2007Submit Documentation Feedback1PLLC2Configuration (10)2DDR2Memory Controller Signal Descriptions (11)3DDR2SDRAM Commands (12)4Truth Table for DDR2SDRAM Commands (12)5Addressable Memory Ranges (20)616-Bit External Memory (21)732-Bit External Memory (21)8Bank Configuration Register Fields for Address Mapping (22)9Logical Address-to-DDR2SDRAM Address Map for32-Bit SDRAM (23)10Logical Address-to-DDR2SDRAM Address Map for16-bit SDRAM (23)11DDR2Memory Controller FIFO Description (26)12Refresh Urgency Levels (29)13Reset Sources (30)14DDR2SDRAM Configuration by MRS Command (32)15DDR2SDRAM Configuration by EMRS(1)Command (32)16SDRAM Bank Configuration Register(SDBCR)Configuration (38)17DDR2Memory Refresh Specification (38)18SDRAM Refresh Control Register(SDRCR)Configuration (38)19SDRAM Timing Register(SDTIMR)Configuration (39)20SDRAM Timing Register2(SDTIMR2)Configuration (39)21DDR PHY Control Register(DDRPHYCR)Configuration (40)22DDR2Memory Controller Registers Relative to Base Address20000000h (41)23DDR2Memory Controller Registers Relative to Base Address01C42000h (41)24DDR2Memory Controller Registers Relative to Base Address01C40000h (41)25SDRAM Status Register(SDRSTAT)Field Descriptions (42)26SDRAM Bank Configuration Register(SDBCR)Field Descriptions (43)27SDRAM Refresh Control Register(SDRCR)Field Descriptions (45)28SDRAM Timing Register(SDTIMR)Field Descriptions (46)29SDRAM Timing Register2(SDTIMR2)Field Descriptions (47)30Peripheral Bus Burst Priority Register(PBBPR)Field Descriptions (48)31Interrupt Raw Register(IRR)Field Descriptions (49)32Interrupt Masked Register(IMR)Field Descriptions (50)33Interrupt Mask Set Register(IMSR)Field Descriptions (51)34Interrupt Mask Clear Register(IMCR)Field Descriptions (52)35DDR PHY Control Register(DDRPHYCR)Field Descriptions (53)36VTP IO Control Register(VTPIOCR)Field Descriptions (54)37DDR VTP Register(DDRVTPR)Field Descriptions (55)38DDR VTP Enable Register(DDRVTPER)Field Descriptions (55)A-1Document Revision History (56)SPRUEM4A–November2007List of Tables5 Submit Documentation FeedbackPrefaceSPRUEM4A–November2007About This ManualThis document describes the DDR2memory controller in the TMS320C642x Digital Signal Processor(DSP).Notational ConventionsThis document uses the following conventions.•Hexadecimal numbers are shown with the suffix h.For example,the following number is40 hexadecimal(decimal64):40h.•Registers in this document are shown in figures and described in tables.–Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name,its beginning and ending bit numbers above,and itsread/write properties below.A legend explains the notation used for the properties.–Reserved bits in a register figure designate a bit that is used for future device expansion.Related Documentation From Texas InstrumentsThe following documents describe the Signal Processor(DSP).Copies of these documents are available on the Internet at Tip:Enter the literature number in the search boxprovided at .The current documentation that describes the C642x and other technicalcollateral,is available in the C6000DSP product folder at:—TMS320C642x DSP Peripherals Overview Reference Guide.Provides an overview anddescribes the peripherals available on the TMS320C642x Digital Signal Processor(DSP).—TMS320C64x to TMS320C64x+CPU Migration Guide.Describes migrating from theInstruments TMS320C64x digital signal processor(DSP)to the TMS320C64x+DSP.The objective of this document is to indicate differences between the two cores.Functionality in thedevices that is identical is not included.—TMS320C64x/C64x+DSP CPU and Instruction Set Reference Guide.Describes the CPUpipeline,instruction set,and interrupts for the TMS320C64x and TMS320C64x+digital signal processors(DSPs)of the TMS320C6000DSP family.The C64x/C64x+DSP generationcomprises fixed-point devices in the C6000DSP platform.The C64x+DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.—TMS320C64x+DSP Megamodule Reference Guide.Describes the TMS320C64x+digitalprocessor(DSP)megamodule.Included is a discussion on the internal direct memory access (IDMA)controller,the interrupt controller,the power-down controller,memory protection,bandwidthmanagement,and the memory and cache.6Preface SPRUEM4A–November2007Submit Documentation Feedback1Introduction1.1Purpose of the Peripheral1.2FeaturesUser's GuideSPRUEM4A–November 2007This document describes the DDR2memory controller in the TMS320C642x Digital Signal Processor (DSP).The DDR2memory controller is used to interface with JESD79D-2A standard compliant DDR2SDRAM devices.Memories types such as DDR1SDRAM,SDR SDRAM,SBSRAM,and asynchronous memories are not supported.The DDR2memory controller is the major memory location for program and data storage.The DDR2memory controller supports the following features:•JESD79D-2A standard compliant DDR2SDRAM •256Mbyte memory space•Data bus width of 32or 16bits (see the device-specific data manual for the mode(s)that are supported)•CAS latencies:2,3,4,and 5•Internal banks:1,2,4,and 8•Burst length:8•Burst type:sequential •1CS signal•Page sizes:256,512,1024,and 2048•SDRAM autoinitialization •Self-refresh mode •Prioritized refresh•Programmable refresh rate and backlog counter •Programmable timing parameters•Big-endian and little-endian operating modesSPRUEM4A–November 2007DDR2Memory Controller 7Submit Documentation Feedback1.3Functional Block DiagramDSP Master peripheralsEDMA VPSS1.4Supported Use Case Statement1.5Industry Standard(s)Compliance StatementIntroductionThe DDR2memory controller is the main interface to external DDR2memory.Figure 1displays the general data paths to on-chip peripherals and external DDR2SDRAM.Master peripherals,EDMA,the ARM processor,and DSP can access the DDR2memory controller through the switched central resource (SCR).Figure 1.Data Paths to DDR2Memory ControllerThe DDR2memory controller supports JESD79D-2A DDR2-400SDRAM memories utilizing either 32-bit or 16-bit of the DDR2memory controller data bus.See Section 3for more details.The DDR2memory controller is compliant with the JESD79D-2A DDR2SDRAM standard with the exception of the following feature list:•On Die Termination (ODT).The DDR2memory controller does not include any on-die terminating resistors.Furthermore,the on-die terminating resistors of the DDR2SDRAM device must be disabled by tying the ODT input pin of the DDR2SDRAM to ground.•Differential DQS.The DDR2memory controller supports single ended DQS signals.DDR2Memory Controller8SPRUEM4A–November 2007Submit Documentation Feedback2Peripheral Architecture2.1Clock Control2.1.1Clock SourceDDR_CLK Peripheral ArchitectureThis section describes the architecture of the DDR2memory controller as well as how it is structured and how it works within the context of the system-on-a-chip.The DDR2memory controller can gluelesslyinterface to most standard DDR2SDRAM devices and supports such features as self-refresh mode and prioritized refresh.In addition,it provides flexibility through programmable parameters such as the refresh rate,CAS latency,and many SDRAM timing parameters.The following sections include details on how to interface and properly configure the DDR2memory controller to perform read and write operations toexternally-connected DDR2SDRAM devices.Also,Section3provides a detailed example of interfacing the DDR2memory controller to a common DDR2The DDR2memory controller receives two input clocks from internal clock sources,SYSCLK2andPLL2_SYSCLK1(Figure2).SYSCLK2is a divided-down version of the DSP clock.PLL2_SYSCLK1should be at the frequency of the desired data rate,or stated similarly,it shouldoperate at twice the frequency of the desired DDR2memory clock.DDR_CLK and DDR_CLK are the two output clocks of the DDR2memory controller providing the interface clock to the DDR2SDRAM memory.These two clocks operate at a frequency of PLL2_SYSCLK1/2.SYSCLK2and PLL2_SYSCLK1are sourced from two independent PLLs(Figure2).SYSCLK2is sourced from PLL controller1(PLLC1)and PLL2_SYSCLK1is sourced from PLL2(PLLC2).SYSCLK2is clocked at a fixed divider ratio of PLL1.This divider is fixed at3,meaning SYSCLK2isclocked at a frequency of PLL1/3.Once inside the DDR2memory controller,this signal is called VCLK.PLLC2has a programmable divider that is used to divide-down the output clock of PLL2.This dividershould be configured such that PLLC2supplies the PLL2_SYSCLK1at the desired frequency.Forexample,if a150-MHZ DDR2interface clock(DDR_CLK)is desired,then PLLC2must be configured to generate a300-MHZ clock on PLL2_SYSCLK1.Once inside the DDR2memory controller,PLL2_SYSCLK1is called X2_CLK.Figure2.DDR2Memory Controller Clock Block DiagramSPRUEM4A–November2007DDR2Memory Controller9 Submit Documentation Feedback2.1.2Clock Configuration2.1.3DDR2Memory Controller Internal Clock Domains2.2Memory MapPeripheral ArchitectureThe frequency of PLL2_SYSCLK1is configured by selecting the appropriate PLL multiplier anddivider ratio.The PLL multiplier and divider ratio are selected by programming registers within PLLC2.Table 1shows a list of PLL multiplier and divider settings to achieve certain DDR2frequencies.The Table 1is derived by assuming a 27-MHZ reference clock.See the device-specific data manual for the supported.See the TMS320C642x DSP Phase-Locked Loop Controller (PLLC)User's Guide for information on the PLL controller.Note:PLLC2should be configured and a stable clock present on PLL2_SYSCLK1before releasing the DDR2memory controller from reset.Table 1.PLLC2ConfigurationPLL Multiplier PLL Frequency (MHZ)Divider Ratio X2_CLK Frequency (MHZ)DDR2Clock Frequency (MHZ)287563252126195132256.6128.3297833261130.5205402270135318373279139.5215672283.5141.8328643288144225942297148.5236212310155.3246482324162256752337.5168.8There are two clock domains within the DDR2memory controller.The two clock domains are driven by VCLK and a divided-down by 2version of X2_CLK called MCLK.The command FIFO,write FIFO,and read FIFO described in Section 2.8are all on the VCLK domain.From this,you can see that VCLK drives the interface to the The MCLK domain consists of the DDR2memory controller state machine and memory-mapped registers.This clock domain is clocked at the rate of the external DDR2memory,X2_CLK/2.To conserve power within the DDR2memory controller,VCLK,MCLK,and X2_CLK may be stopped.See Section 2.16for proper clock stop procedures.See the device-specific data manual for information describing the device memory-map.DDR2Memory Controller10SPRUEM4A–November 2007Submit Documentation Feedback2.3Signal DescriptionsPeripheral ArchitectureThe DDR2memory controller signals are shown in Figure3and described in Table2.The following features are included:•The maximum data bus is32-bits wide.•The address bus is13-bits wide with an additional3bank address pins.•Two differential output clocks driven by internal clock sources.•Command signals:Row and column address strobe,write enable strobe,data strobe,and data mask.•One chip select signal and one clock enable signal.Figure3.DDR2Memory Controller SignalsTable2.DDR2Memory Controller Signal DescriptionsPin Type DescriptionDDR_CLK,O/Z Clock:Differential clock outputs.DDR_CLKDDR_CKE O/Z Clock enable:Active high.DDR_CS O/Z Chip select:Active low.DDR_WE O/Z Write enable strobe:Active low,command output.DDR_RAS O/Z Row address strobe:Active low,command output.DDR_CAS O/Z Column address strobe:Active low,command output.DDR_DQM[3:0]O/Z Data mask:Output mask signal for write data.DDR_DQS[3:0]I/O/Z Data strobe:Active high,bi-directional signals.Output with write data,input with read data. DDR_BA[2:0]O/Z Bank address:Output,defining which bank a given command is applied.DDR_A[12:0]O/Z Address:Address bus.DDR_D[31:0]I/O/Z Data:Bi-directional data bus.Input for read data,output for write data.DDR_ZN,O Output impedance control:Required to set the DDR2output impedance.Connected by way of DDR_ZP a200-ohm resistor to power and ground(see Figure3).The resistor should be chosen to be4times the desired impedance of the output changing the size of the resistor,theDDR2outputs can be tuned to match the board load,if necessary. Peripheral Architecture2.4Protocol Description(s)The DDR2memory controller supports the DDR2SDRAM commands listed in Table3.Table4shows the signal truth table for the DDR2SDRAM commands.Table3.DDR2SDRAM CommandsCommand FunctionACTV Activates the selected bank and row.DCAB Precharge all command.Deactivates(precharges)all banks.DEAC Precharge single command.Deactivates(precharges)a single bank.DESEL Device Deselect.EMRS Extended Mode Register set.Allows altering the contents of the mode register.MRS Mode register set.Allows altering the contents of the mode register.NOP No operation.Power Down Power down mode.READ Inputs the starting column address and begins the read operation.READ with Inputs the starting column address and begins the read operation.The read operation is followed by aautoprecharge precharge.REFR Autorefresh cycle.SLFREFR Self-refresh mode.WRT Inputs the starting column address and begins the write operation.WRT with Inputs the starting column address and begins the write operation.The write operation is followed by aautoprecharge precharge.Table4.Truth Table for DDR2SDRAM CommandsDDR2SDRAM:CKE CS RAS CAS WE BA[2:0]A[12:11,9:0]A10 DDR2memorycontroller:DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_BA[2:0]DDR_A[12:11,9:0]DDR_A[10] PreviousCycles Current CycleACTV H H L L H H Bank Row AddressDCAB H H L L H L X X LDEAC H H L L H L Bank X LMRS H H L L L L BA OP CodeEMRS H H L L L L BA OP CodeREAD H H L H L H BA Column Address LREAD with H H L H L H BA Column Address HprechargeWRT H H L H L L BA Column Address LWRT with H H L H L L BA Column Address LprechargeREFR H H L L L H X X XSLFREFR H L L L L H X X XentrySLFREFR L H H X X X X X XexitL H H H X X X NOP H X L H H H X X XDESEL H X H X X X X X XPower Down H L H X X X X X XentryL H H H X X X Power Down L H H X X X X X XexitL H H H X X X12DDR2Memory Controller SPRUEM4A–November20072.4.1RefreshModeDDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[12:0]DDR_BA[2:0]DDR_DQM[3:0]DDR_CLK Peripheral ArchitectureThe DDR2memory controller issues refresh commands to the DDR2SDRAM memory (Figure 4).REFR is automatically preceded by a DCAB command,ensuring the deactivation of all CE banks selected.Following the DCAB command,the DDR2memory controller begins performing refreshes at a rate defined by the refresh rate (RR)bit in the SDRAM refresh control register (SDRCR).Page information is always invalid before and after a REFR command;thus,a refresh cycle always forces a page miss.This type of refresh cycle is often called autorefresh.Autorefresh commands may not be disabled within the DDR2memory controller.See Section 2.9for more details on REFR command scheduling.Figure 4.Refresh Command2.4.2Deactivation (DCAB andDEAC)DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WEDDR_A[12,11, 9:0]DDR_BA[2:0]DDR_DQM[3:0]DDR_A[10]DDR_CAS DDR_CLK Peripheral ArchitectureThe precharge all banks command (DCAB)is performed after a reset to the DDR2memory controller or following the initialization sequence.DDR2SDRAMs also require this cycle prior to a refresh (REFR)and mode set register commands (MRS and EMRS).During a DCAB command,DDR_A[10]is driven high to ensure the deactivation of all banks.Figure 5shows the timing diagram for a DCAB command.Figure 5.DCAB Command14DDR2Memory ControllerSPRUEM4A–November 2007DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WEDDR_A[12,11, 9:0]DDR_BA[2:0]DDR_DQM[3:0]DDR_A[10]DDR_CAS DDR_CLK Peripheral ArchitectureThe DEAC command closes a single bank of memory specified by the bank select signals.Figure 6shows the timings diagram for a DEAC command.Figure 6.DEAC Command2.4.3Activation(ACTV)DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_WEDDR_BA[2:0]DDR_DQM[3:0]DDR_A[12:0]DDR_CAS DDR_CLK Peripheral ArchitectureThe DDR2memory controller automatically issues the activate (ACTV)command before a read or write to a closed row of memory.The ACTV command opens a row of memory,allowing future accesses (reads or writes)with minimum latency.The value of DDR_BA[2:0]selects the bank and the value of A[12:0]selects the row.When the DDR2memory controller issues an ACTV command,a delay of t RCD is incurred before a read or write command is issued.Figure 7shows an example of an ACTV command.Reads or writes to the currently active row and bank of can achieve much higher throughput than reads or writes to random areas because every time a new row is accessed,the ACTV command must be issued and a delay of t RCD incurred.Figure 7.ACTV CommandDDR2Memory Controller16SPRUEM4A–November 20072.4.4READ CommandDDR_CLK DDR_CKE DDR_CS DDR_WE DDR_CAS DDR_DQM[3:0]DDR_D[31:0]DDR_A[12:0]DDR_RAS DDR_DQS[3:0]DDR_A[10]DDR_BA[2:0]DDR_CLK Peripheral ArchitectureFigure 8shows the DDR2memory controller performing a read burst from DDR2SDRAM.The READ initiates a burst read operation to an active row.During the READ command,DDR_CAS drives low,DDR_WE and DDR_RAS remain high,the column address is driven on DDR_A[12:0],and the bank address is driven on DDR_BA[2:0].The DDR2memory controller uses a burst length of 8,and has a programmable CAS latency of 2,3,4,or 5.The CAS latency is three cycles in Figure 8.Read latency is equal to CAS latency plus additive latency.The DDR2memory controller always the memory to have an additive latency of 0,so read latency equals CAS latency.Since the default burst size is 8,the DDR2memory controller returns 8pieces of data for every read command.If additional accesses are not pending to the DDR2memory controller,the read burst completes and the unneeded data is disregarded.If additional accesses are pending,depending on the scheduling result,the DDR2memory controller can terminate the read burst and start a new read burst.Furthermore,the DDR2memory controller does not issue a DAB/DEAC command until page information becomes invalid.Figure 8.DDR2READ Command2.4.5Write (WRT)CommandDDR_CLK DDR_CKEDDR_CSDDR_WE DDR_CAS DDR_DQM[3:0]DDR_D[31:0]DDR_A[12:0]DDR_RASDDR_DQS[3:0]DDR_A[10]DDR_BA[2:0]DDR_CLKPeripheral ArchitecturePrior to a WRT command,the desired bank and row are activated by the ACTV command.Following the WRT command,a write latency is incurred.Write latency is equal to CAS latency minus 1.All writes have a burst length of 8.The use of the DDR_DQM outputs allows byte and halfword writes to be executed.Figure 9shows the timing for a write on the DDR2memory controller.If the transfer request is for less than 8words,depending on the scheduling result and the pending commands,the DDR2memory controller can:•Mask out the additional data using DDR_DQM outputs •Terminate the write burst and start a new write burstThe DDR2memory controller does not perform the DEAC command until page information becomes invalid.Figure 9.DDR2WRT CommandDDR2Memory Controller18SPRUEM4A–November 20072.4.6Mode Register Set (MRS and EMRS)DDR_CLK DDR_CKE DDR_CSDDR_RAS DDR_WEDDR_BA[2:0]DDR_A[12:0]DDR_CAS DDR_CLK Peripheral ArchitectureDDR2SDRAM contains mode and extended mode registers that configure the DDR2memory foroperation.These registers control burst type,burst length,CAS latency,DLL enable/disable (on DDR2device),single-ended strobe,etc.The DDR2memory controller programs the mode and extended mode registers of the DDR2memory by issuing MRS and EMRS commands.When the MRS or EMRS command is executed,the value on DDR_BA[1:0]selects the mode register to be written and the data on DDR_A[12:0]is loaded into the register.Figure 10shows the timing for an MRS and EMRS command.The DDR2memory controller only issues MRS and EMRS commands during the DDR2memory controller initialization sequence.See Section 2.13for more information.Figure 10.DDR2MRS and EMRS Command2.5Memory Width and Byte AlignmentDDR2 memory controller data busDDR_D[31:24]DDR_D[23:16]DDR_D[15:8]DDR_D[7:0]32-bit memory device16-bit memory devicePeripheral ArchitectureThe DDR2memory controller supports memory widths of 16bits and 32bits.Table 5summarizes the addressable memory ranges on the DDR2memory controller.See the data manual for the memory widths that are supported.Both big-endian and little-endian formats are supported.Figure 11shows the byte lanes used on the DDR2memory controller.The external memory is always on the data bus.Table 5.Addressable Memory RangesMemory Width Maximum addressable bytes per CS space Description ×16128Mbytes Halfword address ×32256MbytesWord addressFigure 11.Byte Alignment (Little-Endian Mode)DDR2Memory Controller20SPRUEM4A–November 2007Peripheral Architecture 2.6Endianness SupportThe DDR2memory controller supports both big-endian and little-endian operating modes.The endianness mode selection at the time of an access determines the order in which data on the internal data bus iswritten to or read from devices that are not as wide as the internal data bus.However,the DDR2memory controller maintains the natural order of endian operations.That is,a stream of data starting at anyaddress N within any endian environment will always be accessed in the correct or incrementing dataorder.The DDR2memory controller will always access address N prior to N+1in all endian modes and in any data width.Table6and Table7show operation of the DDR2memory controller for both16-bit and 32-bit external both and little-endian modes.See the device-specific data manual for the memory widths that are supported.Since the endianness mode must be determined prior to bootloading,the endian mode selection is latched in the Boot Configuration(BOOTCFG)register when the device is reset.This endianness mode selection is also reflected in the BE bit in the SDRAM status register(SDRSTAT).Table6.16-Bit External MemoryBig-Endian Mode Little-Endian Mode Internal Data(64-Bit)DDR_A[2:1]DDR_D[15:0]DDR_A[2:1]DDR_D[15:0] 0123456789AB CDEFh000123h00CDEFh0123456789AB CDEFh014567h0189ABh0123456789AB CDEFh1089ABh104567h0123456789AB CDEFh11CDEFh110123hTable7.32-Bit External MemoryBig-Endian Mode Little-Endian Mode Internal Data(64-Bit)DDR_A[2]DDR_D[31:0]DDR_A[2]DDR_D[31:0] 0123456789AB CDEFh089AB CDEFh089AB CDEFh 0123456789AB CDEFh101234567h101234567h Peripheral Architecture2.7Address MappingThe DDR2memory controller views external DDR2SDRAM as one continuous block of memory.Thisstatement is true regardless of the number of external physical devices mapped to a given chip selectspace.The DDR2memory controller receives DDR2memory access requests along with a32-bit logical address from the rest of the system.In turn,the DDR2memory controller uses the logical address togenerate a row/page,column,and bank address for the DDR2SDRAM.The number of column and bank address bits used is determined by the IBANK and PAGESIZE fields in the SDRAM bank configuration register(SDBCR)(see Table8).Table8.Bank Configuration Register Fields for Address Mapping Bit Field Bit Value Bit DescriptionIBANK Defines the number of internal banks on the external DDR2memory.01bank1h2banks2h4banks3h8banksPAGESIZE Defines the page size of each page of the external DDR2memory.0256words(requires8column address bits)1h512words(requires9column address bits)2h1024words(requires10column address bits)3h2048words(requires11column address bits)As stated in Table8,the IBANK and PAGESIZE fields of SDBCR control the mapping of the logical,source DDR2memory controller to the DDR2SDRAM row,column,and bank address bits.The DDR2memory controller logical address always contains13row address bits,whereas the number of column and bank bits are determined by the IBANK and PAGESIZE fields.Table9and Table10show how the logical address bits map to the DDR2SDRAM row,column,and for of IBANK and PAGESIZE values.The same DDR2memory controller pins provide the row and columnaddress to the DDR2SDRAM,thus the DDR2memory controller appropriately shifts the address during row and column address selection.Figure12shows how this address-mapping scheme organizes the DDR2SDRAM rows,columns,and the device memory map.Note that during a linear access,the DDR2memory controller increments the column address as the logical address increments.When the DDR2memory controller reaches a page/row boundary,it moves onto the same page/row in the next bank.This movementcontinues until the same page has been accessed in all banks.To the DDR2SDRAM,this process looks as shown in Figure13.By traversing across banks while remaining on the same row/page,the DDR2memory controllermaximizes the number of activated banks for a linear access.This results in the maximum number ofopen pages when performing a linear access being equal to the number of banks.Note that the DDR2 memory controller never opens more than one page per bank.Ending the current access is not a condition that forces the active DDR2SDRAM row to be closed.The DDR2memory controller leaves the active row open until it becomes necessary to close it.This decreases the deactivate-reactivate overhead.22DDR2Memory Controller SPRUEM4A–November2007。