74LCXH2245中文资料
74LVT2245D-T中文资料
19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7 mna817
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mna818
Fig 2. IEC logic symbol
SOT339-1
plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74LVTH2245PW −40 °C to +85 °C TSSOP20
Description
Version
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
plastic shrink small outline package; 20 leads; body width 5.3 mm
The 74LVT2245; 74LVTH2245 is designed with 30 Ω series resistance in both the HIGH-state and LOW-state of the output. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers and transmitters.
74LVXC3245中文资料
© 2003 Fairchild Semiconductor Corporation DS012008February 1994Revised October 200374LVXC3245 8-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE Outputs74LVXC32458-Bit Dual Supply Configurable Voltage Interface Transceiver with 3-STATE OutputsGeneral DescriptionThe LVXC3245 is a 24-pin dual-supply, 8-bit configurable voltage interface transceiver suited for PCMCIA and other real time configurable I/O applications. The V CCA pin accepts a 3V supply level. The A Port is a dedicated 3V port. The V CCB pin accepts a 3V-to-5V supply level. The B Port is configured to track the V CCB supply level respec-tively. A 5V level on the V CC pin will configure the I/O pins at a 5V level and a 3V V CC will configure the I/O pins at a 3V level. The A Port should interface with a 3V host system and the B Port to the card slots. This device will allow the V CCB voltage source pin and I/O pins on the B Port to float when OE is HIGH. This feature is necessary to buffer data to and from a PCMCIA socket that permits PCMCIA cards to be inserted and removed during normal operation.Featuress Bidirectional interface between 3V and 3V-to-5V buses s Control inputs compatible with TTL level s Outputs source/sink up to 24 mAs Guaranteed simultaneous switching noise level and dynamic threshold performance s Implements patented EMI reduction circuitry s Flexible V CCB operating ranges Allows B Port and V CCB to float simultaneously when OE is HIGH s Functionally compatible with the 74 series 245Ordering Code:Devices also available in T ape and Reel. Specify by appending suffix letter “X” to the ordering code.Logic Symbol Pin DescriptionsConnection DiagramOrder Number Package NumberPackage Description74LVXC3245WM M24B 224-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVXC3245QSC MQA2424-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 74LVXC3245MTCMTC2424-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin NamesDescriptionOE Output Enable Input T/R Transmit/Receive InputA 0–A 7Side A Inputs or 3-STATE OutputsB 0–B 7Side B Inputs or 3-STATE Outputs 274L V X C 3245Truth TableH= HIGH Voltage Level L = LOW Voltage Level X = ImmaterialLogic DiagramInputs OutputsOE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B HXHIGH-Z State74LVXC3245Absolute Maximum Ratings (Note 1)Recommended Operating Conditions (Note 2)Note 1: The “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions ” table will define the conditions for actual device operation.Note 2: The A Port unused pins (inputs or I/Os) must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsSupply Voltage (V CCA , V CCB )−0.5V to +7.0V DC Input Voltage (V I ) @ OE, T/R −0.5V to V CCA +0.5V DC Input/Output Voltage (V I/O )@ A n −0.5V to V CCA +0.5V @ B n−0.5V to V CCB +0.5VDC Input Diode Current (I IK )@ OE, T/R±20 mA DC Output Diode (I OK ) Current ±50 mA DC Output Source or Sink Current (I O )±50 mA DC V CC or Ground Current per Output Pin (I CC or I GND )±50 mA and Max Current±200 mAStorage Temperature Range (T STG )−65°C to +150°CDC Latch-Up Source or Sink Current±300 mASupply Voltage V CCA 2.7V to 3.6V V CCB3.0V to 5.5V Input Voltage (V I ) @ OE, T/R 0V to V CCA Input Output Voltage (V I/O )@ A n 0V to V CCA @ B n0V to V CCBFree Air Operating Temperature (T A )−40°C to +85°CMinimum Input Edge Rate (∆V/∆t)8 ns/VV IN from 30% to 70% of V CC V CC @ 3.0V, 4.5V, 5.5VSymbol ParameterV CCA V CCB T A = 25°C T A = −40°C to +85°C UnitsConditions(V)(V)TypGuaranteed LimitsV IHAMinimum HIGH A n , 2.7 3.0 2.0 2.0V V OUT ≤ 0.1V Level Input OE 3.0 3.6 2.0 2.0orVoltageT/R 3.6 5.5 2.0 2.0≥V CC − 0.1VV IHBB n2.73.0 2.0 2.03.0 3.6 2.0 2.03.65.5 3.85 3.85V ILAMaximum LOW A n , 2.7 3.00.80.8VV OUT ≤ 0.1V Level Input OE 3.0 3.60.80.8orVoltageT/R 3.6 5.50.80.8≥V CC − 0.1V V ILBB n2.73.00.80.83.0 3.60.80.83.65.5 1.65 1.65V OHAMinimum HIGH Level 3.0 3.0 2.99 2.9 2.9VI OUT = −100 µA Output Voltage3.0 3.0 2.85 2.56 2.46I OH = −12 mA 3.0 3.0 2.65 2.35 2.25I OH = −24 mA 2.7 3.0 2.5 2.3 2.2I OH = −12 mA 2.74.5 2.3 2.1 2.0I OH = −24 mA V OHB3.0 3.0 2.99 2.9 2.9V I OUT = −100 µA 3.0 3.0 2.85 2.56 2.46I OH = −12 mA 3.0 3.0 2.65 2.35 2.25I OH = −24 mA 3.04.5 4.25 3.86 3.76I OH = −24 mA V OLAMaximum LOW Level 3.0 3.00.0020.10.1V I OUT = 100 µA Output Voltage3.0 3.00.210.360.44I OL = 24 mA 2.7 3.00.110.360.44I OL = 12 mA 2.74.50.220.420.5I OL = 24 mA V OLB3.0 3.00.0020.10.1V I OUT = 100 µA 3.0 3.00.210.360.44I OL = 24 mA 3.04.50.180.360.44I OL = 24 mA I INMaximum Input 3.6 3.6±0.1±1.0µA V I = V CCA , GND Leakage Current @ 3.65.5±0.1±1.0OE, T/R 474L V X C 3245DC Electrical Characteristics (Continued)Note 3: Worst case package.Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to V CC level; one output at GND.Note 5: Max number of Data Inputs (n) switching. (n –1) inputs switching 0V to V CC level. Input-under-test switching: V CC level to threshold (V IHD ), 0V to threshold (V ILD ), f = 1 MHz.Symbol ParameterV CCA V CCB T A = 25°C T A = −40°C to +85°C Units Conditions(V)(V)TypGuaranteed LimitsI OZAMaximum 3-STATE 3.6 3.6±0.5±5.0µA V I = V IL , V IH ,Output Leakage 3.6 5.5±0.5±5.0OE = V CCA @ A nV O = V CCA , GND I OZBMaximum 3-STATE 3.6 3.6±0.5±5.0µA V I = V IL , V IH ,Output Leakage 3.65.5±0.5±5.0OE = V CCA @ B nV O = V CCB , GND ∆I CC Maximum B n 3.6 5.5 1.01.35 1.5mAV I = V CCB –2.1V I CC /Input All Inputs3.6 3.60.350.5V I = V CC –0.6V I CCA1Quiescent V CCA A n = V CCA or GND Supply Current 3.6Open550µAB n = Open, OE = V CCA ,as B Port FloatsT/R = V CCA , V CCB = OpenI CCA2Quiescent V CCA 3.6 3.6550µAA n = V CCA or GND,Supply Current3.6 5.5550B n = V CCB or GND,OE = GND, T/R = GND I CCBQuiescent V CCB 3.6 3.6550µA A n = V CCA or GND,Supply Current3.6 5.5880B n = V CCB or GND,OE = GND, T/R = V CCAV OLPA Quiet Output 3.3 3.30.8V (Note 3)(Note 4)Maximum Dynamic 3.3 5.00.8V OLPB V OL3.3 3.30.8V (Note 3)(Note 4)3.3 5.0 1.5V OLVA Quiet Output 3.3 3.3−0.8V (Note 3)(Note 4)Minimum Dynamic 3.3 5.0−0.8V OLVB V OL3.3 3.3−0.8V (Note 3)(Note 4)3.3 5.0−1.2V IHDA Minimum HIGH 3.3 3.3 2.0V (Note 3)(Note 5)Level Dynamic 3.3 5.0 2.0V IHDB Input Voltage 3.3 3.3 2.0V (Note 3)(Note 5)3.3 5.0 3.5V ILDA Maximum LOW 3.3 3.30.8V (Note 3)(Note 5)Level Dynamic 3.3 5.00.8V ILDBInput Voltage3.3 3.30.8V(Note 3)(Note 5)3.35.01.574LVXC3245AC Electrical CharacteristicsNote 6: Typical values at V CCA = 3.3V, V CCB = 5.0V @ 25°C.Note 7: Typical values at V CCA = 3.3V, V CCB = 3.3V @ 25°C.Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ). Parameter guaranteed by design.CapacitanceNote 9: C PD is measured at 10 MHz.SymbolParameterT A = +25°C T A = −40°C to +85°CT A = +25°C T A = −40°C to +85°CUnitsC L = 50 pFC L = 50 pF C L = 50 pF C L = 50 pF V CCA = 2.7V–3.6V V CCA = 2.7V–3.6V V CCA = 2.7V–3.6V V CCA = 2.7V–3.6V V CCB = 4.5V–5.5V V CCB = 4.5V–5.5V V CCB = 3.0V–3.6V V CCB = 3.0V–3.6V MinTyp Max Min Max Min Typ Max Min Max (Note 6)(Note 7)t PHL Propagation Delay 1.0 4.88.0 1.08.5 1.0 5.58.5 1.09.0ns t PLH A to B1.0 3.9 6.5 1.07.0 1.0 5.28.0 1.08.5t PHL Propagation Delay 1.0 3.8 6.5 1.07.0 1.0 4.47.0 1.07.5ns t PLH B to A1.0 4.37.5 1.08.0 1.0 5.17.5 1.08.0t PZL Output Enable Time 1.0 4.78.0 1.08.5 1.0 6.09.0 1.09.5ns t PZH OE to B1.0 4.88.5 1.09.0 1.0 6.19.5 1.010.0t PZL Output Enable Time 1.0 5.99.5 1.010.0 1.0 6.410.0 1.010.5ns t PZH OE to A1.0 5.49.0 1.09.5 1.0 5.89.0 1.09.5t PHZ Output Disable Time 1.0 4.08.0 1.08.5 1.0 6.39.5 1.010.0ns t PLZ OE to B1.0 3.87.5 1.08.0 1.0 4.58.0 1.08.5t PHZ Output Disable Time 1.0 4.69.5 1.010.0 1.0 5.29.5 1.010.0nst PLZ OE to A 1.03.1 6.5 1.07.0 1.03.4 6.5 1.07.0t OSHL Output to Output t OSLHSkew (Note 8) 1.01.51.51.01.51.5nsData to OutputSymbol Parameter Typ Units ConditionsC IN Input Capacitance 4.5pF V CC = Open C I/O Input/Output Capacitance 10pF V CCA = 3.3V V CCB = 5.0V C PDPower Dissipation A →B 50pF V CCB = 5.0V Capacitance (Note 9)B →A40pFV CCA = 3.3V 674L V X C 3245Power Up ConsiderationsTo insure the system does not experience unnecessary I CC current draw, bus contention, or oscillations during power up, the following guidelines should be adhered to (refer to Table 1):•Power up the control side of the device first. This is the V CCA side.•OE should ramp with or ahead of V CCA . This will help guard against bus contention.•The Transmit/Receive control pin (T/R) should ramp with V CCA , this will ensure that the A Port data pins are con-figured as inputs. With V CCA receiving power first, the A I/O Port should be configured as inputs to help guard against bus contention and oscillations.• A side data inputs should be driven to a valid logic level.This will prevent excessive current draw.The above steps will ensure that no bus contention or oscil-lations, and therefore no excessive current draw occurs during the power up cycling of these devices. These steps will help prevent possible damage to the translator devices and potential damage to other system components.TABLE 1. Low Voltage Translator Power Up Sequencing TablePlease reference Application Note AN-5001 for more detailed information on using Fairchild ’s LVX Low Voltage Dual Supply CMOS Translating Transceivers.Configurable I/O Application for PCMCIA Cards Block DiagramThe LVXC3245 is a 24-pin dual supply device well suited for PCMCIA configurable I/O applications. Ideal for low power notebook designs, the LVXC3245 consumes less than 1mW of quiescent power in all modes of operation.The LVXC3245 meets all PCMCIA I/O voltage require-ments at 5V and 3.3V operation. By tying V CCB of the LVXC3245 to the card voltage supply, the PCMCIA cardwill always experience rail to rail output swings, maximizing the reliability of the interface.The V CCA pin on the LVXC3245 must always be tied to a 3V power supply. This voltage connection provides internal references needed to account for variations in V CCB . When connected as in the figure above, the LVXC3245 meets all the voltage and current requirements of the ISA bus stan-dard (IEEE P996).Device Type V CCA V CCB T/R OE A Side I/O B Side I/O Floatable Pin Allowed 74LVXC32453V 3V to 5.5V ramp ramp logic outputsyes, V CCB and B (power up 1st)configurablewith V CCAwith V CCA0V or V CCAI/O ’s w/ OE HIGH74LVXC3245Physical Dimensions inches (millimeters) unless otherwise noted24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M24B24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" WidePackage Number MQA24874L V X C 3245 8-B i t D u a l S u p p l y C o n f i g u r a b l e V o l t a g e I n t e r f a c e T r a n s c e i v e r w i t h 3-S T A T E O u t p u t sPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC24Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
MC74LCX244 低电压三态非反转八路缓冲器说明书
MC74LCX244Octal Buffer, Non-Inverting, Low Voltage, 3-StateThe MC74LCX244 is a high performance, non−inverting octal buffer operating from a 2.3 to 5.5 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows MC74LCX244 inputs to be safely driven from 5 V devices. The MC74LCX244 is suitable for memory address driving and all TTL level bus oriented transceiver applications.Current drive capability is 24 mA at the outputs. The Output Enable (OE) input, when HIGH, disables the output by placing them in a HIGH Z condition.Features•Designed for 2.3 to 5.5 V V CC Operation•5 V Tolerant − Interface Capability With 5 V TTL Logic •Supports Live Insertion and Withdrawal•I OFF Specification Guarantees High Impedance When V CC = 0 V •LVTTL Compatible•LVCMOS Compatible•24 mA Balanced Output Sink and Source Capability•Near Zero Static Supply Current in All Three Logic States (10 m A) Substantially Reduces System Power Requirements •Latchup Performance Exceeds 500 mA•ESD Performance:♦Human Body Model >2000 V♦Machine Model >200 V•NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant120MARKING DIAGRAMSA=Assembly LocationL, WL=Wafer LotY, YY=YearW, WW=Work WeekG or G=Pb−Free PackageSOIC−20 WBDW SUFFIXCASE 751DLCX244AWLYYWWGLCX244ALYW GGTSSOP−20DT SUFFIXCASE 948E201See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.ORDERING INFORMATION(Note: Microdot may be in either location)QFN20MN SUFFIXCASES 485AA& 485CBLCX244ALYW GGSOIC−20 WBTSSOP−20QFN20 − 485AA QFN20 − 485CB244ALYW GGFigure 1. Pinouts: 20−Lead (Top View)H = High Voltage Level L = Low Voltage Level Z = High Impedance StateX = High or Low Voltage Level and Transitions are Acceptable For I CC reasons, DO NOT FLOAT InputsFigure 2. Logic Diagram192018171615142134567V CC 13812911102OE 1O02D01O12D11O22D21O32D31OE1D02O01D12O11D22O21D32O3GND1OE1D01O01D11O11D21O21D31O32OE 2D02O02D12O12D22O22D32O3PIN #1291912201011QFNMAXIMUM RATINGSSymbol Parameter Value Condition Units V CC DC Supply Voltage−0.5 to +7.0V V I DC Input Voltage−0.5 ≤ V I≤ +7.0V V O DC Output Voltage−0.5 ≤ V O≤ +7.0Output in 3−State V−0.5 ≤ V O≤ V CC + 0.5Output in HIGH or LOW State (Note 1)VI IK DC Input Diode Current−50V I < GND mAI OK DC Output Diode Current−50V O < GND mA+50V O > V CC mAI O DC Output Source/Sink Current±50mAI CC DC Supply Current Per Supply Pin±100mAI GND DC Ground Current Per Ground Pin±100mAT STG Storage Temperature Range−65 to +150°C T L Lead Temperature, 1 mm from Casefor 10 SecondsT L = 260°C T J Junction Temperature Under Bias T J = 150°C q JA Thermal Resistance (Note 2)q JA = 140°C/W MSL Moisture Sensitivity Level 1Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.1.I O absolute maximum rating must be observed.2.Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow. RECOMMENDED OPERATING CONDITIONSSymbol Parameter Min Typ Max Units V CC Supply VoltageOperatingData Retention Only 2.01.52.5,3.32.5,3.35.55.5VV I Input Voltage0 5.5V V O Output VoltageHIGH or LOW State 3−State 0V CC5.5VI OH HIGH Level Output CurrentV CC = 3.0 V − 3.6 V V CC = 2.7 V − 3.0 V −24−12mAI OL LOW Level Output CurrentV CC = 3.0 V − 3.6 V V CC = 2.7 V − 3.0 V 2412mAT A Operating Free−Air Temperature−55+125°CD t/D V Input Transition Rise or Fall Rate, V IN from 0.8 V to 2.0 V, V CC = 3.0 V010ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.DC ELECTRICAL CHARACTERISTICST A = −55°C to +125°CSymbol Characteristic Condition Min Max Units V IH HIGH Level Input Voltage (Note 3) 2.3 V ≤ V CC≤ 2.7 V 1.7V2.7 V ≤ V CC≤3.6 V 2.0V IL LOW Level Input Voltage (Note 3) 2.3 V ≤ V CC≤ 2.7 V0.7V2.7 V ≤ V CC≤3.6 V0.8V OH HIGH Level Output Voltage 2.3 V ≤ V CC≤ 3.6 V; I OL = 100 m A V CC−0.2VV CC = 2.3 V; I OH = −8 mA 1.8V CC = 2.7 V; I OH = −12 mA 2.2V CC = 3.0 V; I OH = −18 mA 2.4V CC = 3.0 V; I OH = −24 mA 2.2 V OL LOW Level Output Voltage 2.3 V ≤ V CC≤ 3.6 V; I OL = 100 m A0.2VV CC = 2.3 V; I OL = 8 mA0.6V CC = 2.7 V; I OL = 12 mA0.4V CC = 3.0 V; I OL = 16 mA0.4V CC = 3.0 V; I OL = 24 mA0.55I OZ3−State Output Current V CC = 3.6 V, V IN = V IH or V IL,V OUT = 0 to 5.5 V±5m AI OFF Power Off Leakage Current V CC = 0, V IN = 5.5 V or V OUT = 5.5 V10m AI IN Input Leakage Current V CC = 3.6 V, V IN = 5.5 V or GND±5m AI CC Quiescent Supply Current V CC = 3.6 V, V IN = 5.5 V or GND10m AD I CC Increase in I CC per Input 2.3 ≤ V CC≤ 3.6 V; V IH = V CC − 0.6 V500m A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.3.These values of V I are used to test DC electrical characteristics only.AC CHARACTERISTICS(t R = t F = 2.5 ns; R L = 500 W)LimitsT A = −55°C to +125°CV CC = 3.0 V to 3.6 V V CC = 2.7 V V CC = 2.5 V ±0.2C L = 50 pF C L = 50 pF C L = 30 pFSymbol Parameter Waveform Min Max Min Max Min Max Unitst PLH t PHL Propagation DelayInput to Output1 1.51.56.56.51.51.57.57.51.51.57.87.8nst PZH t PZL Output Enable Time toHigh and Low Level2 1.51.58.08.01.51.59.09.01.51.51010nst PHZ t PLZ Output Disable Time FromHigh and Low Level2 1.51.57.07.01.51.58.08.01.51.58.48.4nst OSHL t OSLH Output−to−Output Skew(Note 4)1.01.0ns4.Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t OSHL) or LOW−to−HIGH (t OSLH); parameter guaranteed by design.DYNAMIC SWITCHING CHARACTERISTICST A = +25°CSymbol Characteristic Condition Min Typ Max UnitsV OLP Dynamic LOW Peak Voltage (Note 5)V CC = 3.3 V, C L = 50 pF, V IH = 3.3 V, V IL = 0 VV CC = 2.5 V, C L = 30 pF, V IH = 2.5 V, V IL = 0 V 0.80.6VV OLV Dynamic LOW Valley Voltage (Note 5)V CC = 3.3 V, C L = 50 pF, V IH = 3.3 V, V IL = 0 VV CC = 2.5 V, C L = 30 pF, V IH = 2.5 V, V IL = 0 V −0.8−0.6V5.Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output ismeasured in the LOW state.CAPACITIVE CHARACTERISTICSSymbol ParameterConditionTypical Units C IN Input Capacitance V CC = 3.3 V, V I = 0 V or V CC 7pF C OUT Output CapacitanceV CC = 3.3 V, V I = 0 V or V CC 8pF C PDPower Dissipation Capacitance10 MHz, V CC = 3.3 V, V I = 0 V or V CC25pFV CC0 VV OHV OL1Dn, 2Dn1On, 2OnV CC0 V≈ 0 V1OE, 2OE1On, 2On≈ 3.0 V1On, 2OnFigure 3. AC WaveformsV CCV OH - 0.3 V V OL + 0.3 V GNDWAVEFORM 1 − PROPAGATION DELAYS t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 nsWAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMESt R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 nsSymbol V CC3.3 V ±0.3 V2.7 V 2.5 V ±0.2 VVmi Vmo V HZ V LZ1.5 V 1.5 V V OL + 0.3 V V OH − 0.3 V1.5 V 1.5 V V OL + 0.3 V V OH − 0.3 VV CC /2V CC /2V OL + 0.15 V V OH − 015 VOPENV 6 V GNDTEST SWITCH t PLH , t PHL Opent PZL , t PLZ6 V at V CC = 3.3 ±0.3 V 6 V at V CC = 2.5 ±0.2 VOpen Collector/Drain t PLH and t PHL6 V t PZH , t PHZGNDC L = 50 pF at V CC = 3.3 ±0.3 V or equivalent (includes jig and probe capacitance)C L = 30 pF at V CC = 2.5 ±0.2 V or equivalent (includes jig and probe capacitance)R L = R 1 = 500 W or equivalentR T = Z OUT of pulse generator (typically 50 W )Figure 4. Test CircuitORDERING INFORMATIONDevicePackage Shipping †MC74LCX244DWG SOIC−20 WB (Pb−Free)38 Units / Rail MC74LCX244DWR2G SOIC−20 WB (Pb−Free)1000 / Tape & Reel MC74LCX244DTG TSSOP−20(Pb−Free)75 Units / Rail MC74LCX244DTR2G TSSOP−20(Pb−Free)2500 / Tape & Reel NLV74LCX244DTR2G*TSSOP−20(Pb−Free)2500 / Tape & Reel MC74LCX244MNTWG QFN20, 2.5x4.5(Pb−Free)3000 / Tape & Reel MC74LCX244MN2TWGQFN20, 2.5x3.5(Pb−Free)3000 / Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP CapableQFN20, 2.5x4.5 MMCASE 485AA−01ISSUE BDATE 30 APR 2010DIM MIN MAXMILLIMETERSAA10.000.05A3b0.200.30D 2.50 BSCD20.85 1.15E 4.50 BSCE2e0.50 BSCK0.20---NOTES:1.DIMENSIONING AND TOLERANCING PERASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.DIMENSIONS b APPLIES TO PLATEDTERMINAL AND IS MEASURED BETWEEN0.25 AND 0.30 MM FROM TERMINAL.4.COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.0.20 REF0.80 1.00L0.350.452.853.15GENERIC MARKINGDIAGRAM*XXXX= Specific Device CodeA= Assembly LocationL= Wafer LotY= YearW= Work WeekG= Pb−Free Package*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ G”,may or may not be present.BOTTOM VIEW(Note: Microdot may be in either location)QFN20, 2.5x3.5, 0.4PCASE 485CBISSUE ODATE 25 OCT 2011DIMMIN MAXMILLIMETERSAA10.000.05A3b0.150.25D 2.50 BSCD20.90 1.10E 3.50 BSCE2e0.40 BSCNOTES:1.DIMENSIONING AND TOLERANCING PERASME Y14.5M, 1994.2.CONTROLLING DIMENSION: MILLIMETERS.3.DIMENSIONS b APPLIES TO PLATEDTERMINAL AND IS MEASURED BETWEEN0.15 AND 0.30 MM FROM TERMINAL TIP.4.COPLANARITY APPLIES TO THE EXPOSEDPAD AS WELL AS THE TERMINALS.0.20 REF20X0.80 1.00L0.350.452.00 2.20SCALE 2:1GENERIC MARKINGDIAGRAM*XXXX= Specific Device CodeA= Assembly LocationL= Wafer LotY= YearW= Work WeekG= Pb−Free Package*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ G”,may or may not be present.L1DETAIL ALALTERNATE TERMINALCONSTRUCTIONSDETAIL BALTERNATECONSTRUCTIONS*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*20XDIMENSIONS: MILLIMETERS BOTTOM VIEWL1---0.15(Note: Microdot may be in either location)SOIC −20 WB CASE 751D −05ISSUE HDATE 22 APR 2015SCALE 1:1DIM MIN MAX MILLIMETERS A 2.35 2.65A10.100.25b 0.350.49c 0.230.32D 12.6512.95E 7.407.60e 1.27 BSC H 10.0510.55h 0.250.75L 0.500.90q0 7 NOTES:1.DIMENSIONS ARE IN MILLIMETERS.2.INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.3.DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5.DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION.__XXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = YearWW = Work WeekG= Pb −Free PackageGENERICMARKING DIAGRAM*20XDIMENSIONS: MILLIMETERS*For additional information on our Pb −Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*RECOMMENDED*This information is generic. Please refer to device data sheet for actual part marking.Pb −Free indicator, “G” or microdot “G ”, may or may not be present. Some products may not follow the Generic Marking.TSSOP −20 WB CASE 948E ISSUE DDATE 17 FEB 2016SCALE 2:1DIM A MIN MAX MIN MAX INCHES 6.600.260MILLIMETERS B 4.30 4.500.1690.177C 1.200.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.270.370.0110.015J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSCM0 8 0 8 ____NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSIONSHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BEDETERMINED AT DATUM PLANE −W −.DETAIL E6.400.252------GENERICMARKING DIAGRAM*XXXX XXXX ALYW G G16X0.360.65PITCHSOLDERING FOOTPRINTA = Assembly Location L = Wafer Lot Y = YearW = Work WeekG = Pb −Free Package*This information is generic. Please refer to device data sheet for actual part marking.Pb −Free indicator, “G” or microdot “ G ”,may or may not be present.(Note: Microdot may be in either location)ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor thePUBLICATION ORDERING INFORMATIONTECHNICAL SUPPORT North American Technical Support:Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910LITERATURE FULFILLMENT :Email Requests to:*******************onsemi Website: Europe, Middle East and Africa Technical Support:Phone: 00421 33 790 2910For additional information, please contact your local Sales Representative ◊。
MC74LVXC3245DTR2资料
MC74LVXC3245Configurable Dual Supply Octal Transceiverwith 3−State Outputs for 3 V SystemsThe 74LVXC3245 is a 24−pin dual−supply, octal configurable voltage interface transceiver especially well suited for PCMCIA and other real time configurable I/O applications. The V CCA pin accepts a 3.0 V supply level; the A port is a dedicated 3.0 V port. The V CCB pin accepts a 3.0 V−to−5.0 V supply level. The B port is configured to track the V CCB supply level. A 5.0 V level on the V CCB pin will configure the I/O pins at a 5.0 V level and a 3.0 V V CCB will configure the I/O pins at a 3.0 V level. The A port interfaces with a 3.0 V host system and the B port to the card slots. This device will allow the V CCB voltage source pin and I/O pins on the B port to float when OE is High. This feature is necessary to buffer data to and from a PCMCIA socket that permits PCMCIA cards to be inserted and removed during normal operation. The Transmit/Receive (T/R) input determines the direction of data flow. Transmit (active−High) enables data from the A port to B port. Receive (active−Low) enables data from the B port to the A port.Features•Bidirectional Interface Between 3.0 V and 3.0 V/5.0 V Buses •Control Inputs Compatible with TTL Level •Outputs Source/Sink Up to 24 mA•Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance•Available in SOIC and TSSOP Packages •Flexible V CCB Operating Range•Allows B Port and V CCB to Float Simultaneously When OE is High •Functionally Compatible With the 74 Series 245•Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.MARKING DIAGRAMSSOIC−24See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.ORDERING INFORMATION124LVXC3245AWLYYWW A =Assembly Location WL =Wafer Lot YY =YearWW =Work WeekLVX 3245AWLYYWW124TSSOP−24DT SUFFIX CASE 948HB0B1B2B3B4B5B6B7Figure 2. Logic Diagramand Transitions are Acceptable; for I CC reasons, Do Not Float InputsMAXIMUM RATINGSvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.RECOMMENDED OPERATING CONDITIONSDC ELECTRICAL CHARACTERISTICS2.Max number of outputs defined as (n). Data inputs are driven 0 V to V CC level; one output at GND.3.Max number of data inputs (n) switching. (n−1) inputs switching 0 V to V CC level. Input under test switching: V CC level to threshold (V IHD),0 V to threshold (V ILD), f = 1 MHz.AC ELECTRICAL CHARACTERISTICSCCA CCB5.Typical values at V CCA = 3.3 V, V CCB = 3.3 V at 25°C.6.Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t OSHL) or LOW−to−HIGH (t OSLH); parameter guaranteed by design.CAPACITIVE CHARACTERISTICSORDERING INFORMATIONSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.Figure 3. Block DiagramOPTIONALConfigurable I/O Application for PCMCIA CardsThe 74LVXC3245 is a dual−supply device well suited for PCMCIA configurable I/O applications. The LVXC3245consumes less than 1mW of quiescent power in all modes of operation, making it ideal for low power notebook designs.The L VXC3245 meets all PCMCIA I/O voltage requirements at 5.0 V and 3.3 V operation. By tying the V CCB pin to the card voltage supply, the PCMCIA card will always haverail−to−rail output swings, maximizing the reliability of the interface.The V CCA pin must always be tied to a 3.3 V power supply.This voltage connection provides internal references needed to account for variations in V CCB . When connected as in the figure above, the L VXC3245 meets all the voltage and current requirements of the ISA bus standard (IEEE P996).WAVEFORM 1 − PROPAGATION DELAYS t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 nsV CC0 VV OHV OLAn, BnBn, AnWAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES t R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 nsV CC0 V ≈ 0 VOE, T/RAn, Bn≈ V CC An, BnFigure 4. AC WaveformsV CCV OH − 0.3 V V OL + 0.3 V GNDOPEN2xV CC C L = 50 pF or equivalent (Includes jig and probe capacitance)R L = R 1 = 500 W or equivalentR T = Z OUT of pulse generator (typically 50 W )Figure 5. Test CircuitPACKAGE DIMENSIONSSOIC−24DW SUFFIX CASE 751E−04ISSUE ENOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.DIM MIN MAX MIN MAX INCHESMILLIMETERS A 15.2515.540.6010.612B 7.407.600.2920.299C 2.35 2.650.0930.104D 0.350.490.0140.019F 0.410.900.0160.035G 1.27 BSC 0.050 BSC J 0.230.320.0090.013K 0.130.290.0050.011M 0 8 0 8 P 10.0510.550.3950.415R0.250.750.0100.029____PACKAGE DIMENSIONSTSSOP−24DT SUFFIX CASE 948H−01ISSUE ANOTES:24X REFON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
74系列芯片功能表汇总
74系列芯片功能表汇总74系列标准数字电路功能表——中文资料名称类别功能7400 TTL 2输入端四与非门7401 TTL 集电极开路2输入端四与非门7402 TTL 2输入端四或非门7403 TTL 集电极开路2输入端四与非门7404 TTL 六反相器7405 TTL 集电极开路六反相器7406 TTL 集电极开路六反相高压驱动器7407 TTL 集电极开路六正相高压驱动器7408 TTL 2输入端四与门7409 TTL 集电极开路2输入端四与门7410 TTL 3输入端3与非门74107 TTL 带清除主从双J-K触发器74109 TTL 带预置清除正触发双J-K触发器7411 TTL 3输入端3与门74112 TTL 带预置清除负触发双J-K触发器7412 TTL 开路输出3输入端三与非门74121 TTL 单稳态多谐振荡器74122 TTL 可再触发单稳态多谐振荡器74123 TTL 双可再触发单稳态多谐振荡器74125 TTL 三态输出高有效四总线缓冲门74126 TTL 三态输出低有效四总线缓冲门7413 TTL 4输入端双与非施密特触发器74132 TTL 2输入端四与非施密特触发器74133 TTL 13输入端与非门74136 TTL 四异或门74138 TTL 3-8线译码器/复工器74139 TTL 双2-4线译码器/复工器7414 TTL 六反相施密特触发器74145 TTL BCD—十进制译码/驱动器7415 TTL 开路输出3输入端三与门74150 TTL 16选1数据选择/多路开关74151 TTL 8选1数据选择器74153 TTL 双4选1数据选择器74154 TTL 4线—16线译码器74155 TTL 图腾柱输出译码器/分配器74156 TTL 开路输出译码器/分配器74157 TTL 同相输出四2选1数据选择器74158 TTL 反相输出四2选1数据选择器7416 TTL 开路输出六反相缓冲/驱动器74160 TTL 可预置BCD异步清除计数器74161 TTL 可予制四位二进制异步清除计数器74162 TTL 可预置BCD同步清除计数器74163 TTL 可予制四位二进制同步清除计数器74164 TTL 八位串行入/并行输出移位寄存器74165 TTL 八位并行入/串行输出移位寄存器74166 TTL 八位并入/串出移位寄存器74169 TTL 二进制四位加/减同步计数器7417 TTL 开路输出六同相缓冲/驱动器74170 TTL 开路输出4×4寄存器堆74173 TTL 三态输出四位D型寄存器74174 TTL 带公共时钟和复位六D触发器74175 TTL 带公共时钟和复位四D触发器74180 TTL 9位奇数/偶数发生器/校验器74181 TTL 算术逻辑单元/函数发生器74185 TTL 二进制—BCD代码转换器74190 TTL BCD同步加/减计数器74191 TTL 二进制同步可逆计数器74192 TTL 可预置BCD双时钟可逆计数器74193 TTL 可预置四位二进制双时钟可逆计数器74194 TTL 四位双向通用移位寄存器74195 TTL 四位并行通道移位寄存器74196 TTL 十进制/二-十进制可预置计数锁存器74197 TTL 二进制可预置锁存器/计数器7420 TTL 4输入端双与非门7421 TTL 4输入端双与门7422 TTL 开路输出4输入端双与非门74221 TTL 双/单稳态多谐振荡器74240 TTL 八反相三态缓冲器/线驱动器74241 TTL 八同相三态缓冲器/线驱动器74243 TTL 四同相三态总线收发器74244 TTL 八同相三态缓冲器/线驱动器74245 TTL 八同相三态总线收发器74247 TTL BCD—7段15V输出译码/驱动器74248 TTL BCD—7段译码/升压输出驱动器74249 TTL BCD—7段译码/开路输出驱动器74251 TTL 三态输出8选1数据选择器/复工器74253 TTL 三态输出双4选1数据选择器/复工器74256 TTL 双四位可寻址锁存器74257 TTL 三态原码四2选1数据选择器/复工器74258 TTL 三态反码四2选1数据选择器/复工器74259 TTL 八位可寻址锁存器/3-8线译码器7426 TTL 2输入端高压接口四与非门74260 TTL 5输入端双或非门74266 TTL 2输入端四异或非门7427 TTL 3输入端三或非门74273 TTL 带公共时钟复位八D触发器74279 TTL 四图腾柱输出S-R锁存器7428 TTL 2输入端四或非门缓冲器74283 TTL 4位二进制全加器74290 TTL 二/五分频十进制计数器74293 TTL 二/八分频四位二进制计数器74295 TTL 四位双向通用移位寄存器74298 TTL 四2输入多路带存贮开关74299 TTL 三态输出八位通用移位寄存器7430 TTL 8输入端与非门7432 TTL 2输入端四或门74322 TTL 带符号扩展端八位移位寄存器74323 TTL 三态输出八位双向移位/存贮寄存器7433 TTL 开路输出2输入端四或非缓冲器74347 TTL BCD—7段译码器/驱动器74352 TTL 双4选1数据选择器/复工器74353 TTL 三态输出双4选1数据选择器/复工器74365 TTL 门使能输入三态输出六同相线驱动器74365 TTL 门使能输入三态输出六同相线驱动器74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器74373 TTL 三态同相八D锁存器74374 TTL 三态反相八D锁存器74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D锁存器74378 TTL 单边输出公共使能六D锁存器74379 TTL 双边输出公共使能四D锁存器7438 TTL 开路输出2输入端四与非缓冲器74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器74390 TTL 双十进制计数器74393 TTL 双四位二进制计数器7440 TTL 4输入端双与非缓冲器7442 TTL BCD—十进制代码转换器74352 TTL 双4选1数据选择器/复工器74353 TTL 三态输出双4选1数据选择器/复工器74365 TTL 门使能输入三态输出六同相线驱动器74366 TTL 门使能输入三态输出六反相线驱动器74367 TTL 4/2线使能输入三态六同相线驱动器74368 TTL 4/2线使能输入三态六反相线驱动器7437 TTL 开路输出2输入端四与非缓冲器74373 TTL 三态同相八D锁存器74374 TTL 三态反相八D锁存器74375 TTL 4位双稳态锁存器74377 TTL 单边输出公共使能八D锁存器74378 TTL 单边输出公共使能六D锁存器74379 TTL 双边输出公共使能四D锁存器7438 TTL 开路输出2输入端四与非缓冲器74380 TTL 多功能八进制寄存器7439 TTL 开路输出2输入端四与非缓冲器74390 TTL 双十进制计数器74393 TTL 双四位二进制计数器7440 TTL 4输入端双与非缓冲器7442 TTL BCD—十进制代码转换器74447 TTL BCD—7段译码器/驱动器7445 TTL BCD—十进制代码转换/驱动器74450 TTL 16:1多路转接复用器多工器74451 TTL 双8:1多路转接复用器多工器74453 TTL 四4:1多路转接复用器多工器7446 TTL BCD—7段低有效译码/驱动器74460 TTL 十位比较器74461 TTL 八进制计数器74465 TTL 三态同相2与使能端八总线缓冲器74466 TTL 三态反相2与使能八总线缓冲器74467 TTL 三态同相2使能端八总线缓冲器74468 TTL 三态反相2使能端八总线缓冲器74469 TTL 八位双向计数器7447 TTL BCD—7段高有效译码/驱动器7448 TTL BCD—7段译码器/内部上拉输出驱动74490 TTL 双十进制计数器7449174498 TTL 八进制移位寄存器7450 TTL 2-3/2-2输入端双与或非门74502 TTL 八位逐次逼近寄存器74503 TTL 八位逐次逼近寄存器7451 TTL 2-3/2-2输入端双与或非门74533 TTL 三态反相八D锁存器74534 TTL 三态反相八D锁存器7454 TTL 四路输入与或非门74540 TTL 八位三态反相输出总线缓冲器7455 TTL 4输入端二路输入与或非门74563 TTL 八位三态反相输出触发器74564 TTL 八位三态反相输出D触发器74573 TTL 八位三态输出触发器74574 TTL 八位三态输出D触发器74645 TTL 三态输出八同相总线传送接收器74670 TTL 三态输出4×4寄存器堆7473 TTL 带清除负触发双J-K触发器7474 TTL 带置位复位正触发双D触发器7476 TTL 带预置清除双J-K触发器7483 TTL 四位二进制快速进位全加器7485 TTL 四位数字比较器7486 TTL 2输入端四异或门7490 TTL 可二/五分频十进制计数器7493 TTL 可二/八分频二进制计数器7495 TTL 四位并行输入\输出移位寄存器7497 TTL 6位同步二进制乘法器常用74系列标准数字电路的中文名称资料器件代号器件名称74 74LS 74HC00 四2输入端与非门√√√01 四2输入端与非门(OC) √√02 四2输入端或非门√√√03 四2输入端与非门(OC) √√04 六反相器√√√05 六反相器(OC) √√06 六高压输出反相器(OC,30V) √√07 六高压输出缓冲,驱动器(OC,30V) √√√08 四2输入端与门√√√09 四2输入端与门(OC) √√√10 三3输入端与非门√√√11 三3输入端与门√√12 三3输入端与非门(OC) √√√13 双4输入端与非门√√√14 六反相器√√√15 三3输入端与门√√16 六高压输出反相器(OC,15V) √17 六高压输出缓冲,驱动器(OC,15V) √20 双4输入端与非门√√√21 双4输入端与门√√√22 双4输入端与非门(OC) √√25 双4输入端或非门(有选通端) √√√26 四2输入端高压输出与非缓冲器√√√27 三3输入端或非门√√√28 四2输入端或非缓冲器√√√30 8输入端与非门√√√32 四2输入端或门√√√33 四2输入端或非缓冲器(OC) √√37 四2输入端与非缓冲器√√38 四2输入端与非缓冲器(OC) √√40 双4输入端与非缓冲器√√√42 4线-10线译码器(BCD输入) √√43 4线-10线译码器(余3码输入) √44 4线-10线译码器(余3葛莱码输入) √48 4线-7段译码器√49 4线-7段译码器√50 双2路2-2输入与或非门√√√√√√51 2路3-3输入,2路2-2输入与或非门52 4路2-3-2-2输入与或门√53 4路2-2-2-2输入与或非门√54 4路2-3-3-2输入与或非门√√55 2路4-4输入与或非门√60 双4输入与扩展器√√61 三3输入与扩展器√62 4路2-3-3-2输入与或扩展器√64 4路4-2-3-2输入与或非门√65 4路4-2-3-2输入与或非门(OC) √70 与门输入J-K触发器√71 与或门输入J-K触发器√72 与门输入J-K触发器√74 双上升沿D型触发器√√78 双D型触发器√√85 四位数值比较器√86 四2输入端异或门√√√87 4位二进制原码/反码√95 4位移位寄存器√101 与或门输入J-K触发器√102 与门输入J-K触发器√107 双主-从J-K触发器√108 双主-从J-K触发器√109 双主-从J-K触发器√110 与门输入J-K触发器√111 双主-从J-K触发器√√112 双下降沿J-K触发器√。
74HC245
74HC245简介：总线驱动器，典型的TTL型三态缓冲门电路。
由于单片机等CPU的数据／地址／控制总线端口都有一定的负载能力，如果负载超过其负载能力，一般应加驱动器。
另外，也可以使用74HC244等其他电路，74HC244比74HC245多了锁存器。
74HC245实物图:引脚定义：第1脚DIR，为输入输出端口转换用，DIR=“1”高电平时信号由“A”端输入“B”端输出，DIR=“0”低电平时信号由“B”端输入“A”端输出。
第2~9脚“A”信号输入输出端，A1=B1、、、、、、A8=B8，A1与B1是一组，如果DIR=“1”OE=“0”则A1输入B1输出，其它类同。
如果DIR=“0”OE=“0”则B1输入A1输出，其它类同。
第11~18脚“B”信号输入输出端，功能与“A”端一样，不再描述。
第19脚OE，使能端，若该脚为“1”A/B端的信号将不导通，只有为“0”时A/B端才被启用，该脚也就是起到开关的作用。
第10脚GND，电源地。
第20脚VCC，电源正极。
TRUTH TABLE真值表H=高电平L=低电平×=不定Absolute Maximum Ratings绝对最大额定值Supply Voltage电源电压(VCC)-0.5 to -7.0VDC Input Voltage DIR and G pins (VIN) 直流输入电压方向和G引脚（输入电压）-1.5 to VCC -1.5VDC Input/Output Voltage (VIN, VOUT)直流输入/输出电压-0.5 to VCC -0.5VClamp Diode Current 钳位二极管电流(ICD)±20 mADC Output Current直流输出电流，每个引脚（输出）±35 mADC VCC or GND Current, per pin (ICC)±70 mAStorage Temperature Range 储存温度范围(TSTG)-65℃ to -150℃Power Dissipation (PD)功耗(Note 3)600 mWS.O. Package only500 mWLead Temperature (TL) (Soldering 10 seconds)260℃74HC245的作用：信号功率放大第1脚DIR，为输入输出端口转换用，DIR=“1”高电平时信号由“A”端输入“B”端输出，DIR=“0”低电平时信号由“B”端输入“A”端输出。
74LVC2245APWDH中文资料
74LVC2245A
handbook, halfpage handbook, halfpage
DIR 1
VCC 20 19 18 17 16 2OE B0 B1 B2 B3 B4 B5 B6
DIR 1 A0 2 A1 3 A2 4 A3 5
20 VCC 19 OE源自A0 A12 3 4 518 B0 17 B1 16 B2 A2 A3 A4
FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • Integrated 30 Ω termination resistors • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION
2245
A4 6 A5 7 A6 8 A7 9 GND 10
MNA363
15 B3 6 7 8 9 14 B4 13 B5 12 B6 11 B7 A7 A5 A6
GND(1)
15 14 13 12 10 Top view GND 11 B7
74HC245详细中文资料
74HC245详细中文资料74HC245是一款高速CMOS器件，74HC2 45引脚兼容低功耗肖特基TTL（LSTTL）系列。
74HC245译码器可接受3位二进制加权地址输入（A0, A1和A2），并当使能时，提供8个互斥的低有效输出（Y0至Y7）。
74HC245特有3个使能输入端：两个低有效（E1和E2）和一个高有效（E3）。
除非E1和E2置低且E3置高，否则74HC138将保持所有输出为高。
利用这种复合使能特性，仅需4片7 4HC245芯片和1个反相器，即可轻松实现并行扩展，组合成为一个1-32（5线到32线）译码器。
任选一个低有效使能输入端作为数据输入，而把其余的使能输入端作为选通端，则74HC245亦可充当一个8输出多路分配器，未使用的使能输入端必须保持绑定在各自合适的高有效或低有效状态。
74HC245与74HC 238逻辑功能一致，只不过74HC138为反相输出。
功能CD74HC245 ，CD74HC238和CD74HCT245， CD74HCT238是高速硅栅CMO S解码器，适合内存地址解码或数据路由应用。
74HC245作用原理于高性能的存贮译码或要求传输延迟时间短的数据传输系统,在高性能存贮器系统中,用这种译码器可以提高译码系统的效率。
将快速赋能电路用于高速存贮器时,译码器的延迟时间和存贮器的赋能时间通常小于存贮器的典型存取时间,这就是说由肖特基钳位的系统译码器所引起的有效系统延迟可以忽略不计。
HC138 按照三位二进制输入码和赋能输入条件,从8 个输出端中译出一个低电平输出。
两个低电平有效的赋能输入端和一个高电平有效的赋能输入端减少了扩展所需要的外接门或倒相器,扩展成24 线译码器不需外接门;扩展成32 线译码器,只需要接一个外接倒相器。
在解调器应用中,赋能输入端可用作数据输入端。
特性复合使能输入，轻松实现扩展兼容JEDEC标准no.7A 存储器芯片译码选择的理想选择低有效互斥输出 ESD保护 HBM EIA/JESD22-A114-C超过2000 V MM EIA/JESD22-A115-A超过200 V 温度范围 -40～+85 ℃ -40～+125 ℃多路分配功能74HC245是一款高速CMOS器件，74HC245引脚兼容低功耗肖特基T TL（LSTTL）系列。
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© 2001 Fairchild Semiconductor Corporation DS500409October 2000Revised September 200174LCXH2245 Low Voltage Bidirectional Transceiver with Bushold and 26Ω Series Resistors in B Outputs74LCXH2245Low Voltage Bidirectional Transceiver with Bushold and 26Ω Series Resistors in B OutputsGeneral DescriptionThe LCXH2245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus ori-ented applications. The device is designed for low voltage (2.5V and 3.3V) V CC applications. The T/R input deter-mines the direction of data flow through the device. The OE input disables both the A and B ports by placing them in a high impedance state. The 26Ω series resistor in the B Port output helps reduce output overshoot and undershoot.The LCXH2245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintain-ing CMOS low power dissipation.The LCXH2245 data inputs include active bushold circuitry,eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.Featuress 5V tolerant control inputss 2.3V–3.6V V CC specifications provideds Bushold on inputs eliminates the need for external pull-up/pull-down resistors s 7.0 ns t PD max (V CC = 3.3V), 10 µA I CC max s Power down high impedance outputs s ±12 mA output drive B Port (V CC = 3.0V)s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s Equivalent 26Ω series resistor on B Port outputs s ESD performance:Human body model > 2000V Machine model > 200VOrdering Code:Devices also available in T ape and Reel. Specify by appending the suffix letter “X ” to the ordering code.Logic Symbol Pin DescriptionsConnection DiagramGTO is a trademark of Fairchild Semiconductor Corporation.Order Number Package NumberPackage Description74LCXH2245WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCXH2245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCXH2245MSA MSA2020-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide74LCXH2245MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin Names DescriptionOE Output Enable Input T/R Transmit/Receive InputA 0–A 7Side A Inputs or 3-STATE Outputs (Bushold)B 0–B 7Side B Inputs or 3-STATE Outputs (Bushold) 274L C X H 2245Truth TableH = HIGH Voltage Level L = LOW Voltage Level X = ImmaterialZ = High ImpedanceLogic DiagramInputsOutputsOE T/R L L Bus B 0 – B 7 Data to Bus A 0 – A 7L H Bus A 0 – A 7 Data to Bus B 0 – B 7HXHIGH Z State on A 0 – A 7, B 0 – B 774LCXH2245Absolute Maximum Ratings (Note 1)Recommended Operating Conditions (Note 3)Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-mended Operating Conditions ” table will define the conditions for actual device operation.Note 2: I O Absolute Maximum Rating must be observed.Note 3: Floating or unused control inputs must be HIGH or LOW.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage−0.5 to +7.0V V I T/R, OE,−0.5 to +7.0VI/O Ports−0.5 to V CC +0.5V O DC Output Voltage −0.5 to V CC + 0.5Output in HIGH or LOW State (Note 2)V I IK DC Input Diode Current −50V I < GND mA I OK DC Output Diode Current −50V O < GND mA +50V O > V CCI O DC Output Source/Sink Current ±50mA I CC DC Supply Current per Supply Pin ±100mA I GND DC Ground Current per Ground Pin ±100mAT STGStorage Temperature−65 to +150°CSymbol ParameterMin Max Units V CC Supply Voltage Operating 2.0 3.6V Data Retention1.5 3.6V I Input Voltage 0V CC V V O Output VoltageHIGH or LOW State0V CC V3-STATE5.5I OH /I OLOutput Current in I OH /I OL - A OutputsV CC = 3.0V − 3.6V ±24mAV CC = 2.7V - 3.0V ±12V CC = 2.3V - 2.7V±8Output Current in I OH /I OL - B OutputsV CC = 3.0V − 3.6V ±12mA V CC = 2.7V - 3.0V ±8V CC = 2.3V - 2.7V±4T AFree-Air Operating Temperature−4085°C ∆t/∆VInput Edge Rate, V IN = 0.8V − 2.0V, V CC = 3.0V10ns/VSymbol ParameterConditionsV CC T A = −40°C to +85°C Units (V)Min MaxV IH HIGH Level Input Voltage 2.3 − 2.7 1.7V 2.7 − 3.6 2.0V IL LOW Level Input Voltage 2.3 − 2.70.7V2.7 -3.60.8V OHHIGH Level Output Voltage I OH = −100 µA 2.3 - 3.6V CC − 0.2VA OutputsI OH = −8 mA 2.3 1.8I OH = −12 mA 2.7 2.2I OH = −16 mA 3.0 2.4I OH = −24 mA3.0 2.2V OHHIGH Level Output Voltage I OH = −100 µA 2.3 - 3.6V CC − 0.2V B OutputsI OH = −4 mA 2.3 1.8I OH = −4 mA 2.7 2.2I OH = −6 mA 3.0 2.4I OH = −8 mA 2.7 2.0I OH = −12 mA3.02.0 474L C X H 2245DC Electrical Characteristics (Continued)Note 4: Outputs disabled or 3-STATE only.Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.AC Electrical CharacteristicsNote 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Symbol ParameterConditionsV CC T A = −40°C to +85°C Units(V)MinMax V OLLOW Level Output Voltage I OL = 100 µA 2.3 − 3.60.2VA OutputsI OL = 8 mA 2.30.6I OL = 12 mA 2.70.4I OL = 16 mA 3.00.4I OL = 24 mA3.00.55V OLLOW Level Output Voltage I OL = 100 µA 2.3 − 3.60.2VB OutputsI OL = 4 mA 2.30.6I OL = 4 mA 2.70.4I OL = 6 mA 3.00.55I OL = 8 mA 2.70.6I OL = 12 mA3.00.8I I Input Leakage Current V I = V CC or GND 2.3 − 3.6±5.0µAI I(HOLD)Bushold Input Minimum V IN = 0.7V 2.345µADrive Hold CurrentV IN = 1.7V −45V IN = 0.8V 3.075V IN = 2.0V−75I I(OD)Bushold Input Over-Drive (Note 5) 2.7300µACurrent to Change State(Note 6)−300(Note 5) 3.6450(Note 6)−450I OZ 3-STATE I/O Leakage V O = V CC or GND 2.3 − 3.6±5.0µA V I = V IH or V IL I CC Quiescent Supply Current V I = V CC or GND2.3 −3.610µA 3.6V ≤ V I , V O ≤ 5.5V (Note 4) 2.3 − 3.6±10∆I CCIncrease in I CC per InputV IH = V CC −0.6V2.3 -3.6500µASymbolParameterT A = −40°C to +85°C, R L = 500ΩUnitsV CC = 3.3V ± 0.3VV CC = 2.7V V CC = 2.5V ± 0.2VC L = 50 pF C L = 50 pF C L = 30 pF MinMax Min Max Min Max t PHL Propagation Delay 1.58.0 1.59.0 1.59.6ns t PLH A to Bt PHL Propagation Delay 1.57.0 1.58.0 1.58.4ns t PLH B to At PZL Output Enable Time 1.59.5 1.510.5 1.511.0ns t PZH A to Bt PZL Output Enable Time 1.58.5 1.59.5 1.510.5ns t PZH B to At PLZ Output Disable Time 1.57.5 1.58.5 1.59.0ns t PHZ A to Bt PLZ Output Disable Time 1.57.5 1.58.51.59.0ns t PHZ B to At OSHL Output to Output Skew 1.0ns t OSLH(Note 7)74LCXH2245Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC (V)T A = 25°C Units Typical V OLPQuiet Output Dynamic Peak V OL C L = 30 pF, V IH = 2.5V, V IL = 0V 2.50.6V B to AC L = 50 pF, V IH =3.3V, V IL = 0V 3.30.8Quiet Output Dynamic Peak V OL C L = 30 pF, V IH = 2.5V, V IL = 0V 2.50.4V A to BC L = 50 pF, V IH = 3.3V, V IL = 0V 3.30.5V OLVQuiet Output Dynamic Valley V OL C L = 30 pF, V IH = 2.5V, V IL = 0V 2.5−0.6V B to AC L = 50 pF, V IH = 3.3V, V IL = 0V 3.3−0.8Quiet Output Dynamic Valley V OL C L = 30 pF, V IH = 2.5V, V IL = 0V 2.5−0.4VA to BC L = 50 pF, V IH = 3.3V, V IL = 0V3.3−0.5Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC = Open, V I = 0V or V CC 7pF C I/O Input/Output Capacitance V CC = 3.3V, V I = 0V or V CC8pF C PDPower Dissipation CapacitanceV CC = 3.3V, V I = 0V or V CC , f = 10 MHz25pF 674L C X H 2245AC LOADING and WAVEFORMS Generic for LCX FamilyFIGURE 1. AC Test Circuit (C L includes probe and jig capacitance)Waveform for Inverting and Non-Inverting FunctionsPropagation Delay. Pulse Width and t rec Waveforms3-STATE Output Low Enable andDisable Times for Logic3-STATE Output High Enable andDisable Times for LogicSetup Time, Hold Time and Recovery Time for Logict rise and t fallFIGURE 2. Waveforms(Input Characteristics; f = 1MHz, t r = t f = 3ns)Test Switch t PLH , t PHL Opent PZL , t PLZ 6V at V CC = 3.3 ± 0.3V; and 2.7V V CC x 2 at V CC = 2.5 ± 0.2Vt PZH , t PHZGNDSymbol V CC3.3V ± 0.3V2.7V 2.5V ± 0.2V V mi 1.5V 1.5V V CC /2V mo 1.5V 1.5V V CC /2V x V OL + 0.3V V OL + 0.3V V OL + 0.15V V yV OH − 0.3VV OH − 0.3VV OH − 0.15V 74LCXH2245Schematic DiagramGeneric for LCXH Family (with Bushold) 874L C X H 2245Physical Dimensionsinches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B 74LCXH2245Physical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm WidePackage Number M20D 1074L C X H 2245Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm WidePackage Number MSA20 74LCXH2245 Low Voltage Bidirectional Transceiver with Bushold and 26ΩSeries Resistors in B OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or 元器件交易网。